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© Digital Equipment Corporation 1997.
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AlphaServer 4000 and 4100 Service Manual

This material provides information needed to service AlphaServer 4000 and 4100 cabinet and pedestal systems.  It is made up of the following sections:

Section	Description
System Overview	Describes the system packaging and components of the system drawer.
FRU Removal and Replacement	Describes removal and replacement of FRUs.
Power-Up Tests	Describes the power-up test flow, and the normal behavior of both LEDs and the console.
Troubleshooting	Describes how to troubleshoot the system using LEDs, diagnostics, and the error log.
FRU List	Lists or points to all FRUs in the system.
Error Registers	Describes CPU and IOD error registers.
Console Command Summary	Gives a brief description of SRM console commands.
Utilities	Describes how to run utility programs to configure devices and to update system firmware.
Environment Variable Summary	Gives a brief description of SRM environment variables.


A FRU is a field-replaceable unit.  It refers to any piece of hardware that can be replaced to fix a system.


AlphaServer systems have two variants:

A pedestal version consists of a single system drawer and up to three StorageWorks shelves.

A cabinet version contains a maximum of four system drawers and two StorageWorks shelves or some combination of these.


A system drawer contains system power, cooling, CPU, memory, control panel, and an I/O subsystem.


System Overview

This section contains descriptions of the following:

System Drawer

The system drawer is the modular building block of the AlphaServer 4000 and 4100 systems.  It contains the system power supplies, the CPU(s), memory, and the I/O subsystem.

System Packaging

AlphaServer 4000 and 4100 systems are available in cabinet or pedestal versions.  The pedestal is a bounded system with one system drawer and up to three StorageWorks options.  The cabinet system can be a combination of system drawers and StorageWorks options that occupy the four or five sections of the cabinet depending upon the cabinet variant.  There are two variants of the pedestal and four variants of the cabinet.

System Architecture

The 4100 uses the Alpha RISC chip for its CPU.  The CPU, memory, and an I/O bridge module to PCI/EISA I/O buses are connected to the system bus motherboard.

System Addressing

AlphaServers use a 40 bit address capable of identifying 1 terabyte locations.  This topic discusses how these locations are organized.

Control Panel Assembly

The control panel assembly consists of the operator control panel (OCP), the CD-ROM, and the floppy.  The OCP contains the On/Off button, the Halt button, the Reset button, and the OCP display.

CPU Types

A number of CPU types are available for AlphaServer 4000 and 4100 systems.  CPUs run at different speeds and come both with and without module-level backup cache.

Memory Types

The 4100 and 4000 systems use a number of different memory modules built with synchronous DRAMs or EDO DRAMs.  Memory modules work in pairs and are of different sizes.  The size of memory module affects physical address mapping.

System Bus

The system bus consists of a 40 bit command/address bus, a 128 plus ECC data bus, and several control signals and clocks.

System Bus to PCI Bus Bridge

The system bus to PCI bus bridge module converts system-bus data addressed to I/O space to PCI commands and data and converts PCI bus data addressed to system memory or CPUs to system bus commands and data.

Power Control Module

The power control module controls the power-up sequence, monitors system power, system temperature, and system fan operation.

PCI I/O Subsystem

The 4100 and 4000 systems use a PCI I/O subsystem.  Two four-slot PCI buses, one that has an EISA bridge and one that does not, enable use of up to eight I/O options on both the 4000 and 4100.  The 4000 can be configured with an additional eight PCI I/O slots.

Server Control Module

The server control module provides remote access to the system, can be powered independently, and has a modem connector.  The module also passes through signals to COM ports 1 and 2, the mouse, keyboard, and parallel port from the PCI motherboard.

Power System

There are two slightly different power systems; one for North America and Japan and another for Europe and AP.  There are also variations for cabinet and pedestal versions of the system.  The power system consists of from one to three power supplies, an AC input box for two of the four cabinet variants, a number of power strips, power cords, and power cables.  For the other two cabinet variants, two power controllers are used between the AC wall outlet and the system drawer power supplies.  A power control module (PCM) senses the system environment and will, if necessary, remove DC power from the system.

Cabinet System Fan Tray

A fan tray, at the top of the cabinet, contains three exhaust fans, a small 12 volt power supply, a power distribution panel, and a fan failure detect module.

Maintenance Bus (I2C bus)

The I2 C bus (spoken of as the I squared C bus) is a small internal maintenance bus used to monitor, fault display, store error state, and track configuration information in the system.


After providing initial data from a memory page (DRAMs that have the same row address), memories made from synchronous DRAMs are approximately five times faster at retrieving subsequent data than memories made from conventional DRAMs.


After providing initial data from a memory page (DRAMs that have the same row address), memories made from EDO DRAMs are approximately 75% faster at retrieving subsequent data than memories made from conventional DRAMs.  EDO stands for extended data out.


System Packaging

The AlphaServer 4100 and 4000 systems come in either a cabinet or a pedestal.

Cabinet System

The cabinet system is an expandable system that has four or five sections depending upon the cabinet variant.  Each section can contain either a system drawer or two StorageWorks options.  At least one system drawer is required, but a cabinet could contain up to three or four system drawers.

Cabinet Variations:

Cabinet	Power	Mounting	Destination
H9A10-EB	AC input box power strips	C channel (max drawers: 4)	North America Japan
H9A10-EC	AC input box power strips	C channel (max drawers: 4)	Europe Asia Pacific
H9A10-EL	Two 120 volt H7600-AA power controllers	Pull-out tray (max drawers: 3)	North America Japan
H9A10-EM	Two 240 volt H7600-DB power controllers	Pull-out tray (max drawers: 3)	Europe Asia Pacific

See AlphaServer 4000/4100 Configuration and Installation for detailed configurations.

Pedestal System

The pedestal system has a single system drawer and up to three StorageWorks options.


Pedestal System Cabinet


Rackmount System Cabinet


System Architecture

The AlphaServer 4000 and 4100 use the same system bus that forms the backbone of the systems.  The AlphaServer 4100 is the compute intensive configuration with up to four CPUs.  The AlphaServer 4000 is the I/O intensive configuration with up to two PCI card cages allowing up to sixteen (16) I/O options.

These systems use the Alpha RISC chip as their processor.  There are two types of CPU modules; one with a B-cache and one without.  The CPU, memory, and an I/O bridge module to PCI/EISA I/O buses are connected to the system bus motherboard.  A fourth type of module, the power control module also connects to the system bus motherboard.  A fully configured 4100 system drawer can have up to four CPUs, four memory pairs, and up to eight I/O options, three of which may be EISA or PCI options and the remaining five PCI options.  A fully configured 4000 system drawer can hav up to two CPUs, two memory pairs, and up to sixteen I/O options, three of which may be EISA or PCI options and the remainint fifteen PCI options.

The system bus has a 144-bit data bus protected by 16 bits of ECC and a 40-bit command/address bus protected by parity.  The bus speed depends on the speed of the CPU in slot 0 which provides the clock for the buses.  The 40-bit address bus can create one terabyte of addresses.  The bus connects CPUs, memory, and the system bus to PCI bus bridge.

The CPU modules are available with and without an external cache.  The Alpha chip has an 8-Kbyte instruction cache (I-cache), an 8-Kbyte write-through data cache (D-cache), and a 96-Kbyte write-back secondary data cache (S-cache).  On-board cache versions of the module have backup data caches (B-caches).  The default cache system is write-back.

The memory modules are placed on the system bus motherboard in pairs.  Each module drives half (72 bits) of the system bus along with the associated ECC bits.  Memory pairs consist of two modules that are the same size and type.  Two types are available:  synchronous and asynchronous.

The system bus to PCI bus bridge module translates system bus commands and data addressed to I/O space to PCI commands and data.  It also translates PCI bus commands and data addressed to system memory or CPUs to system bus commands and data.  The PCI bus is a 64-bit wide bus used for I/O.

The power control module also sits on the system motherboard and monitors power and the system environment.

AlphaServer 4100 Block Diagram
AlphaServer 4000 Block Diagram


System Block Diagram
AlphaServer 4100  Block Diagram


AlphaServer 4000 Block Diagram


Write-through caches propagate all writes through to the next level of memory whether that be another cache or main memory.


Write-back caches write data to the next level of memory whether that be another cache or main memory only when the data is needed by another source.


Memory Types
Memory Types (B3020 or B3030)

In AlphaServer 4000 and 4100 systems, memory nodes are made up of two memory modules.  Memories are made with synchronous or EDO DRAMS and there are several module variants.  Note the memory option is twice the size of the module.

Memory Module Variants:

Module	Size (MB)	DRAM Type	DRAM Number	DRAM Size
B3020-CA	64	Synch	36	4 MB x 4
B3030-EA	256	EDO	144	4 MB x 4
B3030-FA	512	EDO	72	16 MB x 4
B3030-GA	1024	EDO	144	16 MB x 4
Memory Operation

Memory modules are used only in pairs; each module provides half the data, or 64 bits plus 8 ECC bits, of the octaword (16 bytes) transferred on the system bus.  Each of the modules in the memory pair drives 32 data bits and 4 ECC bits; data bits are mixed between modules.  It is not true that the module in slot MEMxL drives the lower 8 bytes, and the module in slot MEMxH drives the higher 8 bytes of the 16 byte transfer. Decoding ECC bits can be used to differentiate between the two memory modules.

Unless otherwise programmed, memory drives the system bus in bursts.  Upon each memory fetch, data is transferred in 4 consecutive cycles transferring 64 bytes.  There are situations, however, when memories made with EDO DRAMs cannot provide data fast enough to complete the system bus transactions.  When these situations arise, EDO type memories assert a signal that causes the system bus to stall for one (occasionally more) clock tick.  When memory completes such an operation, it releases the system bus.

Memory Configuration Rules
Memory Addressing
Memory Module and Placement

For a complete discussion of addressing, see system addressing.


Memory Modules and Placement


Memories of different sizes and types are permitted but:

•	Memory pairs must match - they must be the same size and type.

•	The largest memory pair must be in slots MEM 0L and MEM 0H.

•	Other memory pairs must be the same size or smaller than the first memory pair.

•	Memory pairs must be in consecutive slots.


Memory Addressing

Alpha system memory addressing is unusual because memory address space is determined not by the amount of physical memory but is calculated by a multiple of the size of the memory pair in slot MEM0.  The following applies:

•	Address space is determined by the memory pair in slot MEM0.

•	Multiple memory pairs need not be the same size.

•	The memory pair in slot MEM0 must be the largest of all memory pairs.  Other memory pairs may be as large but none may be larger.

•	The starting address of each memory pair is N times the size of the memory pair in slot MEM0.  N=0,1,2,3.

•	Memory addresses are contiguous within each module pair.

•	If memory pairs are of different sizes, memory "holes" will occur in the physical address space as seen in the figure.

•	Software creates contiguous virtual memory even though physical memory may not be contiguous.

Memory Address Figure
Hexadecimal Address Table


Memory Addressing Figure


MC Bus
System Bus (54-23803-01, 54-23803-02, 54-023805-01)

The system bus (MC bus) connects the CPUs, memory, and the I/O system bus to PCI bus bridge(s).  It is the motherboard for the system drawer.  The power control module also connects to the board.  There are three variants of the system bus motherboard: one for the AlphaServer 4100 (54-23803-01) and the other two for the AlphaServer 4000.

The bus consists of a 40 bit command/address bus, a 128 plus ECC data bus, and several control signals, clocks, and a bus arbiter.  The bus requires that all CPUs have the same high-speed oscillator providing the clock to the Alpha chip.

The system-bus clock depends on the clock of the CPU in slot CPU0.  This clock has a 1:5 ratio to the Alpha chip.  For example, with 300 MHz CPUs, the system bus operates at 60 MHz.

The system bus motherboard initiates memory refresh transactions.

For systems with EV5 CPU processor chips, 5 volt and 3.43 volt power is provided directly to the module from the power supplies.  For systems with EV56 CPU processor chips, 5 volt, 3.3 volt, and 2.5 volt power is necessary.  The CPU modules with EV56 chips convert some of the 3.3 volt power into 2.5 volts needed for the internal circuitry of the CPU chip.


MC Bus Block Diagram and Slot Designation
System Bus Block Diagram


EV5 is 0.5 micron CMOS tecnology used to make the Alpha chip used in B3001, and B3002 modules.


EV56 is 0.35 micron CMOS technology used to make the Alpha chip used in the B3004 module.


The 54-23803-01 is the system bus motherboard for the AlphaServer 4100.


The 54-23803-02 is the system bus motherboard for early shipments of the AlphaServer 4000.


The 54-23805-01 is the system bus motherboard for AlphaServer systems with up to 16 PCI I/O slots.


MC Bus to PCI Bus Bridge
System Bus to PCI Bus Bridge (B3040-AA and B3040-AB)

The system bus to PCI bus bridge module (the horse module) converts system bus commands and data addressed to I/O space to PCI commands and data; and converts PCI bus commands and data addressed to system memory or CPUs to system bus commands and data. The AlphaServer 4000 can be configured with both bridges; the AlphaServer 4100 is configured with one, the B3040-AA.

The bridge has two major components:

Command/address processor (CAP) chip

Two data path chips (MDPA and MDPB)

There are two sets of these three chips, one set on each side of the module.  Each set bridges to one of the PCI buses on the PCI motherboard.

The interface on the system bus side of the bridge responds to system bus commands addressed to the upper 64 Gbytes of I/O space.

The interface on the PCI side of the bridge responds to commands addressed to CPUs and memory on the system bus.  On the PCI side, the bridge provides the interface to the PCIs.  Each PCI bus is addressed separately.  The bridge does not respond to devices communicating with each other on the same PCI bus.  However, should a device on one PCI address a device on another PCI bus, commands, addresses, and data run through the bridge out onto the system bus and back through the bridge to the other PCI bus.

In addition to its bridge function, the system bus to PCI bus bridge module monitors every transaction on the system bus for errors.  It monitors the data lines for ECC errors and the command/address lines for parity errors.

Note:  When errors are logged the B3040-AA is called the left hand horse and the B3040-AB is called the right hand horse.

LEDs

The bottom LED indicates that DC power and all fans are within tolerances.  This LED flashes when DC power is off and indicates the presence of Vaux.


System Bus to PCI Bus Bridge
System Bus to PCI Bus Bridge Block Diagram and Module


I/O space is addressed whenever bit <39> on the system bus address lines is set.  The space so defined is 512 Gbytes in size.  The first 448 Gbytes are reserved and the last 64 Gbytes, when bits <38:36> are set, are mapped to the two PCI I/O buses.


Vaux is a voltage supplied by the power supplies whenever AC power is applied to them.  Vaux powers the cabinet fans at the top of cabinet systems.


Power System Topics
Power System

Power Circuit and Cover Interlocks

Power Up/Down Sequencing

Power Control Module Features

Power Control Module LEDs

Power Supply Features

Cabinet Power Configuration

Pedestal Power Configuration (North America and Japan)

Pedestal Power Configuration (Europe and AP)

Power System FRU List


Power System FRU List and Block Diagram
Power System FRU List

Item	Part Number	Description
1	30-45353-01 30-45353-02	AC input box; only in cabinet systems.  The 01 variant is for North America and Japan and has a NEMA L6-30P power cord. The 02 variant is for Europe and AP and has an IEC 309 power cord. Used in H9A10-EB and -EC cabinets
2	12-23501-01 12-45334-02	AC power strip: The 12-23501 part is used on pedestals in North America and Japan and has six NEMA outlets and a 15 ft. cord to the wall outlet. The 12-45334 part is used on pedestals in Europe and AP and on H9A10-EB and -EC cabinet systems worldwide and has six IEC320 outlets.  In pedestal systems, country kit cords match country-specific wall outlets.
2a	17-04285-01	Power cord from AC input box to power strip.  A .5 meter, IEC320 to IEC320 connector used in H9A10-EB and -EC cabinet systems only.  In pedestal systems, country kit cords match country-specific wall outlets.
1, 2, &2a	H7600-AA H7600-DB	Power controllers used in H910-EL and -EM cabinets.  The H7600-AA is a 120 volt, 15 amp controller used in H9A10-EL cabinets found in North America and Japan.  It has 10 NEMA 5-15 outlets. The H7600-DB is a 240 volt, 16 amp controller used in H9A10-EM cabinets found in Europe and Asia Pacific.  It has 12 NEMA 5-IEC C13 outlets.
3	17-00606-02  17-04285-02	Power cord from power strip to power supply:  The 17-00606-02 is a 2 m NEMA to IEC320 AC jumper used with the 12-23501-01 power strip in North American and Japan pedestals. The 17-04285-02 is a 2 m IEC320 to IEC320 AC jumper used with the 12-45334-02 power strip used on pedestals in Europe and AP and on cabinet systems worldwide and has six IEC320 outlets  In pedestal systems, country kit cords match country-specific wall outlets.
4	30-44712-01	Power supply; 92 to 264 VAC input; one to three in a system drawer.
5	17-04199-01	Cable connecting power supplies
6	17-04217-01 17-04385-01	Power distribution harness (4100 and 4000 with 54-23803-02 motherb) Power distribution harness (4000 with 54-23805-01 motherboard)
7	17-04201-01	Cable from OCP to the PCI motherboard (cabinet system only)
8	70-32016-01 70-33002-01	Interlocks and cable to OCP (4100 and 4000 with 54-23803-02 motherb) Interlocks and cable to OCP (4000 with 54-23805-01 motherboard)
9	17-04351-01	Power from power harness between the harness and fan2 to the SCM (4100 and early 4000 only).
10	17-04293-01	Cable from power harness to interconnect cable and pedestal tray connector (pedestal system only)
11	17-04302-01	Cable from pedestal tray connector to the PCI motherboard (pedestal system only)
12	17-04201-01	Cable from pedestal tray connector to OCP (pedestal system only)
13	17-04305-01	Cable from pedestal tray connector to OCP and SCSI devices (pedestal system only)
14	17-04339-01	Power cord from the power strip to the cabinet fan tray (cabinet only)
AlphaServer 4100 Power System Block Diagram
AlphaServer 4000 Power System Block Diagram


Power System Block Diagram
Power System Block Diagram (4100 and early 4000)


Power System Block Diagram
Power System Block Diagram (4000)


The operator control panel (OCP) has a 16-character display panel and three button switches: the On/Off button, the Halt button, and the Reset button.  In the pedestal, the OCP is  above the system drawer.  In the cabinet, the OCP is below the system drawer.


Power Supply Features
Power Supply Features (30-44712-01)

The system drawer holds one to three power supplies, optionally providing redundant power.  The features are:

•	90-264 Vrms Input.

The power supply senses a wide range of input voltages and input cycles.

•	450 watts output.

•	Output voltages are as follows:

Output Voltage	Min Voltage	Max  Voltage	Max Current
+5.0	4.85	5.25	50
+3.43	3.400	3.465	75
+12	11.5	12.6	11
-12	-10.9	-13.2	0.2
-5.0	-4.6	-5.5	0.2
Vaux	8.5	9.5	0.05
•	Remote sense on +5.0V and +3.43V.

+5.0V is sensed on all CPUs, the system bus motherboard, and the PCI bus motherboard.

+3.43V is sensed on all CPUs and the system bus motherboard.

•	Current share on +5.0V, +3.43V, and +12V.

•	1% regulation on +3.43V.

•	Fault protection (latched)  If a fault is detected by the power supply, it will shut down.  The faults detected are:

•	Overvoltage

•	Overcurrent

•	Power overload

•	DC_ENABLE_L input signal starts the DC outputs.

•	POK_H output signal indicates that the power supply is operating properly.


Power Supply Outputs
Power Supply Outputs (back of supply)


Power Control Module Features
Power Control Module Features (54-24117-01)

The power control module is located behind the the system bus to PCI bus bridge module (B3040).  Its features are as follows:

1	Controls the power-up/down sequencing.
2	Monitors the combined output of power supplies VDD (3.43V) and VCC (5.0V) and asserts DCOK_SENSE if these voltages are within range and asserts POWER_FAULT_L causing an immediate power shutdown if either is not.
3	Monitors its own temperature sensor and asserts TEMP_FAIL, if temperature exceeds 55 degrees C.
4	Monitors CPU and system drawer fans and asserts CPUFAN_OK if all CPU fans are functioning properly, asserts SYSTEM_FAN_OK if the drawer cooling fans are functioning properly, otherwise it asserts FAN_FAULT_L.  Each fan is checked at 1 second intervals.
5	Powers down the system 30 seconds after detecting TEMP_FAIL, or the absence of CPUFAN_OK, or the absence of SYSTEM_FAN_OK by asserting POWER_FAULT_L.
6	Provides visual indication of faults through LEDs.
7	Has two registers, one that generates interrupts when bits change, and one that latches errors but does not generate interrupts.


Power Control Module


Power Up/Down Sequencing
Power-Up/Down Sequencing

The power On/Off button can be controlled manually or remotely.  The button is on the OCP.  Remote power control is provided though the server control module.

When AC is applied to the system, Vaux is asserted and is sensed by the PCM.  The PCM asserts DC_ENABLE_L starting the power supplies.  If there is a hard fault on power-up, the power supplies shut down immediately; otherwise, the power system powers up and remains up until the system is shut off or the PCM senses a fault.  If a power fault is sensed, the power system attempts to restore power and will do so if the fault is not sensed a second time.  If the fault is still present, the power system shuts down.

Since Vaux is independent of the power supply start, the AC plugs at the front of the supplies must be removed to reset Vaux allowing capacitors to drain voltage. All power failures require this procedure since the PCM must sense a change in Vaux to start the power supplies.


Power Up/Down Sequence Flow-chart
Power-Up/Down Sequence Flowchart


Power Control Module LEDs

The PCM has 11 LEDs visible through the back of the system card cage.  The LED display shows the relative placement of the LEDs and the following table gives the meaning of each LED state:

LED	Normal State and Description
DCOK_SENSE	On  Indicates both +5.0V and +3.43V are present and within limits
PS0_OK	On  Indicates power supply 0 is present and has asserted POK_H
PS1_0K	On  Indicates power supply 1 is present and has asserted POK_H Off  Indicates power supply 1 not present or is broken
PS2_OK	On  Indicates power supply 2 is present and has asserted POK_H Off  Indicates power supply 2 is not present or is broken
TEMP_OK	On  Indicates that the system temperature is below 55 C
CPUFAN_OK	On  Indicates that all CPU fans are OK. Off  Indicates that a CPU fan has failed.  The specific fan is identified by the CS_FANx or C_FAN3 LED that remains lit.
SYSFAN_OK	On  Indicates that all system fans are OK. Off  Indicates that a system fan has failed.  The specific fan is identified by the CS_FANx that remains lit.
CS_FAN0	On  Indicates that CPU fan 0 and system fan 0 are being sampled or one of them has failed as indicated by CPUFAN_OK and SYSFAN_OK. Off  Indicates that CPU fan 0 and system fan 0 are not being sampled and are functioning properly.
CS_FAN1	On  Indicates that CPU fan 1 and system fan 1 are being sampled or one of them has failed as indicated by CPUFAN_OK and SYSFAN_OK. Off  Indicates that CPU fan 1 and system fan 1 are not being sampled and are functioning properly.
CS_FAN2	On  Indicates that CPU fan 2 and system fan 2 are being sampled or one of them has failed as indicated by CPUFAN_OK and SYSFAN_OK. Off  Indicates that CPU fan 2 and system fan 2 are not being sampled and are functioning properly.
C_FAN3	On  Indicates that CPU fan 3 is being sampled or has failed as indicated by CPUFAN_OK. Off  Indicates that CPU fan 3 is not being sampled and is functioning properly.


Power Control Module LED Display


Power Circuit and Cover Interlocks

The power circuit diagram shows the distribution of power thoughout the system drawer.  Opens in the circuit or the PCM signal POWER_FAULT_L or the SCM signal RSM_DC_EN_L interrupt DC power applied to the system.  The opens can be caused by the On/Off button or the cover interlocks.  The POWER_FAULT_L signal is asserted by the PCM module if it detects a fault and the RSM_DC_EN_L is controlled remotely.

A failure anywhere in the circuit will result in the removal of DC power.  Note that if the relay used on the SCM modules to control the RSM_DC_EN_L signal fails, DC power is removed for the system.

To override the cover interlocks, find a suitable object to close the interlock circuit at the location(s) identified in the picture(s).  The switch assemblies contain single switches for all covers.

AlphaServer 4000 vs AlphaServer 4100

All system drawers have three cover interlocks:  one for the system bus card cage, one for the PCI card cage on the left, and one for the power and system fan area.  In AlphaServer 4000 systems with the second PCI card cage a fourth switch is used.

AlphaServer 4100 Power Circuit Diagram
AlphaServer 4000 Power Circuit Diagram


Interlock Block Diagram
Power Circuit Diagram for AlphaServer 4100


Power Circuit Diagram for AlphaServer 4000


Rackmount Power Configuration
Cabinet Power Configuration

The following apply to cabinet systems:

1	There is 4800 VA power available.

2	A single system drawer requires 1100 VA.

3	A StorageWorks shelf requires 150 VA.

4	A system fan tray requires 100 VA and is required in all cabinet systems.

5	There is a maximum of 18 IEC 320 outlets (3 power strips) in H9A10-EB and -EC cabinets.

6	There are 20 NEMA 5-15 outlets (2 H7600-AA controllers) in the H9A10-EL cabinet.

7	There are 24 IEC C13 outlets (2 H7600-DB controllers) in the H9A10-EM cabinet.

8	Site grounding is critical.  Leakage current will exceed 3.5 mArms in all but the simplest of configurations.

9	Only one system drawer may be connected to a single power strip.  In a four system drawer configuration, H9A10-EB and -EC only, the fourth drawer should have its three power cords distributed to each power strip.

10	H9A10-EL and -EM cabinets can have a maximum of three system drawers.

11	The H7600-AA power controller in the H9A10-EL cabinet and the H7600-DB power controller in the H9A10-EM cabinet are configured differently.  In the -DB variant, all 12 outlets are protected by a single 16 amp. circuit breaker.  In the -AA variant, 6 outlets are protected by a 15 amp. circuit breaker and the remarining 4 outlets are protected by a second 15 amp. circuit breaker.  The examples show the differences.

For example, redundant power configurations are shown: two, a simple configuration and a worst-case configuration, are for H9A10-EB and -EC cabinets; a third, with an H7600-AA controller and three system drawers for the H9A10-EL cabinet; and the fourth, with an H7600-DB controller with a single system drawer for the H9A10-EM cabinet.

See System Packaging for a table showing cabinet differences.


Worst Case Rackmount Power Distribution
Worst-Case Cabinet Power Distribution


 H9A10-EM Cabinet Single Drawer Configuration


H9A10-EL Cabinet Three Drawer Configuration


Simple Rackmount Power Distribution
Simple Cabinet Power Distribution


Pedestal Power Configuration (North America and Japan)

The following apply to pedestal systems in N.A. and Japan:

1	1800 VA per branch circuit and 1440 VA per line cord in North America assuming a 15 A branch.

2	1500 VA per branch circuit and 1200 VA per line cord in Japan assuming a 15A branch.

3	A system drawer requires 1100 VA.

4	A StorageWorks shelf requires 150 VA.

5	There is a maximum of 12 NEMA receptacles.

6	A single AC power strip can only support one system drawer and one StorageWorks shelf without exceeding the 15A restriction.

7	When two AC power strips are used, the combined AC input line current cannot exceed the site circuit breaker restriction assuming both strips are plugged into the same circuit.

The figure shows the application of these premises in a redundant power configuration.


Pedestal Power Distribution (North America and Japan)


Pedestal Power Configuration (Europe and GIA)
Pedestal Power Configuration (Europe and AP)

The following apply to pedestal systems in Europe and AP:

1	2200 VA is available per power strip.

2	A system drawer requires 1100 VA.

3	A StorageWorks shelf requires 150 VA.

4	There is a maximum of 10 IEC 320 receptacles.  One receptacle is blocked on each power strip to control leakage.

5	A single AC power strip can support one system drawer and three StorageWorks shelves.

The figure shows the application of these premises in a redundant power configuration.


Pedestal Power Distribution (Europe and GIA)
Pedestal Power Distribution (Europe and AP)


In 4100 systems, one or two CPUs require one power supply; redundant power is provided by two.  Systems with three on more CPUs require two power supplies; redundant power is provided by three.

In 4000 systems, one or two CPUs and a single PCI card cage require one power supply; redundant power is provided by two.  Systems with one or two CPUs and two PCI card cages require two power supplies; redundant power is provided by three.


PCI I/O Subsystem
PCI I/O Subsystem (B3050 and B3051)

The 4000 and 4100 systems use PCI I/O subsystems (the saddle module).  The 4100 uses two four-slot PCI buses on the B3050 module, one that has an EISA bridge and one that does not.  The 4000 has another two PCI buses available on the B3051 module.

System diagnostics are on the B3050 module.  Note the path from the CPU to the diagnostics and console code requires that most of the system hardware function.

PCI bus 0 is a 64 bit bus with a PCI to EISA bus bridge embedded on it.  There are four PCI slots on the PCI bus, and three EISA slots on the EISA bus.  However, physical space limits the number of PCI and EISA options to four. (If all PCI slots are filled on the bus, the SRM console command show config shows five devices on the bus - four in slots and the embedded PCI to EISA bus bridge.)

An 8-bit XBUS is connected to the EISA bus.  On this bus there is an interface to the system I2  C bus; mouse and keyboard support;  an I/O combo controller supporting two serial ports, the floppy controller, and a parallel port; a real-time clock; two 1 MB flash ROMs containing system tests and console code, and an 8 KB NVRAM.

PCI bus 1 is a 64 bit bus that has four option slots.  Embedded on this bus is a SCSI controller that controls the CD-ROM.  (If all slots are filled on the bus, the SRM console command show config will show five devices on the bus - four in slots and the embedded SCSI controller.)

PCI bus 2 and 3 are two more 64 bit PCI buses used in the AlphaServer 4000.  No devices are embedded on either of these two buses.  Both buses accept devices powered by either 3 or 5 volts.

Note:  In error logs when the Saddle type is left, the B3050 module is referenced; when the Saddle type is right, the B3051 is referenced.

PCI Bus Numbering Scheme

Slot	PCI 0	PCI 1	PCI 2 (4000 only)	PCI 1 (4000 only)
0	Reserved	Reserved	Reserved	Reserved
1	PCI to EISA bridge	Internal CD-ROM controller	Reserved	Reserved
2	PCI or EISA slot	PCI slot	PCI slot	PCI slot
3	PCI or EISA slot	PCI slot	PCI slot	PCI slot
4	PCI or EISA slot	PCI slot	PCI slot	PCI slot
5	PCI slot	PCI slot	PCI slot	PCI slot


I/O Subsystem Module and Block Diagram


Copyright

Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.

The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation.

Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies.

Copyright  1997 by Digital Equipment Corporation. All rights reserved.

The following are trademarks of Digital Equipment Corporation: AlphaServer, OpenVMS, StorageWorks, VAX, and the DIGITAL logo.

The following are third-party trademarks:  Lifestyle 28.8 DATA/FAX Modem is a trademark of Motorola, Inc. UNIX is a registered trademark in the U.S. and other countries, licensed exclusively through X/Open Company Ltd.  U.S. Robotics and Sportster are registered trademarks of U.S. Robotics.  Windows NT is a trademark of Microsoft, Inc.  All other trademarks and registered trademarks are the property of their respective holders.

FCC Notice: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense will be required to take whatever measures are required to correct the interference.

Shielded Cables: If shielded cables have been supplied or specified, they must be used on the system in order to maintain international regulatory compliance.

Warning! This is a Class A product. In a domestic environment this product may cause radio interference, in which case the user may be required to take adequate measures.

Achtung! Dieses ist ein Gerät der Funkstörgrenzwertklasse A. In Wohnbereichen können bei Betrieb dieses Gerätes Rundfunkstörungen auftreten, in welchen Fällen der Benutzer für entsprechende Gegenmaßnahmen verantwortlich ist.

Avertissement! Cet appareil est un appareil de Classe A. Dans un environnement résidentiel, cet appareil peut provoquer des brouillages radioélectriques. Dans ce cas, il peut être demandé à l'utilisateur de prendre les mesures appropriées.


Cabinet System Fan Tray

A fan tray, at the top of the cabinet, contains three exhaust fans, a small 12 volt power supply, a power distribution panel, and a fan failure detect module.

Two LEDs, located on the front panel, are used to indicate the state of the tray.  One LED, a power LED (green), indicates the presence or absence of power; the other (amber), normally off, indicates, when it is flashing, that one or more of the fans is not functioning properly.  There are no system indications of malfunction.

The 12 volt distribution panel is used to deliver 12 volts to each SCM.

Part numbers:

Part Number	Name
54-24691-01	Fan fail detect module
30-46788-01	Power supply
12-23609-21	Fan
17-04324-01	Fan tray power harness


Cabinet System Fan Tray


Maintenance Bus (I2 C Bus)

The I2 C bus (spoken I squared C bus) is a small internal maintenance bus used to monitor system conditions, display faults, store error state, and track configuration information in the system.  Though all system modules (not I/O modules) sit on this bus, only the I2 C controller accesses it.  Everything written or read on the I2 C bus is done by the controller.

Monitor

The state of system conditions scanned by the PCM occurs on the I2 C bus.  There are two registers on the PCM: one records the state of the fans and power supplies and is latched when there is a fault, the other causes an interrupt on the I2 C bus when a CPU or system fan fails, an overtemperature condition exists, or power supplied to the system is out of tolerance.  It is this interrupt received by the I2 C bus controller on PCI0 that alerts the system of imminent power shutdown.  Thirty (30) seconds is provided for the controller to read the two registers and store the information in the EEPROM on the PCM and for the system to gracefully come down.  The SRM console command show power reads these registers.  See Power Control Module.

Fault Display

The OCP display is written through the I2 C bus.

Halt Button

The I2 C bus detects the state of the Halt button (in/out).

Store Error State

Error state is written and read for power conditions.

Configuration Tracking

Each module in the system has an EEPROM that contains information about the module that can be written and read over the I2 C bus.  All modules contain the following information:

Module type

Module serial number

Hardware revision

Firmware revision

Memory size (only required for memory modules)

AlphaServer 4100 and 4000 Differences

On the I2 C bus AlphaServer 4100 CPUs 2 and 3 are replaced by AlphaServer 4000 IOD2 and 3.

I2 C Bus Block Diagram (4100)
I2 C Bus Block Diagram (4000)


I2 C Bus Block Diagram
I2 C Bus Block Diagram (4100)


I2 C Bus Block Diagram
I2 C Bus Block Diagram (4000)


Troubleshooting

Troubleshooting is an art.  The flowchart is a place to start; it directs you to different troubleshooting methods in an attempt to get the machine to tell you what is broken.  It is very important to check power system LEDs.  Information in these LEDs gets lost when the AC is removed from the machine to recycle the PCM module.  See the power-up/down sequence flowchart.

Systems running Open VMS and Digital UNIX most likely have a serial terminal connected to COM1 on the server control module bulkhead.  Systems running NT may or may not have a serial terminal connected to COM1.  Windows NT systems require a graphics monitor as the console. If COM1 is not used, you are likely to miss power-up messages that can help you diagnose the system (you can see the messages flash by on the OCP display but you may wish to connect a serial terminal). See console device determination.

Methods to troubleshoot described here are:

Troubleshooting Power

Troubleshooting with LEDs

Troubleshooting with Diagnostics

Troubleshooting Using the Error Log

Troubleshooting IOD-Detected Errors

Double Error Halts and Machine Checks while in PAL

Error Registers


Troubleshooting Flowchart


The server control module is at the bottom of the PCI card cage.  Its bulkhead has connectors for a mouse, keyboard, a parallell port, and COM ports 1 and 2.  Remote control of the system though is the primary function of the server control module.


Troubleshooting Power

Power problems can occur before the system is up or while the system is running.

If a system stops running, always check the PCM module LEDs.  Troubleshooting a power problem from a cold start is vastly more difficult and time consuming than troubleshooting a system that halted because of a power problem while running.  The  PCM LEDs capture data indicating what in the power circuit shuts down power.  Perform whatever service is indicated by the LEDs.

On a cold start, the PCM LEDs are not valid until after DCOK_SENSE has been asserted.  Notice in the power-up/down sequence flowchart that DCOK_senSE, the signal necessary to apply DC power to the system, is asserted after power, fans, and temperature are tested for the first time.  The power problem could be caused by anything that prevents DCOK_SENSE from being asserted and in this situation the LEDs give no indication of what that failure might be.

Those failures are:

•	A system fan failure

•	A CPU fan failure

•	Power supplied to the system is out of tolerance (in redundant power systems a power supply could be broken and the system could still power up)

•	A PCM failure

•	An interlock failure

•	Wire problems

A temperature problem is unlikely but possible on a cold start.

The recommended order to try to fix this type of failure is:

1	Look to see if any CPU fan or system fan is not spinning (fans can fail by not spinning and/or failing to put out the tachometer output necessary as input to the PCM comparator that checks the fans; see step 4 and 5).

2	Change the PCM module.

3	Reduce the number of CPUs.  You can check the output of each CPU fan with a voltmeter.  Probe the middle of the three outputs of a fan with the positive lead of the meter and ground the other probe.  The meter should read 4.5 to 5.5 volts.  If the output of the fan is out of this range, replace the fan.

4	Check the output of the power supplies.  See power supply features for locations of +5 and +3.3 volt output pins.

5	Check the output of each system fan with a voltmeter.  Probe the middle of three outputs of the fans with the positive lead of the meter and ground the other probe.  The meter should read 2.5 to 3 volts.  If the output of the fan is out of this range, replace the fan.

Disable the interlocks to check the voltages mentioned in steps 3 and 5.  You will have only 10 seconds before the PCM module shuts down the DC power as shown in the power up/down sequence flowchart to measure these voltages.  Also note: the PCM module must sense a change in Vaux to start the power supplies.  Pressing the On button has no effect if the machine halted because of some failure in the power system.  The power supplies must be unplugged and plugged back in for the On button to work.


Power Problem List


Troubleshooting with LEDs

LEDs can be seen on the OCP, on each CPU, on the system bus to PCI bus bridge module, and on the PCM.  Also, the cabinet has two LEDs on its top panel.  The LEDs on the modules are visible from the back of the system drawer.  LEDs on the OCP and on the cabinet top panel are visible when the front door is open.

For descriptive information on LEDs see the following topics:

LEDs and Power-Up

Power Control Module LEDs

Control Panel Assembly

Cabinet System Fan Tray

During power-up/reset/initialize/test, diagnostics are run on CPUs, memories, IODs, PCIs, and sometimes options.  Refer to the power-up test strategy section for a description of power-up tests.  The following is likely the case when any of these events happen:

1. 	If the CPU STP LED on any CPU module is lit, that CPU is functioning properly.  Cases where this is not true are likely to be for reasons other than those tested by the SROM and XSROM.  See SROM power-up test flow  and XSROM power-up test flow.  If the LED is out and Windows NT is not the operating system, replace the CPU.

NOTE: When OpenVMS and Digital UNIX are the operating systems, CPU STP LEDs remain lit.  When Windows NT is the operating system, the CPU STP LED is turned off by the AlphaBIOS console.

You can use the Halt button on the OCP to prevent the AlphaBIOS console from booting, thus assuring the validity of the CPU STP  LED.  If the LED is still off, replace the CPU.  If the LED is lit, you can use the SRM console command alphabios to load and run the AlphaBIOS console.

The DC_OK LED on a CPU module is driven by the PCM module.  If it is not lit, power problems are likely.

The third and middle LED on a CPU lights only when the SROM on each CPU is functioning.

2.	The system bus to PCI/EISA bus bridge module has four LEDs:

The top two indicate the condition of the bridge.  If either is off, replace the bridge.

The bottom two are passed from the PCM module.  Both should be on during normal operation.  If either is off while the system is on, the LEDs on the PCM module should indicate what failed.  If they do not, the PCM could be broken or the bridge module is not passing the signals to the LEDs.  Note that if AC power is applied and the system is off and a power supply is in operation, the power LED flashes indicating the presence of Vaux.  See power control module LEDs and troubleshooting power.

3.	The system bus to PCI bus bridge for IODs 2 and 3 in the AlphaServer 4000 has two LEDs.  If either LED is off, replace the bridge.

4.	The two LEDs on the OCP are contained in the On button and the Halt button.

When the ON button LED is on, DC power is applied and the system is running.  When the LED is off, the system is not running; however, AC power may be present. If AC power is present, the PCM LEDs are in a steady state and the power LED on the system bus to PCI bus bridge module should be flashing.  If these conditions are not met, something is wrong with power.  See troubleshooting power.

When the Halt button LED is lit and the On button is on, the system is running either the SRM console or any of the three operating systems.  See control panel assembly for a description of the function of the Halt button.  If the button is in, but the LED is off, the OCP, its cables, or PCM is likely to be broken.

4.	A cabinet system has three exhaust fans at the top of the cabinet.  They are powered by a small power supply in the fan tray and are independent of the system.  If they fail, there is no system, console, or error log message.  There are two LEDs on the top panel: a fan LED and a power LED.

When the fan LED (amber) is flashing, a cabinet fan needs replacing. Look to see which fan appears broken (either not functioning at all; or appears to be moving slower than the others).

When the power LED (green) is off, either the power supply in the fan tray is broken or there is a power problem.  Note that this power source is independent of the system as are these fans; no system message is produced if it fails.  Also note that this supply may power the server control module.


The self-test pass LED is the top LED on CPU modules.  When it is lit, the CPU passed self-test.  When it is not lit and the SRM console was not replaced by AlphaBIOS, the CPU did not pass self-test.


The power control module or PCM controls the power-up/down sequencing.  The PCM monitors the power and system drawer environment.


LEDs Placement
LED Placement


Troubleshooting with Diagnostics

Diagnostic console commands allow a user to monitor and control the running of diagnostics, configure the system, and run exercisers on specific devices.

The test command runs firmware diagnostics for components of the system drawer and runs only under the SRM console.

Testing can be aborted by Ctrl/C.

NOTE: If you are running the Microsoft Windows NT operating system, switch from AlphaBIOS to the SRM console in order to enter the test command. From the AlphaBIOS console, press in the Halt button (the LED will light) and reset the system, or select DIGITAL UNIX (SRM) or OpenVMS (SRM) from the Advanced CMOS Setup screen and reset the system.

The tests run sequentially.  The status of each test is displayed on the console terminal as the tests progress.  If a particular device is not present, a message is displayed indicating that the device is not available for testing.

The test command with no qualifiers runs all exercisers for subsystems and devices supported as boot devices.  The test runs for 10 minutes.

The command syntax is:

test [-t time] [-q] [option]

-t time	Specifies the run time in seconds. The default for system test is 600 seconds (10 minutes).
-q	Disables the display of status messages as exerciser processes are started and stopped during testing. Sets the environment variable d_verbose to zero.
option	Either cpun, memn, or pcin, where n is 0, 1, 2, 3, or *. If nothing is specified, the entire system is tested.  For testing specific options on the PCI, see Console Power-Up Test Flow.
Examples:

P00>>> test cpu0	# tests only CPU0

P00>>> test mem2 -t 60	# tests only MEM pair 2 for 60 seconds

P00>>> test esc_diag 	# tests the EISA controller on PCI0


Test Command Example

P00>>> test

Console is in diagnostic mode

System test, runtime 600 seconds

Type ^C to stop testing

Configuring system..

polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1   SCSI Bus ID 7

dka500.5.0.1.1     DKa500                   RRD45  1645

polling ncr1 (NCR 53C810) slot 3, bus 0 PCI, hose 1   SCSI Bus ID 7

dkb200.2.0.3.1     DKb200                   RZ29B  0007

dkb400.4.0.3.1     DKb400                   RZ29B  0007

polling floppy0 (FLOPPY) PCEB - XBUS hose 0

dva0.0.0.1000.0    DVA0                      RX23

polling tulip0 (DECchip 21040-AA) slot 2, bus 0 PCI, hose 1

ewa0.0.0.2.1: 08-00-2B-E5-B4-1A

Testing EWA0 network device

Testing VGA (alphanumeric mode only)

Starting background memory test, affinity to all CPUs..

Starting processor/cache thrasher on each CPU..

Starting processor/cache thrasher on each CPU..

Starting processor/cache thrasher on each CPU..

Starting processor/cache thrasher on each CPU..

Testing SCSI disks (read-only)

No CD/ROM present, skipping embedded SCSI test

Testing other SCSI devices (read-only)..

Testing floppy drive (dva0, read-only)

 ID      Program   Device       Pass Hard/Soft Bytes Written  Bytes Read

------- --------- ------------- ---- --------- -------------- ----------

00003047 memtest   memory          1  0    0     134217728     134217728

00003050 memtest   memory        205  0    0     213883392     213883392

00003059 memtest   memory        192  0    0     200253568     200253568

00003062 memtest   memory        192  0    0     200253568     200253568

00003084 memtest   memory         80  0    0      82827392      82827392

000030d8 exer_kid  dkb200.2.0.3   26  0    0             0      13690880

000030d9 exer_kid  dkb400.4.0.3   26  0    0             0      13674496

0000310d exer_kid  dva0.0.0.100    0  0    0             0             0

 ID      Program   Device       Pass Hard/Soft Bytes Written  Bytes Read

------- --------- ------------- ---- --------- -------------- ----------

00003047 memtest   memory          1  0    0     432013312     432013312

00003050 memtest   memory        635  0    0     664716032     664716032

00003059 memtest   memory        619  0    0     647940864     647940864

00003062 memtest   memory        620  0    0     648989312     648989312

00003084 memtest   memory        263  0    0     274693376     274693376

000030d8 exer_kid  dkb200.2.0.3   90  0    0             0      47572992

000030d9 exer_kid  dkb400.4.0.3   90  0    0             0      47523840

0000310d exer_kid  dva0.0.0.100    0  0    0             0        327680

 ID      Program   Device       Pass Hard/Soft Bytes Written  Bytes Read

------- --------- ------------- ---- --------- -------------- ----------

00003047 memtest   memory          1  0    0     727711744     727711744

00003050 memtest   memory       1054  0    0    1104015744    1104015744

00003059 memtest   memory       1039  0    0    1088289024    1088289024

00003062 memtest   memory       1041  0    0    1090385920    1090385920

00003084 memtest   memory        447  0    0     467607808     467607808

000030d8 exer_kid  dkb200.2.0.3  155  0    0             0      81488896

000030d9 exer_kid  dkb400.4.0.3  155  0    0             0      81472512

0000310d exer_kid  dva0.0.0.100    1  0    0             0        607232

^C

Testing aborted. Shutting down tests.

Please wait..

System test complete

P00>>>


The horse module is the engineering code name for the system bus to PCI bus bridge module.


Troubleshooting using the Error Log
Troubleshooting with Error Logs

Error detection is performed by CPUs, the IOD, and the EISA to PCI bus bridge.

In the CPU module, the system bus is isolated by transceivers (XVER) from the data and command/address lines on the module.  This allows the CPU chip access to the duplicate tag store and B-cache while the system bus is in use.  The CPU detects errors only when it is the consumer of the data.  The IOD detects errors on each system bus cycle regardless of whether it is involved in the transaction or not.

Note that the primary, in multiprocessing AlphaServers 4100 systems, is always CPU0.  It handles all system interrupts.

Lines Protected	Device
ECC Protected

System bus data lines	IOD on every transaction, CPU when taking data from the system bus
B-cache data	IOD on transactions to/from the B-cache, CPU when taking data from its internal bus

Parity Protected

System bus command/address lines	IOD on every transaction, CPU when taking data from the system bus
Duplicate tag store	IOD on transactions to/from the duplicate tag store, CPU when taking data from its internal bus
B-cache index and status lines	CPU
PCI bus	IOD
EISA bus	EISA bridge
System bus errors detected by a CPU are also detected by the IOD.  Therefore, it is necessary to check the IOD for errors any time there is a CPU machine check.

•	If the CPU sees bad data and the IOD does not, the CPU is at fault.

•	If both the CPU and the IOD see bad data on the system bus, either memory or a secondary CPU put it there.  In such a case, the DIRTY bit, bit<20>, in the IOD MC_ERR1 register should be set or clear. If the DIRTY bit is clear, memory put the bad data on the bus.  If this bit is set, the source of the data is some CPUs cache destined for a different CPU.  Unless the system is a dual-processor system, there is no way of determining which of the other processors put the data on the bus.

Hard Errors

System-independent errors detected by the CPU.  These errors are processor machine checks handled as MCHK 670 interrupts and are:

Internal processor chip cache errors
CPU B-cache module errors

System-dependent errors detected by both the CPU and IOD.  These errors are system machine checks handled as MCHK 660 interrupts and are:

CPU-detected external reference errors
IOD hard error interrupts

The IOD can detect hard errors on either side of the bridge.

Soft Errors

System-independent errors detected and corrected by the CPU.  These errors are CPU module correctable errors handled as MCHK 630 interrupts.

System-dependent errors that are correctable single-bit errors on the system bus and are handled as MCHK 620 interrupts.

Error Log Events

Several different events get logged by OpenVMS and Digital UNIX.  Windows NT does not log errors in this fashion.

Error Log Event	Description
MCHK 670	Processor machine checks.  These are synchronous errors that inform precisely what happened at the time the error occurred.  They are detected inside the CPU chip and are fatal.
MCHK 660	System machine checks.  These are asynchronous errors that are recorded after the error has occurred.  Data on exactly what was going on in the machine at the time of the error may not be known.  They are fatal errors.
MCHK 630	Processor-correctable errors
MCHK 620	System-correctable errors
Last Fail	Used to collect system bus registers prior to crashing
I/O error interrupt	IOD error interrupts
System  environment	Used to provide status on power, fans, and temperature
Configuration	Used to provide system configuration information

For information on retrieving error logs, see DECevent and Error Log Retrieval.

For error log examples and analysis, see:

MCHK 670 CPU-Detected Failure

MCHK 670 CPU and IOD-Detected Failure

MCHK 670 a Read Dirty CPU Detected Error

MCHK 660 IOD-Detected Failure

MCHK 630 CPU-Correctable Error

MCHK 620 Correctable Error

Configuration Entry

For more help in isolating IOD errors, see Troubleshooting IOD-Detected Errors.

For definitions of error register bits, see error registers.

To decode commands, see command codes.

To decode system bus node ID, see node IDs.


Error Detector Placement


MCHK 670 CPU Detected Failure
MCHK 670 CPU-Detected Failure

To determine what failed, you need to identify the error.

Since this is a MCHK 670, the CPU that detected the error reports the error and its registers are valid to the error.

1.	CPU 1 logged the error in a system with two CPUs.

2.	During a D-ref fill, the External Interface Status register logged an uncorrectable ECC error.  Decoding the register, you will see that bit<30> is clear, indicating that the source of the error is the B-cache.

3.	Neither IOD CAP Error register saw an error.

The error was detected by a CPU and the data was not on the system bus.  Otherwise, the IODs would have seen the error.  Therefore, CPU 1 is broken.

This error log entry has been edited to decrease its size and registers of interest are in bold type.


MCHK 670 Error Log

Logging OS                         2. Digital UNIX

System Architecture               2. Alpha

Event sequence number             4.

Timestamp of occurrence              04-APR-1996 17:20:04

Host name                            whip16

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000002

CPU logging event (mperr) x00000001

Event validity                    1. O/S claims event is valid

Event severity                    1. Severe Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   1. Machine check (670 entry)

Software Flags            x0000000300000000

                                     IOD 1 Register Subpkt Pres

                                     IOD 2 Register Subpkt Pres

Active CPUs               x00000003

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

* MCHK 670 Regs *

Flags:                    x00000000

PCI Mask                      x0000

Machine Check Reason          x0098

PAL SHADOW REG 0          x00000000

PAL SHADOW REG 1          x00000000

.

.

.

PAL SHADOW REG 6          x00000000

PAL SHADOW REG 7          x00000000

PALTEMP0                  x00000000E87C7A58

PALTEMP1                  xFFFFFFFE8F658000

PALTEMP2                  xFFFFFC00003C9F40

.

.

.

PALTEMP22                 xFFFFFC00004F9D60

PALTEMP23                 x00000000E8709A58

Exception Address Reg     xFFFFFC00003BFB88

                                     Native-mode instruction

                                     Exception PC  x3FFFFF00000EFEE2

Exception Summary Reg     x00000000

Exception Mask Reg        x00000000

PAL BASE                  x00000000020000

                                     Base addr for palcode =  x0000000008

Interrupt Summary Reg     x00000000

                                     AST requests 3 - 0  x00000000

IBOX Ctrl and Status Reg  x000000C160000000

                                     Timeout Bit Not Set

                                     PAL Shadow Registers Enabled

                                     Correctable Err Intrpts Enabled

                                     ICACHE BIST Successful

                                     TEST_STATUS_H Pin Asserted

Icache Par Err Stat Reg   x00000000

Dcache Par Err Stat Reg   x00000000

Virtual Address Reg       xFFFFFFFE8F63BD38

Memory Mgmt Flt Sts Reg   x000000000166D1

                                     Ref which caused err was a write

                                     Ref resulted in DTB miss

                                     RA Field  x0000000000001B

                                     Opcode Field   x0000000000002C

Scache Address Reg        xFFFFFF00000254BF

Scache Status Reg         x00000000

Bcache Tag Address Reg    xFFFFFF80E98F7FFF

                                  External cache hit

                                  Parity for ds and v bits

                                  Cache block dirty

                                  Cache block valid

                                  Ext cache tag addr parity bit

                                  Tag address<38:20> is x00000000000E98

Ext Interface Address Reg xFFFFFF00E984DBCF

Fill Syndrome Reg         x0000000000002B

Ext Interface Status Reg  xFFFFFFF104FFFFFF

                                     Uncorrectable ECC error

                                     Error occurred during D-ref fill

LD LOCK                   xFFFFFF003797340F

** IOD SUBPACKET -> **               IOD 0 Register Subpacket

WHOAMI                    x000000BB  Device ID  x0000003B

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000F9E0000000

PCI Revision              x06008021  CAP Chip Revision  x00000001

                                     Horse Module Revision  x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     EISA Present

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06480FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enbld

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enbld

                                     Write Pend Number Thresh x00000008

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE  MC-PCI Bridge Priority Mode

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Dvice intr info en if en_int = 1

Interrupt Request         x00000000  Interrupts asserted  x00000000

Interrupt Mask Register 0 x00C50010

Interrupt Mask Register 1 x00000000

MC Error Info Register 0  xE0000000  MC bus trans addr <31:4>  x0E000000

MC Error Info Register 1  x000E88FD  MC bus trans addr <39:32>x000000FD

                                     MC_Command x00000008

                                     Device Id x0000003A

CAP Error Register        x00000000     (no error seen)

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      x00000000  MDPA Chip Revision  x00000000

MDPA Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

MDPB Status Register      x00000000  MDPB Chip Revision  x00000000

MDPB Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

** IOD SUBPACKET -> **               IOD 1 Register Subpacket

WHOAMI                    x000000BB  Device ID  x0000003B

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000FBE0000000

PCI Revision              x06000021  CAP Chip Revision  x00000001

                                     Horse Module Revision x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06480FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enbld

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enbld

                                     Write Pend Number Thresh x00000008

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE  MC-PCI Bridge Priority Mode

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Device intr info en if en_int = 1

Interrupt Request         x00000000  Interrupts asserted  x00000000

Interrupt Mask Register 0 x00C50001

Interrupt Mask Register 1 x00000000

MC Error Info Reg 0  xE0000000      MC bus trans addr <31:4>  x0E000000

MC Error Info Reg 1  x000E88FD      MC bus trans addr <39:32> x000000FD

                                     MC_Command x00000008

                                     Device Id x0000003A

CAP Error Register        x00000000     (no error seen)

PCI Bus Trans Error Adr   xC0018B48

MDPA Status Register      x00000000  MDPA Chip Revision  x00000000

MDPA Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

MDPB Status Register      x00000000  MDPB Chip Revision  x00000000

MDPB Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

PALcode Revision                     Palcode Rev: 1.21-3


When a CPU chip does not find data it needs to perform some task in its D-cache, it performs a D-ref fill to acquire data from off chip.


The engineering code name for the system bus to PCI bus bridge module is the horse module.


The engineering code name for the PCI motherboard is the saddle module.


MCHK 670 CPU and IOD Detected Failure
MCHK 670 CPU- and IOD-Detected Failure

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU 3 logged the error in a system with four CPUs.

2.	During a D-ref fill the External Interface Status  register logged an uncorrectable ECC error.  Decoding the register, you can see that bit<30> is set indicating that the source of the error is memory or the system.  Bits <32> and <35> are set indicating an uncorrectable ECC error and a second external interface hard error.

3.	Both IOD CAP Error registers logged an error.

4.	The command at the time of the error was a read.

5.	The bus master at the time of the error was CPU 3.

6.	The Dirty bit, bit <20> in the MC_ERR1 register is clear indicating the data is clean and comes from memory.

The error was detected by CPU 3, and the data was on the system bus and is clean.  Therefore, some memory module provided the wrong data.  (If the Dirty bit had been set, the data would have come from the cache of another CPU.)  To determine which memory, go to toubleshooting IOD-detected errors.

This error log entry has been edited to decrease its size and registers of interest are in bold type.


MCHK 670 CPU and IOD Detected Error Log
MCHK 670 CPU- and IOD-Detected Error Log

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number             6.

Timestamp of occurrence              08-APR-1996 11:27:55

Host name                            whip16

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000004

CPU logging event (mperr) x00000003

Event validity                    1. O/S claims event is valid

Event severity                    1. Severe Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   1. Machine check (670 entry)

Software Flags            x0000000300000000

                                     IOD 1 Register Subpkt Pres

                                     IOD 2 Register Subpkt Pres

Active CPUs               x0000000F

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

* MCHK 670 Regs *

Flags:                    x00000000

PCI Mask                      x0000

Machine Check Reason          x0098

PAL SHADOW REG 0          x00000000

PAL SHADOW REG 1          x00000000

.

.

.

PAL SHADOW REG 6          x00000000

PAL SHADOW REG 7          x00000000

PALTEMP0                  x00000001401A7A90

PALTEMP1                  x00000000000021

.

.

.

PALTEMP23                 x00000000ECE77A58

Exception Address Reg     x000000012005A8B4

                                     Native-mode instruction

                                     Exception PC  x0000000048016A2D

Exception Summary Reg     x00000000

Exception Mask Reg        x00000000

PAL BASE                  x00000000020000

                                   Base addr for palcode =  x0000000008

Interrupt Summary Reg     x00000000

                                     AST requests 3 - 0  x00000000

IBOX Ctrl and Status Reg  x000000C164000000

                                     Timeout Bit Not Set

                                     Floating Point Instr. may be issued

                                     PAL Shadow Registers Enabled

                                     Correctable Err Intrpts Enabled

                                     ICACHE BIST Successful

                                     TEST_STATUS_H Pin Asserted

Icache Par Err Stat Reg   x00000000

Dcache Par Err Stat Reg   x00000000

Virtual Address Reg       x00000001407D6000

Memory Mgmt Flt Sts Reg   x00000000011A10

                                     Ref resulted in DTB miss

                                     RA Field  x0000000008

                                     Opcode Field   x00000000000023

Scache Address Reg        xFFFFFF00000254BF

Scache Status Reg         x00000000

Bcache Tag Address Reg    xFFFFFF80286F7FFF

                                     External cache hit

                                     Parity for ds and v bits

                                     Cache block dirty

                                     Cache block valid

                                     Ext cache tag addr parity bit

                                  Tag address<38:20> is x00000000000286

Ext Interface Address Reg xFFFFFF0028681A8F

Fill Syndrome Reg         x00000000004B00

Ext Interface Status Reg  xFFFFFFF984FFFFFF

                                     Uncorrectable ECC error

                                     Error occurred during D-ref fill

                                     Scnd External Interface hard error

LD LOCK                   xFFFFFF000020040F

** IOD SUBPACKET -> **               IOD 0 Register Subpacket

WHOAMI                    x000000BF  Device ID  x0000003F

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000F9E0000000

PCI Revision              x06008021  CAP Chip Revision  x00000001

                                     Horse Module Revision  x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     EISA Present

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06460FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enabled

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enabled

                                     Write Pend Number Thresho x00000006

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE  MC-PCI Bridge Priority Mode

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Device intr info enabled if en_int = 1

Interrupt Request         x00810000  Interrupts asserted  x00010000

                                     Hard Error

Interrupt Mask Register 0 x00C50010

Interrupt Mask Register 1 x00000000

MC Error Info Register 0  x28681A80  MC bus trans addr <31:4>  x028681A8

MC Error Info Register 1  x800FD800  MC bus trans addr <39:32> x00000000

                                     MC_Command x00000018

                                     Device Id x0000003F

                                     MC error info valid

CAP Error Register        xC0000000  Uncorrectable ECC err det by MDPB

                                     MC error info latched

PCI Bus Trans Error Adr   x000003FD

MDPA Status Register      x00000000  MDPA Chip Revision  x00000000

MDPA Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

MDPB Status Register      x80000000  MDPB Chip Revision  x00000000

                                     MPDB Error Syndrome of  uncorrectable read

                                                             error

MDPB Error Syndrome Reg   x0000004B  Cycle 0 ECC Syndrome x0000000000004B

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

** IOD SUBPACKET -> **               IOD 1 Register Subpacket

WHOAMI                    x000000BF  Device ID  x0000003F

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000FBE0000000

PCI Revision              x06000021  CAP Chip Revision  x00000001

                                     Horse Module Revision  x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06460FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enbld

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enbld

                                     Write Pend Number Thresh x00000006

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE MC-PCI Bridge Priority

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Devce intr info en if en_int = 1

Interrupt Request         x00800000  Interrupts asserted  x00000000

                                     Hard Error

Interrupt Mask Register 0 x00C50001

Interrupt Mask Register 1 x00000000

MC Error Info Reg 0  x28681A80  MC bus trans addr <31:4>  x028681A8

MC Error Info Reg 1  x800FD800  MC bus trans addr <39:32> x00000000

                                     MC_Command x00000018

                                     Device Id x0000003F

                                     MC error info valid

CAP Error Register        xC0000000  Uncorrectable ECC err det by MDPB

                                     MC error info latched

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      x00000000  MDPA Chip Revision  x00000000

MDPA Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

MDPB Status Register      x80000000  MDPB Chip Revision  x00000000

                                     MPDB Error Syndr uncorrectbl read

MDPB Error Syndrome Reg   x0000004B  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

PALcode Revision                     Palcode Rev: 1.21-3


MCHK 670, a Read Dirty CPU Detected Failure
MCHK 670, a Read Dirty CPU-Detected Failure

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU 0 logged the error in a system with two CPUs.

2.	The External Interface Status register records an uncorrectable ECC error from the system (bit <30> set).

3.	Both IOD CAP Error registers logged an error.

4.	The MC Error Info registers 0 and 1 captured the error information.

5.	The commander at the time of the error was CPU0 (known from MC_ERR1).

6.	The command on the bus was a read memory command.

7.	The address read was a memory address not an I/O address.

8.	The data associated with the read was dirty.

From this information you know CPU0 requested data that was dirty, therefore, memory did not provide it nor did an I/O device.  Only another CPU could have provided the data from its cache.  Since there is only one other CPU in this system, other than CPU0, it is faulty.  Had there been more than two CPUs in the system, you could not have identified the error to a particular CPU.  You may wish to go to troubleshooting IOD-detected errors to familiarize yourself with a procedure designed to help with IOD-detected errors.

This error log entry has been edited to decrease its size and registers of interest are in bold type.


MCHK 670 - Read Dirty Failure

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number             4.

Timestamp of occurrence              08-APR-1996 10:20:37

Host name                            sect06

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000002

CPU logging event (mperr) x00000000

Event validity                    1. O/S claims event is valid

Event severity                    1. Severe Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   1. Machine check (670 entry)

Software Flags            x0000000300000000

                                     IOD 0 Register Subpkt Pres

                                     IOD 1 Register Subpkt Pres

Active CPUs               x00000003

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

* MCHK 670 Regs *

Flags:                    x00000000

PCI Mask                      x0000

Machine Check Reason          x0098  Fatal AlphaChip Detectd Hard Error

PAL SHADOW REG 0          x0000000000000000

PAL SHADOW REG 1          x0000000000000000

.

.

.

PAL SHADOW REG 7          x0000000000000000

PALTEMP0                  xFFFFFC00006C00C0

PALTEMP1                  x00000000000061A8

PALTEMP2                  xFFFFFC00004E1E00

.

.

.

PALTEMP22                 xFFFFFC00006530E0

PALTEMP23                 x0000000003D2BA58

Exception Address Reg     xFFFFFC000047395C

                                     Native-mode Instruction

                                     Exception PC  x3FFFFF000011CE57

Exception Summary Reg     x0000000000000000

Exception Mask Reg        x0000000000000000

PAL Base Address Reg      x0000000000020000

                              Base Addr for PALcode:  x0000000000000008

Interrupt Summary Reg     x0000000000200000

                                     External HW Interrupt at IPL21

                                     AST Requests 3-0:  x0000000000000000

IBOX Ctrl and Status Reg  x000000C160000000

                                Timeout Counter Bit Clear.

                                IBOX Timeout Counter Enabled.

                                Floating Point Instructions will Cause

                                FEN Exceptions.

                                PAL Shadow Registers Enabled.

                                Correctable Error Interrupts Enabled.

                                ICACHE BIST (Self Test) Was Successful.

                                TEST_STATUS_H Pin Asserted

Icache Par Err Stat Reg   x0000000000000000

Dcache Par Err Stat Reg   x0000000000000000

Virtual Address Reg       x0000000000044000

Memory Mgmt Flt Sts Reg   x0000000000005D10

                                 If Err, Ref Resulted in DTB Miss

                                 Flt Inst RA Field:  x0000000000000014

                                 Fault Inst Opcode:  x000000000000000B

Scache Address Reg        xFFFFFF00000254BF

Scache Status Reg         x0000000000000000

Bcache Tag Address Reg    xFFFFFF8007EE2FFF

                             Last Bcache Access a Miss.

                             Value of Parity Bit for Tag Control Status

                             Bits Dirty, Shared & Valid is Set.

                             Value of Tag Control Dirty Bit is Clear.

                             Value of Tag Control Shared Bit is Clear.

                             Value of Tag Control Valid Bit is Clear.

                             Value of Parity Bit Covering Tag Store

                             Address Bits is Set.

                             Tag Address<38:20> Is:  x000000000000007E

Ext Interface Address Reg xFFFFFF0007FBF08F

Fill Syndrome Reg         x000000000000D189

Ext Interface Status Reg  xFFFFFFF944FFFFFF

                            Error Source is Memory or System

                            UNCORRECTABLE ECC ERROR

                            Error Occurred During D-ref Fill

                            Second External Interface Status Hard Error

LD LOCK                   xFFFFFF0007FBF00F

** IOD SUBPACKET -> **               IOD 0 Register Subpacket

WHOAMI                    x000000BA  Module Revision  0.

                                     VCTY ASIC Rev = 0

                                     Bcache Size = 2MB

                                     MID  2.

                                     GID  7.

Base Address of Bridge    x000000F9E0000000

Dev Type & Rev Register   x06008021  CAP Chip Revision:        x00000001

                             HORSE  Module Revision:   x00000002

                             SADDLE Module Revision:   x00000000

                             SADDLE Module Type:       Left Hand

                             PCI-EISA Bus Bridge Present on PCI Segment

                             PCI Class Code            x00000600

MC-PCI Command Register   x06480FF1  Module SelfTest Passed LED on

                             Delayed PCI Bus Reads Protocol: Enabled

                             Bridge to PCI Transactions: Enabled

                             Bridge REQUESTS 64 Bit Data Transactions

                             Bridge ACCEPTS 64 Bit Data Transactions

                             PCI Address Parity Check: Enabled

                             MC Bus CMD/Addr Parity Check: Enabled

                             MC Bus NXM Check: Enabled

                             Check ALL Transactions for Errors

                             Use MC_BMSK for 16 Byte Align Blk Mem Wrt

                             Wrt PEND_NUM Threshold:  8.

                             RD_TYPE Memory Prefetch Algorithm: Short

                             RL_TYPE Mem Rd Line Prefetch Type: Medium

                             RM_TYPE Mem Rd Multiple Cmd Type:  Long

                             ARB_MODE Arbitration: MC-PCI Priority Mode

Mem Host Addr Ext Reg  x00000000  HAE Sparse Mem Adr<31:27> x00000000

IO Host Adr Ext Reg    x00000000  PCI Upper Adr Bits<31:25> x00000000

Interrupt Ctrl Reg x00000003  Write Device Interrupt Info Struct:Enabld

Interrupt Request         x00800000  Interrupts asserted  x00000000

                                     Hard Error

Interrupt Mask0 Register  x00C50010

Interrupt Mask1 Register  x00000000

MC Error Info Register 0  x07FBF080

                                    MC Bus Trans Addr<31:4>: 7FBF080

MC Error Info Reg 1  x801E8800      MC bus trans addr <39:32> x00000000

                                    MC Command is Read0-Mem

                                    Device ID 2  x00000002

                                    MC bus error assoc w read/dirty

                                    MC error info valid

CAP Error Register       xE0000000  Uncorrectable ECC err det by MDPA

                                    Uncorrectable ECC err det by MDPB

                                    MC error info latched

Sys Environmental Regs    x00000000

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      xC0000000  MDPA Status Reg Data Not Valid

MDPA Error Syndrome Reg   x00080089  MDPA Syndrome Reg Data Not Valid

MDPB Status Register      x80000000  MDPB Status Reg Data Not Valid

MDPB Error Syndrome Reg   x000D00D1  MDPB Syndrome Reg Data Not Valid

** IOD SUBPACKET -> **               IOD 1 Register Subpacket

WHOAMI                    x000000BA  Module Revision  0.

                                     VCTY ASIC Rev = 0

                                     Bcache Size = 2MB

                                     MID  2.

                                     GID  7.

Base Address of Bridge    x000000FBE0000000

Dev Type & Rev Register   x06000021  CAP Chip Revision:        x00000001

                                    HORSE  Module Revision:   x00000002

                                    SADDLE Module Revision:   x00000000

                                    SADDLE Module Type:       Left Hand

                                    Internal CAP Chip Arbiter: Enabled

                                    PCI Class Code            x00000600

MC-PCI Command Register   x06480FF1  Module SelfTest Passed LED on

                               Delayed PCI Bus Read Protoc: Enbld

                               Bridge to PCI Transaction: Enabled

                               Bridge REQUESTS 64 Bit Data Transactions

                               Bridge ACCEPTS 64 Bit Data Transactions

                               PCI Address Parity Check: Enabled

                               MC Bus CMD/Addr Parity Check: Enabled

                               MC Bus NXM Check: Enabled

                               Check ALL Transactions for Errors

                               Use MC_BMSK for 16 Byte Align Blk Mem Wrt

                              Wrt PEND_NUM Threshold:  8.

                              RD_TYPE Memory Prefetch Algorithm: Short

                              RL_TYPE Mem Rd Line Prefetch Type: Medium

                              RM_TYPE Mem Rd Multiple Cmd Type:  Long

                              ARB_MODE Arbitr: MC-PCI Priority Mode

em Host Address Ext Reg  x00000000  HAE Sparse Mem Adr<31:27> x00000000

IO Host Adr Ext Reg      x00000000  PCI Upper Adr Bits<31:25> x00000000

Interrupt Ctrl Reg x00000003  Write Device Interr Info Struct:Enabled

Interrupt Request         x00800001  Interrupts asserted  x00000001

                                     Hard Error

Interrupt Mask0 Register  x00C50001

Interrupt Mask1 Register  x00000000

MC Error Info Register 0  x07FBF080

                                     MC Bus Trans Addr<31:4>: 7FBF080

MC Error Info Register 1  x801E8800  MC bus trans addr <39:32> x00000000

                                     MC Command is Read0-Mem

                                     Device ID 2  x00000002

                                     MC bus error assoc w read/dirty

                                     MC error info valid

CAP Error Register        xE0000000  Uncorrectable ECC err det by MDPA

                                     Uncorrectable ECC err det by MDPB

                                     MC error info latched

Sys Environmental Regs    x00000000

PCI Bus Trans Error Adr   x00000000

MDPA Status Reg        xC0000000  MDPA Status Register Data Not Valid

MDPA Error Syndr Reg   x00080089  MDPA Syndrome Register Data Not Valid

MDPB Status Reg        x80000000  MDPB Status Register Data Not Valid

MDPB Error Syndr Reg   x000D00D1  MDPB Syndrome Register Data Not Valid

PALcode Revision                     Palcode Rev: 1.21-3


MCHK 660 IOD Detected Failure (System Bus Error)
MCHK 660 IOD-Detected Failure (System Bus Error)

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU 0 logged the error in a system with two CPUs.

2.	The External Interface Status register does not record an error.

3.	Both IOD CAP Error registers logged an error.

4.	The MC Error Info registers 0 and 1 captured the error information.

5.	The commander at the time of the error was CPU1 (known from MC_ERR1).

6.	The command on the bus was a write-back memory command.

Since this is an MCHK 660, the IOD detected the error on the bus, and CPU0 is logging the error.  CPU0 registers are not important in this case since it is servicing the IOD interrupt.  There are three devices that can put data on the system bus: CPUs, memory, or an IOD.  From MC_ERR register 1 we know that CPU3 put bad data on the bus while writing to memory.  You may wish to go to troubleshooting IOD-detected errors to get familiarize yourself with a procedure designed to help with IOD-detected errors.

This error log entry has been edited to decrease its size and registers of interest are in bold type.


MCHK 660 IOD Detected Failure (System Bus Error)
MCHK 660 IOD-Detected Failure (System Bus Error)

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number             6.

Timestamp of occurrence              04-APR-1996 17:20:04

Host name                            whip16

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000002

CPU logging event (mperr) x00000000

Event validity                    1. O/S claims event is valid

Event severity                    1. Severe Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   2. 660 Entry

Software Flags            x0000000300000000

                                     IOD 1 Register Subpkt Pres

                                     IOD 2 Register Subpkt Pres

Active CPUs               x00000003

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

* MCHK 660 Regs *

Flags:                    x00000000

PCI Mask                      x0000

Machine Check Reason          x0202

PAL SHADOW REG 0          x00000000

.

.

.

PAL SHADOW REG 7          x00000000

PALTEMP0                  x0000000007

.

.

.

PALTEMP23                 x00000000047FDA58

Exception Address Reg     xFFFFFC000038D784

                                     Native-mode instruction

                                     Exception PC  x3FFFFF00000E35E1

Exception Summary Reg     x00000000

Exception Mask Reg        x00000000

PAL BASE                  x00000000020000

                                   Base addr for palcode =  x0000000008

Interrupt Summary Reg     x00000000200000

                                     EXT. HW interrupt at IPL21

                                     AST requests 3 - 0  x00000000

IBOX Ctrl and Status Reg  x000000C160000000

                                     Timeout Bit Not Set

                                     PAL Shadow Registers Enabled

                                     Correctable Err Intrpts Enabled

                                     ICACHE BIST Successful

                                     TEST_STATUS_H Pin Asserted

Icache Par Err Stat Reg   x00000000

Dcache Par Err Stat Reg   x00000000

Virtual Address Reg       xFFFFFFFFFF800130

Memory Mgmt Flt Sts Reg   x00000000014990

                                     Ref resulted in DTB miss

                                     RA Field  x0000000006

                                     Opcode Field   x00000000000029

Scache Address Reg        xFFFFFF0000024EAF

Scache Status Reg         x00000000

Bcache Tag Address Reg    xFFFFFF80FFED6FFF

                                     Parity for ds and v bits

                                     Cache block dirty

                                     Cache block valid

                                     Tag address<38:20> is   x00000000000FFE

Ext Interface Address Reg xFFFFFF00FC00000F

Fill Syndrome Reg         x0000000000C5D2

Ext Interface Status Reg  xFFFFFFF004FFFFFF

                                     Error occurred during D-ref fill

LD LOCK                   xFFFFFF000020065F

** IOD SUBPACKET -> **               IOD 0 Register Subpacket

WHOAMI                    x000000BA  Device ID  x0000003A

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000F9E0000000

PCI Revision              x06008021  CAP Chip Revision  x00000001

                                     Horse Module Revision  x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     EISA Present

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06480FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enbld

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enbld

                                     Write Pend Number Thresh x00000008

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE  MC-PCI Bridge Priority

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Dev intr info enbld if en_int = 1

Interrupt Request         x00800000  Interrupts asserted  x00000000

                                     Hard Error

Interrupt Mask Register 0 x00C50010

Interrupt Mask Register 1 x00000000

MC Error Info Register 0  x4A26DBF0  MC bus trans addr <31:4>  x04A26DBF

MC Error Info Register 1  x800ED600  MC bus trans addr <39:32> x00000000

                                     MC_Command x00000016

                                     Device Id x0000003B

                                     MC error info valid

CAP Error Register        xA0000000  Uncorrectable ECC err det by MDPA

                                     MC error info latched

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      x80000000  MDPA Chip Revision  x00000000

                                     MDPA Err Syndr of  uncorrectble rd

MDPA Error Syndrome Reg   x1E00001E  Cycle 0 ECC Syndr x0000000000001E

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndr x0000000000001E

MDPB Status Register      x00000000  MDPB Chip Revision  x00000000

MDPB Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

** IOD SUBPACKET -> **               IOD 1 Register Subpacket

WHOAMI                    x000000BA  Device ID  x0000003A

                                     Bcache Size = 2MB

                                     VCTY ASIC Rev = 0

                                     Module Revision  0.

Base Address of Bridge    x000000FBE0000000

PCI Revision              x06000021  CAP Chip Revision  x00000001

                                     Horse Module Revision  x00000002

                                     Saddle Module Revision  x00000000

                                     Saddle Module Type  Left Hand

                                     PCI Class Code  x00000600

MC-PCI Command Register   x06480FF1  Selftest passed

                                     Delayed read enabled

                                     Bridge PCI trans enabled

                                     Req 64 bit data trans enabled

                                     Accept 64 bit data trans enabled

                                     Check PCI Addr Parity enabled

                                     Check MC bus CMS/Addr Parity enbld

                                     Check MC bus NXM enabled

                                     Check all transaction enabled

                                     16 byte aligned block write enbld

                                     Write Pend Number Thresh x00000008

                                     RD_TYPE  Short

                                     RL_TYPE  Medium

                                     RM_TYPE  Long

                                     ARB_MODE  MC-PCI Bridge Priority

Memory Host Addr Exten    x00000000

IO Host Addr Extension    x00000000

Interrupt Control         x00000003  MC-PCI Intr Enabled

                                     Dev intr info enbld if en_int = 1

Interrupt Request         x00800000  Interrupts asserted  x00000000

                                     Hard Error

Interrupt Mask Register 0 x00C50001

Interrupt Mask Register 1 x00000000

MC Error Info Reg 0  x4A26DBF0  MC bus trans addr <31:4>  x04A26DBF

MC Error Info Reg 1  x800ED600  MC bus trans addr <39:32> x00000000

                                     MC_Command x00000016

                                     Device Id x0000003B

                                     MC error info valid

CAP Error Register        xA0000000  Uncorrectable ECC err det by MDPA

                                     MC error info latched

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      x80000000  MDPA Chip Revision  x00000000

                                     MDPA Error Synd of uncorrectable rd

                                                             error

MDPA Error Syndrome Reg   x1E00001E  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

MDPB Status Register      x00000000  MDPB Chip Revision  x00000000

MDPB Error Syndrome Reg   x00000000  Cycle 0 ECC Syndrome x00000000

                                     Cycle 1 ECC Syndrome x00000000

                                     Cycle 2 ECC Syndrome x00000000

                                     Cycle 3 ECC Syndrome x00000000

PALcode Revision                     Palcode Rev: 1.21-3


MCHK 660 IOD Detected Failure (PCI Error)

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU 0 logged the error in a system with three CPUs.

2.	The External Interface Status register records that the error occured during a D-ref Fill but does not indicate what the error is.

3.	The CAP Error register for IOD0 did not see an error.

4.	The CAP Error register for IOD1, however, detects a serious error.

5.	The MC Error Info registers 0 and 1 captured the error information.

6.	The commander at the time of the error was CPU0 and the command was a Read-IO (known from MC_ERR1).

7.	There is a PCI Subpacket from PCI1 with 5 nodes on it.  Three devices on the PCI bus did not see an error, however two did, the Mylsex DAC960 and the DEC_KZPSA either could have caused the parity error.

This error log entry has been edited to decrease its size and registers of interest are in bold type.


MCHK 660 IOD Detected Failure (PCI Error)

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number             2.

Timestamp of occurrence              27-AUG-1996 08:15:41

Host name                            mason3

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000003

CPU logging event (mperr) x00000000

Event validity                    1. O/S claims event is valid

Event severity                    1. Severe Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   2. 660 Entry

Software Flags            x0000002300000000

                                     IOD 0 Register Subpkt Pres

                                     IOD 1 Register Subpkt Pres

                                     PCI 1 Bus Snapshot Present

Active CPUs               x00000007

Hardware Rev              x00000000

System Serial Number                 NI62503MWE

Module Serial Number

Module Type                   x0000

System Revision           x00000000

* MCHK 660 Regs *

Flags:                    x00000000

PCI Mask                      x0002

Machine Check Reason          x0202  IOD-Detected Hard Error -OR-

                                     DTag Parity Error (If Cached CPU)

PAL SHADOW REG 0          x0000000000000000

.

.

.

PAL SHADOW REG 7          x0000000000000000

PALTEMP0                  xFFFFFFFFB589C000

PALTEMP1                  x0000000000000000

.

.

.

PALTEMP22                 xFFFFFC000058D540

PALTEMP23                 x000000007FC67A58

Exception Address Reg     xFFFFFC0000433E0C

                                     Native-mode Instruction

                                     Exception PC  x3FFFFF000010CF83

Exception Summary Reg     x0000000000000000

Exception Mask Reg        x0000000000000000

PAL Base Address Reg      x0000000000020000

                                     Base Addr for PALcode:  x0000000000000008

Interrupt Summary Reg     x0000000000200000

                                     External HW Interrupt at IPL21

                                     AST Requests 3-0:  x0000000000000000

IBOX Ctrl and Status Reg  x000000C160000000

                                     Timeout Counter Bit Clear.

                                     IBOX Timeout Counter Enabled.

                                     Floating Point Instructions will Cause

                                        FEN Exceptions.

                                     PAL Shadow Registers Enabled.

                                     Correctable Error Interrupts Enabled.

                                     ICACHE BIST (Self Test) Was Successful.

                                     TEST_STATUS_H Pin Asserted

Icache Par Err Stat Reg   x0000000000000000

Dcache Par Err Stat Reg   x0000000000000000

Virtual Address Reg       xFFFFFFFFB6ED3D38

Memory Mgmt Flt Sts Reg   x0000000000016211

                                     If Error, Reference Which Caused Was Write

                                     If Err, Reference Resulted in DTB Miss

                                     Fault Inst RA Field:  x0000000000000008

                                     Fault Inst Opcode:  x000000000000002C

Scache Address Reg        xFFFFFF000002502F

Scache Status Reg         x0000000000000000

Bcache Tag Address Reg    xFFFFFF8077AFAFFF

                                     Last Bcache Access Resulted in a Miss.

                                     Value of Parity Bit for Tag Control Status

                                        Bits Dirty, Shared & Valid is Set.

                                     Value of Tag Control Dirty Bit is Clear.

                                     Value of Tag Control Shared Bit is Set.

                                     Value of Tag Control Valid Bit is Set.

                                     Value of Parity Bit Covering Tag Store

                                        Address Bits is Set.

                                     Tag Address<38:20> Is:  x000000000000077A

Ext Interface Address Reg xFFFFFF007E00000F

Fill Syndrome Reg         x000000000000DE08

Ext Interface Status Reg  xFFFFFFF004FFFFFF

                                     Error Occurred During D-ref Fill

LD LOCK                   xFFFFFF0076750B8F

** IOD SUBPACKET -> **               IOD 0 Register Subpacket

WHOAMI                    x000008BA  Module Revision  2.

                                     VCTY ASIC Rev = 0

                                     Bcache Size = 2MB

                                     MID  2.

                                     GID  7.

Base Address of Bridge    x000000F9E0000000

Dev Type & Rev Register   x06008231  CAP Chip Revision:        x00000001

                             HORSE  Module Revision:   x00000003

                             SADDLE Module Revision:   x00000002

                             SADDLE Module Type:        Left Hand

                             PCI-EISA Bus Bridge Present on PCI Segment

                                    PCI Class Code            x00000600

MC-PCI Command Register   x06470FB1  Module SelfTest Passed LED on

                             Delayed PCI Bus Reads Protocol: Enabled

                             Bridge to PCI Transactions: Enabled

                             Bridge WILL NOT REQUEST 64 Bit Data Trans

                             Bridge ACCEPTS 64 Bit Data Transactions

                             PCI Address Parity Check: Enabled

                             MC Bus CMD/Addr Parity Check: Enabled

                             MC Bus NXM Check: Enabled

                             Check ALL Transactions for Errors

                             Use MC_BMSK for 16 Byte Align Blk Mem Wrt

                             Wrt PEND_NUM Threshold:  7.

                             RD_TYPE Memory Prefetch Algorithm: Short

                             RL_TYPE Mem Rd Line Prefetch Type: Medium

                             RM_TYPE Mem Rd Multiple Cmd Type:  Long

                             ARB_MODE Arbitration: MC-PCI Priority Mode

Mem Host Address Ext Reg  x00000000  HAE Sparse Mem Adr<31:27> x00000000

IO Host Adr Ext Register  x00000000  PCI Upper Adr Bits<31:25> x00000000

Interrupt Ctrl Register   x00000003  Write Device Interrupt Info Struct:Enabled

Interrupt Request         x00000000  Interrupts asserted  x00000000

Interrupt Mask0 Register  x00C50110

Interrupt Mask1 Register  x00000000

MC Error Info Register 0  xE0000000

                                     MC Bus Trans Addr<31:4>: E0000000

MC Error Info Register 1  x000E89FD  MC bus trans addr <39:32> x000000FD

                                     MC Command is Read1-IO

                                     CPU0 Master at Time of Error

                                     Device ID 2  x00000002

CAP Error Register        x00000000

Sys Environmental Regs    x00000000

PCI Bus Trans Error Adr   x00000000

MDPA Status Register      x00000000  MDPA Status Register Data Not Valid

MDPA Error Syndrome Reg   x00000000  MDPA Syndrome Register Data Not Valid

MDPB Status Register      x00000000  MDPB Status Register Data Not Valid

MDPB Error Syndrome Reg   x00000000  MDPB Syndrome Register Data Not Valid

** IOD SUBPACKET -> **               IOD 1 Register Subpacket

WHOAMI                    x000008BA  Module Revision  2.

                                     VCTY ASIC Rev = 0

                                     Bcache Size = 2MB

                                     MID  2.

                                     GID  7.

Base Address of Bridge    x000000FBE0000000

Dev Type & Rev Register   x06000231  CAP Chip Revision:        x00000001

                             HORSE  Module Revision:   x00000003

                             SADDLE Module Revision:   x00000002

                             SADDLE Module Type:        Left Hand

                             Internal CAP Chip Arbiter: Enabled

                             PCI Class Code            x00000600

MC-PCI Command Register   x06470FB1  Module SelfTest Passed LED on

                             Delayed PCI Bus Reads Protocol: Enabled

                             Bridge to PCI Transactions: Enabled

                             Bridge WILL NOT REQUEST 64 Bit Data Trans

                             Bridge ACCEPTS 64 Bit Data Transactions

                             PCI Address Parity Check: Enabled

                             MC Bus CMD/Addr Parity Check: Enabled

                             MC Bus NXM Check: Enabled

                             Check ALL Transactions for Errors

                             Use MC_BMSK for 16 Byte Align Blk Mem Wrt

                             Wrt PEND_NUM Threshold:  7.

                             RD_TYPE Memory Prefetch Algorithm: Short

                             RL_TYPE Mem Rd Line Prefetch Type: Medium

                             RM_TYPE Mem Rd Multiple Cmd Type:  Long

                             ARB_MODE Arbitration: MC-PCI Priority Mode

Mem Host Address Ext Reg  x00000000  HAE Sparse Mem Adr<31:27> x00000000

IO Host Adr Ext Register  x00000000  PCI Upper Adr Bits<31:25> x00000000

Interrupt Ctrl Register   x00000003  Write Device Interrupt Info Struct:Enabled

Interrupt Request         x00800000  Interrupts asserted  x00000000

                                     Hard Error

Interrupt Mask0 Register  x00C51111

Interrupt Mask1 Register  x00000000

MC Error Info Register 0  xE0000000

                                     MC Bus Trans Addr<31:4>: E0000000

MC Error Info Register 1  x000E89FD  MC bus trans addr <39:32> x000000FD

                                     MC Command is Read1-IO

                                     CPU0 Master at Time of Error

                                     Device ID 2  x00000002

CAP Error Register        x00000012  Serious error

                                     PCI error address reg locked

Sys Environmental Regs    x00000000

PCI Bus Trans Error Adr   xC0BB6000

MDPA Status Register      x00000000  MDPA Status Register Data Not Valid

MDPA Error Syndrome Reg   x00000000  MDPA Syndrome Register Data Not Valid

MDPB Status Register      x00000000  MDPB Status Register Data Not Valid

MDPB Error Syndrome Reg   x00000000  MDPB Syndrome Register Data Not Valid

PALcode Revision                     Palcode Rev: 1.21-3

** PCI SUBPACKET -> **               PCI 1 Subpacket

Node Qty                          5.

CONFIG Address            x000000FBC0000800

Device and Vendor ID      x00011000  NCR 53C810 NCR_810 SCSI Narrow SingleEnded

                                     Vendor ID:  x1000 (NCR)

                                     Device ID:  x00000001

Command Register       x0147  I/O Space Accesses Response:      Enabled

                       Memory Space Accesses Response:   Enabled

                       PCI Bus Master Capability:        Enabled

                       Monitor for Special Cycle Ops:    DISABLED

                       Generate Mem Wrt/Invalidate Cmds: DISABLED

                       Parity Error Detection Response:  Normal

                       Wait Cycle Address/Data Stepping: DISABLED

                       SERR# Sys Err Driver Capability:  Enabled

                       Fast Back-to-Back to Many Target: DISABLED

Status Register               x0200  Device is 33 Mhz Capable.

                       No Support for User Defineable Features.

                       Fast Back-to-Back to Different Targets,

                       Is Not Supported in Target Device.

                       Device Select Timing:  Medium.

Revision ID                     x02

Device Class Code           x010000  Mass Storage: SCSI Bus Controller

Cache Line S                    x00

Latency T.                      xFF

Header Type                     x00  Single Function Device

Bist                            x00

Base Address Register 1   x00101300

Base Address Register 2   x01119300

Base Address Register 3   x00000000

Base Address Register 4   x00000000

Base Address Register 5   x00000000

Base Address Register 6   x00000000

Expansion Rom Base Addres x00000000

Interrupt P1                    x04

Interrupt P2                    x01

Min Gnt                         x00

Max Lat                         x00

CONFIG Address            x000000FBC0001000

Device and Vendor ID      x00011069  Mylex DAC960 KZPSC RAID Controller

                                     Vendor ID:  x1069 (Mylex)

                                     Device ID:  x00000001

Command Register       x0147  I/O Space Accesses Response:      Enabled

                       Memory Space Accesses Response:   Enabled

                       PCI Bus Master Capability:        Enabled

                       Monitor for Special Cycle Ops:    DISABLED

                       Generate Mem Wrt/Invalidate Cmds: DISABLED

                       Parity Error Detection Response:  Normal

                       Wait Cycle Address/Data Stepping: DISABLED

                       SERR# Sys Err Driver Capability:  Enabled

                       Fast Back-to-Back to Many Target: DISABLED

Status Register               xC200  Device is 33 Mhz Capable.

                       No Support for User Defineable Features.

                       Fast Back-to-Back to Different Targets,

                       Is Not Supported in Target Device.

                       Device Select Timing:  Medium.

                       SIGNALED SYSTEM ERROR: This Device has Set

                       A System Error on SERR# Line.

                       DETECTED PARITY ERROR:This Device Detected

Revision ID                     x02

Device Class Code           x010400

Cache Line S                    x10

Latency T.                      xFF

Header Type                     x00  Single Function Device

Bist                            x00

Base Address Register 1   x00101200

Base Address Register 2   x01119200

Base Address Register 3   x00000000

Base Address Register 4   x00000000

Base Address Register 5   x00000000

Base Address Register 6   x00000000

Expansion Rom Base Addres x01110000

Interrupt P1                    x08

Interrupt P2                    x01

Min Gnt                         x04

Max Lat                         x00

CONFIG Address            x000000FBC0001800

Device and Vendor ID      x00011000  NCR 53C810 NCR_810 SCSI Narrow SingleEnded

                                     Vendor ID:  x1000 (NCR)

                                     Device ID:  x00000001

Command Register      x0147  I/O Space Accesses Response:      Enabled

                      Memory Space Accesses Response:   Enabled

                      PCI Bus Master Capability:        Enabled

                      Monitor for Special Cycle Ops:    DISABLED

                      Generate Mem Wrt/Invalidate Cmds: DISABLED

                      Parity Error Detection Response:  Normal

                      Wait Cycle Address/Data Stepping: DISABLED

                      SERR# Sys Err Driver Capability:  Enabled

                      Fast Back-to-Back to Many Target: DISABLED

Status Register               x0200  Device is 33 Mhz Capable.

                      No Support for User Defineable Features.

                      Fast Back-to-Back to Different Targets,

                      Is Not Supported in Target Device.

                      Device Select Timing:  Medium.

Revision ID                     x02

Device Class Code           x010000  Mass Storage: SCSI Bus Controller

Cache Line S                    x00

Latency T.                      xFF

Header Type                     x00  Single Function Device

Bist                            x00

Base Address Register 1   x00101100

Base Address Register 2   x01119100

Base Address Register 3   x00000000

Base Address Register 4   x00000000

Base Address Register 5   x00000000

Base Address Register 6   x00000000

Expansion Rom Base Addres x00000000

Interrupt P1                    x0C

Interrupt P2                    x01

Min Gnt                         x00

Max Lat                         x00

CONFIG Address            x000000FBC0002000

Device and Vendor ID      x00091011  DECchip 21140 10/100Mhz TULIP Ethernet

                                     Vendor ID:  x1011 (Digital Equip Corp)

                                     Device ID:  x00000009

Command Register     x0147  I/O Space Accesses Response:      Enabled

                     Memory Space Accesses Response:   Enabled

                     PCI Bus Master Capability:        Enabled

                     Monitor for Special Cycle Ops:    DISABLED

                     Generate Mem Wrt/Invalidate Cmds: DISABLED

                     Parity Error Detection Response:  Normal

                     Wait Cycle Address/Data Stepping: DISABLED

                     SERR# Sys Err Driver Capability:  Enabled

                     Fast Back-to-Back to Many Target: DISABLED

Status Register               x0280  Device is 33 Mhz Capable.

                     No Support for User Defineable Features.

                     Fast Back-to-Back to Different Targets,

                     Is Supported in Target Device.

                     Device Select Timing:  Medium.

Revision ID                     x12

Device Class Code           x020000  Network Controller: Ethernet Controller

Cache Line S                    x00

Latency T.                      xFF

Header Type                     x00  Single Function Device

Bist                            x00

Base Address Register 1   x00101000

Base Address Register 2   x01119000

Base Address Register 3   x00000000

Base Address Register 4   x00000000

Base Address Register 5   x00000000

Base Address Register 6   x00000000

Expansion Rom Base Addres x00000000

Interrupt P1                    x10

Interrupt P2                    x01

Min Gnt                         x00

Max Lat                         x00

CONFIG Address            x000000FBC0002800

Device and Vendor ID      x00081011  DEC_KZPSA  Fast-Wide-Differential SCSI

                                     Vendor ID:  x1011 (Digital Equip Corp)

                                     Device ID:  x00000008

Command Register      x0147  I/O Space Accesses Response:      Enabled

                      Memory Space Accesses Response:   Enabled

                      PCI Bus Master Capability:        Enabled

                      Monitor for Special Cycle Ops:    DISABLED

                      Generate Mem Wrt/Invalidate Cmds: DISABLED

                      Parity Error Detection Response:  Normal

                      Wait Cycle Address/Data Stepping: DISABLED

                      SERR# Sys Err Driver Capability:  Enabled

                      Fast Back-to-Back to Many Target: DISABLED

Status Register              xE2C0  Device is 33 Mhz Capable.

                      Device Supports User Defineable Features.

                      Fast Back-to-Back to Different Targets,

                      Is Supported in Target Device.

                      Device Select Timing:  Medium.

                      RECEIVED MASTER-ABORT:Master Sets When Its

                      Transaction Terminated by MasterAbort.

                      SIGNALED SYSTEM ERROR: This Device has Set

                      A System Error on SERR# Line.

                      DETECTED PARITY ERROR:This Device Detected

Revision ID                     x00

Device Class Code           x010000  Mass Storage: SCSI Bus Controller

Cache Line S                    x10

Latency T.                      xFF

Header Type                     x00  Single Function Device

Bist                            x80

Base Address Register 1   x01118000

Base Address Register 2   x00000000

Base Address Register 3   x00100000

Base Address Register 4   x01000000

Base Address Register 5   x00000000

Base Address Register 6   x00000000

Expansion Rom Base Addres x01100000

Interrupt P1                    x14

Interrupt P2                    x01

Min Gnt                         x08

Max Lat                         x7F


MCHK 630 Correctable CPU Error
MCHK 630 CPU Correctable Error

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU 0 logged the error in a system with two CPUs.

2.	During a D-ref fill, the External Interface Status register shows no error but states that the data source is b-cache.

3.	Both IOD CAP Error registers logged no error.

4.	The FIL Syndrome register has a valid ECC code for the lower half of the data.

Machine check 630s are detected by CPUs when they either take data off the system bus or when they access their own B-cache.  In this case, the data did not come from the system bus; otherwise bit <30> would be set in the External Interface Status register.  CPU0 had a single-bit, ECC correctable error.


MCHK 630 Correctable CPU Error Example

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number           415.

Timestamp of occurrence              09-MAY-1996 14:56:30

Host name                            whip16

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000002

CPU logging event (mperr) x00000000

Event validity                    1. O/S claims event is valid

Event severity                    3. High Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   3. Bcache error (630 entry)

Software Flags            x00000000

Active CPUs               x00000003

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

Machine Check Reason      x0086  AlphaChip Dtctd ECC Err, From B-Cache

EI STAT                   xFFFFFFF004FFFFFF

                                     DATA SOURCE IS BCACHE

                                     D-ref fill

                                     EV5 Chip Rev 4

EI ADDRESS                xFFFFFF00138D85EF

FIL SYNDROME              x00000000000800

ISR                       x0000000100200000

WHOAMI                    x00000000  Module Revision  0.

                                     MID  0.

                                     GID  0.

Sys Environmental Regs    x00000000

Base Addr of Bridge       x00000000

Dev Type & Rev Register   x00000000  CAP Chip Revision:      x00000000

                                     Horse Module Revision:   x00000000

                                     Saddle Module Revision:   x00000000

                                     SADDLE Module Type:        Left Hand

                                     Internal CAP Chip Arbiter: Enabled

                                     PCI Class Code            x00000000

MC Error Info Register 0  x00000000

                                     MC Bus Trans Addr<31:4>: 0

MC Error Info Reg 1  x00000000  MC bus trans addr <39:32> x00000000

                                     MC Command is Illegal

                                     Illegal

                                     Device ID 2  x00000000

CAP Error Register        x00000000

MDPA Status Reg      x00000000  MDPA Status Register Data Not Valid

MDPA Error Syndr Reg   x00000000  MDPA Syndrome Register Data Not Valid

MDPB Status Reg      x00000000  MDPB Status Register Data Not Valid

MDPB Error Syndr Reg   x00000000  MDPB Syndrome Register Data Not Valid

PALcode Revision                     Palcode Rev: 1.21-3


MCHK 620 Correctable Error

The MCHK 620 error is a correctable error detected by the IOD.

To determine what failed, you need to identify the error.

From the log you can see:

1.	CPU0 logged the error in a system with two CPUs.

2.	The External Interface Status register is not valid.

3.	The MC Error Info registers 0 and 1 captured the error information.

4.	The commander at the time of the error was CPU0.

5.	The command was a WriteThru memory command.

The IOD detected a recoverable error on the system bus. The MC command at the time of the error is a WriteThru-Mem Command (x00000006).  The commander at the time of the error is CPU0.  Since this is a write, the defective FRU is CPU0.


MCHK 620 Correctable Error

Logging OS                        2. Digital UNIX

System Architecture               2. Alpha

Event sequence number            32.

Timestamp of occurrence              28-JUN-1996 19:45:42

Host name                            sect06

System type register      x00000016  AlphaStation 4x00

Number of CPUs (mpnum)    x00000002

CPU logging event (mperr) x00000000

Event validity                    1. O/S claims event is valid

Event severity                    5. Low Priority

Entry type                      100. CPU Machine Check Errors

CPU Minor class                   4. 620 System Correctable Error

Software Flags            x0000000000000000

Active CPUs               x00000003

Hardware Rev              x00000000

System Serial Number                 C1563

Module Serial Number

Module Type                   x0000

System Revision           x00000000

Machine Check Reason          x0204  IOD Detected Soft Error

Ext Interface Status Reg  x0000000000000000

                                     Not Valid for 620 System

                                     Correctable Errors

Ext Interface Address Reg x0000000000000000

                                     Not Valid for 620 System

                                     Correctable Errors

Fill Syndrome Reg         x0000000000000000

                                     Not Valid for 620 System

                                     Correctable Errors

Interrupt Summary Reg     x0000000000000000

                                     Not Valid for 620 System

                                     Correctable Errors

WHOAMI                    x00000000  Module Revision  0.

                                     MID  0.

                                     GID  0.

Sys Environmental Regs    x00000000

Base Addr of Bridge       x000000FBE0000000

Dev Type & Rev Register   x06000032  CAP Chip Revision:       x00000002

                                     HORSE  Module Revision:  x00000003

                                     SADDLE Module Revision:  x00000000

                                     SADDLE Module Type:      Left Hand

                                     Internal CAP Chip Arbiter: Enabled

                                     PCI Class Code         x00000600

MC Error Info Register 0  x122D5640

                                     MC Bus Trans Addr<31:4>: 122D5640

MC Error Info Register 1  x800E9600  MC bus trans addr <39:32> x00000000

                                     MC Command is WriteBack Mem

                                     CPU0 Master at Time of Error

                                     Device ID 2  x00000002

                                     MC error info valid

CAP Error Register        x89000000  Error Detected but Not Logged

                                     Correctable ECC err det by MDPA

                                     MC error info latched

MDPA Status Reg      x00000000  MDPA Status Register Data Not Valid

MDPA Error Syndr Reg   x00000000  MDPA Syndrome Register Data Not Valid

MDPB Status Reg      x00000000  MDPB Status Register Data Not Valid

MDPB Error Syndr Reg   x00000000  MDPB Syndrome Register Data Not Valid

PALcode Revision                     Palcode Rev: 0.0-1


Gonfiguration Entry
Configuration Entry

Configuration entries provide basic information about the system.  The example was truncated to show only memory.  To determine which memory pair is defective, you need the base address of each pair.  The configuration entry gives that information.

This entry shows a system with 3 pairs (6 cards) of memory modules configured as follows:

Slot	Size of Pair	Base Address	Ending Address
0	2, 048 Mb	0	7FFF FFFF
1	512 Mb	8000 0000	BFFF FFFF
2	512 Mb	1 0000 0000	1 BFFF FFFF

Note that the beginning address of the memory pair in slot 2 is on the 4-Mbyte boundary even though the memory pair in slot 1 is 518 Mbytes.  This is an example of physical addressing involving a memory hole.  There is a total of 3,072 Mbytes of physical memory.

For a table showing hex addresses, clickhere.


Configuration Log Entry

.

.

.

========================

Config Subpacket Type                3. MEMORY

Packet Revision                              x0001

Number of FRU Subpackets          3.

Memory Size                                   x00000A00  Mbytes Installed:  3072.

Memory Available                         x00000A00  Mbytes Available:  3072.

 - - - - - - - - - - - -

FRU Config Subpacket Type         2. Specific FRU Subpacket

FRU Subpacket Revision                x0001

FRU Manufacturer                                                            Digital

FRU Model       0

FRU Part Number       0

FRU Serial Number     0

FRU Revision Level0

FRU Firmware Rev Level   0

Slot                              0.

Self Test Status          x00010000  Self Test NOT Available

Self Test Information        0

Memory Module Size             2048. Mega Bytes

Memory Module Base Addr   x0000000000000000

Memory Module Type        x00000002  EDO DRAM Memory Card

 - - - - - - - - - - - -

FRU Config Subpacket Type         2. Specific FRU Subpacket

FRU Subpacket Revision        x0001

FRU Manufacturer                                                            Digital

FRU Model                                                                       0

FRU Part Number                                                             0

2RU Serial Number                                                           0

FRU Revision Level                                                            0

FRU Firmware Rev Level                                                   0

Slot                              1.

Self Test Status          x00010000  Self Test NOT Available

Self Test Information                                                       0

Memory Module Size              512. Mega Bytes

Memory Module Base Addr   x0000000080000000

Memory Module Type        x00000002  EDO DRAM Memory Card

 - - - - - - - - - - - -

FRU Config Subpacket Type         2. Specific FRU Subpacket

FRU Subpacket Revision        x0001

FRU Manufacturer                                                            Digital

FRU Model                                                                       0

FRU Part Number                                                             0

2RU Serial Number                                                           0

FRU Revision Level                                                            0

FRU Firmware Rev Level                                                   0

Slot                              2.

Self Test Status          x00010000  Self Test NOT Available

Self Test Information                                                       0

Memory Module Size              512. Mega Bytes

Memory Module Base Addr   x0000000100000000

Memory Module Type        x00000002  EDO DRAM Memory Card


Troublshooting IOD Detected Errors
Troubleshooting IOD-Detected Errors

Here is a procedure to isolate errors to the FRU.

Step 1

Read the CAP_ERR registers on both PCI bridges (F9E0000880 and FBE0000880). If one or both of these registers shows an error, match the contents with the data pattern in the window below and perform the action indicated.


CAP Error Register Data Pattern
CAP Error Register Data Pattern 1

Data Pattern	Most Likely Cause	Action
110x x00x x000 0 0 0 000x X	RDSB - Uncorrectable ECC error detected on upper QW of MC bus (D127:64>), bit <30> set	Go to Step 2
101x x00x x000 0 0 0 000x X	RDSA - Uncorrectable ECC error detected on lower QW of MC bus (D63:0>), bit <29> set	Go to Step 2
111x x00x x000 0 0 0 000x X	Both RDSA and RDSB detected an uncorrectable ECC error on the upper and lower QW of MC bus (D63:0>), bits <30:29> set	Go to Step 2
9 0 x000 0 0 0 000x X	CRDB - Correctable ECC error detected on upper QW of MC bus (D127:64>), bit <28> set	Go to Step 2
8 8 x000 0 0 0 000x X	CRDA - Correctable ECC error detected on lower QW of MC bus (D63:0>), bit <27> set	Go to Step 2
9 8 x000 0 0 0 000x X	Both CRDA and CRDB - detected a correctable ECC error on upper and lower QW of MC bus (D127:64>), bits <28:27> set	Go to Step 2
100x x10x x000 0 0 0 000x X	NXM - Nonexistent MC bus address, bit <26> set	Go to Step 3
100x x01x x000 0 0 0 000x X	MC_ADR_PERR - MC bus address parity error, bit <27> set	Go to Step 4
100x x00x 8 0 0 0 000x X	PIO_OVFL - PIO buffer overflow, bit <25> set	Go to Step 5
0 0 0 0 0 01 1xxx	PTE_INV - Page table entry is invalid, bits <4> and <3> set	Go to Step 6
0 0 0 0 0 0 1 x1xx	MAB - Master abort, bits <4> and <2> set	Go to Step 7
0 0 0 0 0 0 1 xx1x	SERR - PCI system error, bits <4> and <1> set	Go to Step 8
0 0 0 0 0 0 1 xxx1	PERR - PCI parity error, bits <4> and <0> set	Go to Step 9
1 The data pattern shown is a combination of binary and hexadecimal.  When a nibble (4 bits) is a known hex number, it is so expressed.  When the nibble is not a whole hex number, the data pattern is expressed in binary.  If the value of the nibble is do not care, it is expressed as an X.  For example, 110x x00x x000 0000 0000 0000 000x xxxx is expressed 110x x00x x000 0 0 0 000x X.


System Bus ECC Error

Step 2

Read the MC_ERR1 register and match the contents with the data pattern in the window below.  Perform the action indicated.

System Bus ECC Error Data Pattern 1

MC_ERR1 Data Pattern	Most Likely Cause	Action

for Memory Read

8 0 0 X X 10xx 0xxx X	Bad nondirty data from memory (bad memory)	Go to Step 10
8 0 0 X X 111x 0xxx X	Bad nondirty data from memory (bad memory)	Go to Step 10
8 0 1 X X 10xx 0xxx X	Bad dirty data from a CPU	Replace CPU(s)
8 0 1 X X 111x 0xxx X	Bad dirty data from a CPU	Replace CPU(s)

for Memory or I/O Write

8 0 000x xxx0 10xx 011x X X	Bad data from MID = 2	Replace CPU 0
8 0 000x xxx0 11xx 011x X X	Bad data from MID = 3	Replace CPU 1
8 0 000x xxx1 00xx 011x X X	Bad data from MID = 4	Replace Bridge 0
8 0 000x xxx1 01xx 011x X X	Bad data from MID = 5	Replace Bridge 0
8 0 000x xxx1 10xx 011x X X	Bad data from MID = 6	Replace CPU 2 or Replace Bridge 1
8 0 000x xxx1 11xx 011x X X	Bad data from MID = 7	Replace CPU 3 or Replace Bridge 1

for Memory Fill Transactions

8 0 000x xxx1 00xx 110x X X	Bad data from MID = 4	Replace Bridge 0
8 0 000x xxx1 01xx 110x X X	Bad data from MID = 5	Replace Bridge 0
8 0 000x xxx1 10xx 110x X X	Bad data from MID = 6	Replace Bridge 1
8 0 000x xxx1 11xx 110x X X	Bad data from MID = 7	Replace Bridge 1
1 The data pattern shown is a combination of binary and hexadecimal.  When a nibble (4 bits) is a known hex number, it is so expressed.  When the nibble is not a whole hex number, the data pattern is expressed in binary.  If the value of the nibble is do not care, it is expressed as an X.  For example 110x x00x x000 0000 0000 0000 000x xxxx is expressed 110x x00x x000 0 0 0 000x X.


NXM MC Bus Nonexistent Address Error
System Bus Nonexistent Address Error

Step 3

Determine which node (if any) should have responded to the command/address identified in MC_ERR1.

Perform the action indicated.

System Bus Nonexistent Address Error Troubleshooting

MC_ERR1 Data Pattern 1	Most Likely Cause	Action
8 0 000x X X X 0xxx X	Software generated an MC ADDR > TOP_OF_MEM reg.	Fix software
8 0 0 X X X 1xxx 0xxx	Software generated an I/O MC ADDR to a nonexistant I/O node.	Fix software
8 0 0 X X X 1xxx 100x	PCI0 bridge did not respond	Replace Bridge
8 0 0 X X X 1xxx 101x	PCI1 bridge did not respond	Replace Bridge
8 0 0 X X X 1xxx 110x	For 4000/4100 For 4000A, PCI2 bridge did not respond	Fix software Replace Bridge
8 0 0 X X X 1xxx 111x	For 4000/4100  For 4000A, +-PCI3 bridge did not respond	Fix software Replace Bridge
1 The data pattern shown is a combination of binary and hexadecimal.  When a nibble (4 bits) is a known hex number, it is so expressed.  When the nibble is not a whole hex number, the data pattern is expressed in binary.  If the value of the nibble is do not care, it is expressed as an X.  For example, 110x x00x x000 0000 0000 0000 000x xxxx is expressed 110x x00x x000 0 0 0 000x X.


System Bus Address Parity Error

Step 4

Determine which node put the bad command/address on the system bus identified in MC_ERR1.

Perform the action indicated.

Address Parity Error Troubleshooting

MC_ERR1 Data Pattern1	Most likely cause	Action
8 0 000x xxx0 10xx X X X	Bad data from  MID = 2	Replace CPU 0
8 0 000x xxx0 11xx X X X	Baddata from MID = 3	Replace CPU 1
8 0 000x xxx0 00xx X X X	Bad data from MID = 4	Replace Bridge 0
8 0 000x xxx1 01xx X X X	Bad data from MID = 5	Replace Bridge 0
8 0 000x xxx1 10xx X X X	Bad data from MID = 6	Replace CPU 2 or Replace Bridge 1
8 0 000x xxx1 11xx X X X	Bad data from MID = 7 or	Replace CPU 3 or Replace Bridge 1
1 The data pattern shown  is a combination of binary and hexadecimal.  When a nibble (4 bits) is a known hex number, it is so expressed.  When the nibble is not a whole hex number, the data pattern is expressed in binary.  If the value of the nibble is do not care, it is expressed as an X.  For example 110x x00x x000 0000 0000 0000 000x xxxx is expressed 110x x00x x000 0 0 0 000x X.


PIO Buffer Overflow Error
PIO Buffer Overflow Error (PIO_OVFL)

Step 5

Enter the value of the CAP_CTRL register bits<19:16> (Actual_PEND_NUM) in the following formula. Compare the results as indicated in the table to determine the most likely cause of the error.  When an IOD is implicated in the analysis of the error, replace the one that capturered the error in its CAP Error Register.

Expected_PEND_NUM = 12 - ((2 * (X - 1)) + Y)

Where:  X = Number of PCIs

Y = Number of CPUs

Comparison	Most Likely Cause	Action
Actual_PEND_NUM = Expected_PEND_NUM	Broken hardware on IOD	Replace Bridge
Actual_PEND_NUM < Expected_PEND_NUM	Broken hardware on IOD	Replace Bridge
Actual_PEND_NUM > Expected_PEND_NUM	PEND_NUM setup incorrect	Fix the software


Page Table Entry Invalid Error

Step 6

This error is almost always a software problem.  However, if the software is known to be good and the hardware is suspected, replace the Bridge.


PCI Master Abort

Step 7

Master aborts normally occur when the operating system is sizing the PCI bus. However, if the master abort occurs after the system is booted, read PCI_ERR1 and determine which PCI device should have responded to this PCI address. Replace this device.


PCI System Error

Step 8

For this error to occur some PCI device asserted SERR.  Read the error registers in all the PCI devices to determine which.  The PCI device that set SERR should have information logged in its error registers that should indicate a device.


PCI Parity Error

Step 9

Read PCI_ERR1 and determine which PCI device normally uses that particular PCI address space.  Replace that device. Also, read the error registers in all the PCI devices to determine which device was driving the PCI bus when the parity error occurred.


Broken Memory

Step 10

For a Read Data Substitute Error (uncorrectable ECC error):

When an RDS error occurs, determine which memory module pair caused the error as follows:

1.	Run the memory diagnostic to see if it catches the bad memory. If so, then replace the memory module that it reports as bad.

2.	 At the SRM console prompt, enter the show mem command:

                  P00>>> show mem

This command displays the base address and size of the memory module pair for each slot.

OR

      Read the configuration packet, found in the error log, to retrieve the base address and size of the memory module pair.

3.	Compare this address to the failing address from the MC_ERR1 and MC_ERR0 registers to determine which memory slot is failing.

Replace both memory modules (high and low) for that slot.  For an RDS error, there is no way to know which memory module (high or low) is bad.  (There is no ECC syndrome available.)

For a Corrected Read Data Error:

When a CRD error occurs, determine which memory module pair caused the error as follows:

1.	At the SRM console prompt, enter the show mem command:

                  P00>>> show mem

This command displays the base address and size of the memory module pair for each slot.

2.	Compare this address to the failing address from the MC_ERR1 and MC_ERR0 registers to determine which memory slot is failing.

3.	When you have isolated the failing memory pair, determine which of the two modules is bad.  (This can be done when the operating system is not NT.)

4.	Read the CPU FIL Syndrome register.  If this register is non-zero, use the ECC syndrome bits in the table below to determine which module had the single bit error.

ECC Syndrome Bits

MDP Syndrome Values for Low Order Memory

01	02	04	08	10	20	40	80	CE
CB	D3	D5	D6	D9	DA	DC	23	25
26	29	2C	31	13	19	4F	4A	52
54	57	58	5B	5D	A2	A4	A8	B0

MDP Syndrome Values for High Order Memory

2A	34	0E	0B	15	16	1A	1C	E3
E5	E6	E9	EA	EC	F1	F4	A7	AB
AD	B5	8F	8A	92	94	97	98	9B
9D	62	64	67	68	6B	6D	70	75


An RDS, a read data substitute, is the same as an uncorrectable ECC error.


A CRD, a corrected read data, is the same as a correctable ECC error.


Hex Address Chart

Number of Bits	Hex	Size	Number of Bits	Hex	Size
16	FFFF	64 KB	29	1FF FFFF	512 MB
17	1 FFFF	128 KB	30	3FF FFFF	1 GB
18	3 FFFF	256 KB	31	7FF FFFF	2 GB
19	7 FFFF	512 KB	32	FFF FFFF	4 GB
20	F FFFF	1 MB	33	1FF FFFF	8 GB
21	1F FFFF	2 MB	34	3FF FFFF	16 GB
22	3F FFFF	4 MB	35	7FF FFFF	32 GB
23	7F FFFF	8 MB	36	FFF FFFF	64 GB
24	FF FFFF	16 MB	37	1FFF FFFF	128 GB
25	1F FFFF	32 MB	38	3FFF FFFF	256 GB
26	3F FFFF	64 MB	39	7FFF FFFF	512 GB
27	7F FFFF	128 MB	40	FFFF FFFF	1 TB
28	FF FFFF	256 MB


Command Codes
This table shows the codes for transactions on the system bus. The command is a 6-bit field in the command address (bits<5:0>).  Although there are six bits, the top two bit may or may not be relevant.  Note the effect that address bit<39> has on the command.

5 4	MC_CMD 3 2 1 0	CMD in Hex	MC_ADR <39>	Description
x x	0 0 0 0	X 0	1	Mem Idle
0 0	0 0 1 0	0 2	1	Write Pend Ack
x x	0 0 1 1	X 3	1	Mem Refresh
x x	0 1 0 1	X 4	0	Set Dirty
x 0	0 1 1 0	0/2 6	0	Write Thru - Mem
x 0	0 1 1 0	0/2 6	1	Write Thru - I/O
x 1	0 1 1 0	3/1 6	0	Write Back - Mem
x 1	0 1 1 0	3/1 6	1	Write Intr - I/O
0 0	0 1 1 1	0 7	0	Write Full - Mem
1 0	0 1 1 1	2 7	0	Write Part - Mem (B-cache CPU only)
x 0	0 1 1 1	0/2 7	1	Write Mask - I/O
x 0	0 1 1 1	0/2 7	0	Write Merge - Mem
x x	1 0 0 0	X 8	0	Read0 - Mem
x x	1 0 0 0	X 8	1	Read0 - I/O
x x	1 0 0 1	X 9	0	Read1 - Mem
x x	1 0 0 1	X 9	1	Read1 - I/O
x x	1 0 1 0	X A	0	Read Mod0 - Mem
x x	1 0 1 0	X A	1	Read Peer0 - I/O
x x	1 0 1 1	X B	0	Read Mod1 - Mem
x x	1 0 1 1	X B	1	Read Peer1 - I/O
1 0	1 1 0 0	2 C	1	FILL0 (due to Read0/Peer0)
1 0	1 1 0 1	2 D	1	FILL1 (due to Read1/Peer1)
x x	1 1 1 0	X E	0	Read0 - Mem
x x	1 1 1 1	X F	0	Read1 - Mem


Node IDs

The node ID or device ID is made up of two 3-bit fields in the command address (bits<38:33>).  The high-order three bits are always set, and the last three indicate the node.  Bit-to-text translations give either 6-bit data though only the last three bits define the node or three-bit data.  You need to interpret either.

Node ID <2:0>	Six Bits (hex)	Three Bits (hex)	Module ID (4100)	Module ID (4000)
0 0 0	38	0
0 0 1	39	1	Memory	Memory
0 1 0	3A	2	CPU 0	CPU 0
0 1 1	3B	3	CPU 1	CPU 1
1 0 0	3C	4	IOD 0	IOD 0
1 0 1	3D	5	IOD 1	IOD 1
1 1 0	3E	6	CPU 2	IOD 2
1 1 1	3F	7	CPU 3	IOD 3


Double Error Halts and Macnine Check while in PAL; Info 3 command; Info 8 command; Info 5 command;
Double Error Halts and Machine Check while Running PALcode

Two error cases require special attention.  Neither double error halts nor machine checks while the machine is in PAL mode result in error log entries.  Nevertheless information is still available that can help determine what error occurred.

How errors are handled is described by the error flowchart to the left.

Double Error Halt

A double error halts occurs when:

1.	A machine check occurs.

2.	PAL completes its tasks and returns control of the system to the OS.

3,	A second machine check occurs before the OS completes its tasks.

In such a case the machine returns to the console and writes the following message.

halt code = 6

double error halt

PC  =  20000004

Your system has halted due to an unrecoverable error.  Record the error  halt code and PC and contact your Digital Services representative.  In addition, type INFO 5 (definition) and INFO 8 (definition) at the console and record the results.

P00>>>   info 5           # example

.

.

.

P00>>>   info 8           # example

Machine Checks while Running PALcode

A machine check while in PAL occurs when:

1.	A machine check occurs while the system is running PAL code.

In such a case, PALcode returns to the console, not to the operating system.  The SRM console writes the following message.

halt code = 7

machine check while in PAL mode

PC  =  20000004

Your system has halted due to an irrecoverable error.  Record the error  halt code and PC and contact your Digital Services representative.  In addition, type INFO 3 (definition) and INFO 8 at the console and record the results.

P00>>> info 3            # example

.

.

.

P00>>> info 8           # example


PALcode, privileged architecture library code, is used to implement a number of functions at the machine level without the use of microcode.  This allows operating systems to make common calls to PALcode routines without knowing the hardware specifics of each system the operating system is running on.  PALcode routines handle:

• 	Instructions that require complex sequencing such as atomic operations

•	Instructions that require VAX style interlocked memory access

•	Privileged instructions

•	Memory management

•	Context swapping

•	Interrupt and exception dispatching

•	Power-up initialization and booting

•	Console functions

•	Emulation of instructions with no hardware support


The info 3 command causes the SRM console to read the impure area that contains the state of the CPU before it entered PAL.


The info 5 command causes the SRM console to read the PAL-built logout area that contains the data used by the operating system to create the error entry.


The info 8 command causes the SRM console to read IOD 0 and IOD1 registers.


Example of the INFO 3 Command

P00>>> info 3

                      cpu00

per_cpu impure area	00004400
cns$flag	00000001 : 0000
cns$flag+4	00000000 : 0004
cns$hlt	00000000 : 0008
cns$hlt+4	00000000 : 000c
cns$mchkflag	00000228 : 0210
cns$mchkflag+4	00000000 : 0214
cns$exc_addr	20000004 : 0318
cns$exc_addr+4	00000000 : 031c
cns$pal_base	00000000 : 0320
cns$pal_base+4	00000000 : 0324
cns$mm_stat	0000da10 : 0338
cns$mm_stat+4	00000000 : 033c
cns$va	00080000 : 0340
cns$va+4	00000002 : 0344
cns$icsr	40000000 : 0348
cns$icsr+4	000000c1 : 034c
cns$ipl	0000001f : 0350
cns$ipl+4	00000000 : 0354
cns$ps	00000000 : 0358
cns$ps+4	00000000 : 035c
cns$itb_asn	00000000 : 0360
cns$itb_asn+4	00000000 : 0364
cns$aster	00000000 : 0368
cns$aster+4	00000000 : 036c
cns$astrr	00000000 : 0370
cns$astrr+4	00000000 : 0374
cns$isr	00400000 : 0378
cns$isr+4	00000000 : 037c
cns$ivptbr	00000000 : 0380
cns$ivptbr+4	00000002 : 0384
cns$mcsr	00000000 : 0388
cns$mcsr+4	00000000 : 038c
cns$dc_mode	00000001 : 0390
cns$dc_mode+4	00000000 : 0394
cns$maf_mode	00000080 : 0398
cns$maf_mode+4	00000000 : 039c
cns$sirr	00000000 : 03a0
cns$sirr+4	00000000 : 03a4
cns$fpcsr	00000000 : 03a8
cns$fpcsr+4	ff900000 : 03ac
cns$icperr_stat	00000000 : 03b0
cns$icperr_stat+4	00000000 : 03b4
cns$pmctr	00000000 : 03b8
cns$pmctr+4	00000000 : 03bc
cns$exc_sum	00000000 : 03c0
cns$exc_sum+4	00000000 : 03c4
cns$exc_mask	00000000 : 03c8
cns$exc_mask+4	00000000 : 03cc
cns$intid	00000016 : 03d0
cns$intid+4	00000000 : 03d4
cns$dcperr_stat	00000000 : 03d8
cns$dcperr_stat+4	00000000 : 03dc
cns$sc_stat	00000000 : 03e0
cns$sc_stat+4	00000000 : 03e4
cns$sc_addr	000047cf : 03e8
cns$sc_addr+4	ffffff00 : 03ec
cns$sc_ctl	0000f000 : 03f0
cns$sc_ctl+4	00000000 : 03f4
cns$bc_tag_addr	ff7fefff : 03f8
cns$bc_tag_addr+4	ffffffff : 03fc
cns$ei_stat	04ffffff : 0400
cns$ei_stat+4	fffffff0 : 0404
cns$fill_syn	000000a7 : 0410
cns$fill_syn+4	00000000 : 0414
cns$ld_lock	0004eaef : 0418
cns$ld_lock+4	ffffff00 : 041c


Example of the INFO 5 Command

P00>>> info 5

cpu00

per_cpu logout area	00004838
mchk$crd_flag	00000320 : 0000
mchk$crd_flag+4	00000000 : 0004
mchk$crd_offsets	00000118 : 0008
mchk$crd_offsets+4	00001328 : 000c
mchk$crd_mchk_code	00980000 : 0010
mchk$crd_mchk_code+4	00000000 : 0014
mchk$crd_ei_stat	eba00003 : 0018
mchk$crd_ei_stat+4	4143040a : 001c
mchk$crd_ei_addr	d1200067 : 0020
mchk$crd_ei_addr+4	47f90416 : 0024
mchk$crd_fill_syn	eba00003 : 0028
mchk$crd_fill_syn+4	d1200068 : 002c
mchk$crd_isr	7ec38000 : 0030
mchk$crd_isr+4	63ff4000 : 0034
mchk$flag	00000320 : 0000
mchk$flag+4	00000000 : 0004
mchk$isr	00000000 : 0138
. mchk$isr+4	00000000 : 013c
mchk$icsr	60000000 : 0140
mchk$icsr+4	000000c1 : 0144
mchk$ic_perr_stat	00000000 : 0148
mchk$ic_perr_stat+4	00000000 : 014c
mchk$dc_perr_stat	00000000 : 0150
mchk$dc_perr_stat+4	00000000 : 0154
mchk$va	ff8000a0 : 0158
mchk$va+4	ffffffff : 015c
mchk$mm_stat	000149d0 : 0160
mchk$mm_stat+4	00000000 : 0164
mchk$sc_addr	0001904f : 0168
mchk$sc_addr+4	ffffff00 : 016c
mchk$sc_stat	00000000 : 0170
mchk$sc_stat+4	00000000 : 0174
mchk$bc_tag_addr	ff7fefff : 0178
mchk$bc_tag_addr+4	ffffffff : 017c
mchk$ei_addr	066bc3ef : 0180
mchk$ei_addr+4	ffffff00 : 0184
mchk$fill_syn	000000a7 : 0188
mchk$fill_syn+4	00000000 : 018c
mchk$ei_stat	04ffffff : 0190
mchk$ei_stat+4	fffffff0 : 0194
mchk$ld_lock	00005b6f : 0198
mchk$ld_lock+4	ffffff00 : 019c

IOD: 0 base address: f9e0000000

WHOAMI:	0000003a	PCI_REV:	06008221
CAP_CTL:	02490fb1	HAE_MEM:	00000000	HAE_IO:	00000000
INT_CTL:	00000003	INT_REQ:	00800000	INT_MASK0:	00010000
INT_MASK1:	00000000	MC_ERR0:	e0000000	MC_ERR1:	800e88fd
CAP_ERR:	84000000	PCI_ERR:	00000000	MDPA_STAT:	00000000
MDPA_SYN:	00000000	MDPB_STAT:	00000000	MDPB_SYN:	00000000

IOD: 1 base address: fbe0000000

WHOAMI:	0000003a	PCI_REV:	06000221
CAP_CTL:	02490fb1	HAE_MEM:	00000000	HAE_IO:	00000000
INT_CTL:	00000003	INT_REQ:	00800000	INT_MASK0:	00010000
INT_MASK1:	00000000	MC_ERR0:	e0000000	MC_ERR1:	800e88fd
CAP_ERR:	84000000	PCI_ERR:	00000000	MDPA_STAT:	00000000
MDPA_SYN:	00000000	MDPB_STAT:	00000000	MDPB_SYN:	00000000


Example of the INFO 8 Command

P00>>> info 8

IOD 0

WHOAMI:	0000003a	PCI_REV:	06008221
CAP_CTL:	02490fb1	HAE_MEM:	00000000	HAE_IO:	00000000
INT_CTL:	00000003	INT_REQ:	00000000	INT_MASK0:	00210000
INT_MASK1:	00000000	MC_ERR0:	e0000000	MC_ERR1:	000e88fd
CAP_ERR:	00000000	PCI_ERR:	00000000	MDPA_STAT:	00000000
MDPA_SYN:	00000000	MDPB_STAT:	00000000	MDPB_SYN:	00000000
INT_TARG:	0000003a	INT_ADR:	00006000	INT_ADR_EXT:	00000000
PERF_MON:	00406ebf	PERF_CONT:	00000000	CAP_DIAG:	00000000
DIAG_CHKA:	10000000	DIAG_CHKB:	10000000	SCRATCH:	21011131
W0_BASE:	00100001	W0_MASK:	00000000	T0_BASE:	00001000
W1_BASE:	00800001	W1_MASK:	00700000	T1_BASE:	00008000
W2_BASE:	8000000	W2_MASK:	3ff00000	T2_BASE:	00000000
W3_BASE:	00000000	W3_MASK:	1ff00000	T3_BASE:	0000b800
W_DAC:	00000000	SG_TBIA:	00000000	HBASE:	00000000

IOD 1

WHOAMI:	0000003a	PCI_REV:	06000221
CAP_CTL:	02490fb1	HAE_MEM:	00000000	HAE_IO:	00000000
INT_CTL:	00000003	INT_REQ:	00000000	INT_MASK0:	00000000
INT_MASK1:	00000000	MC_ERR0:	e0000000	MC_ERR1:	000e88fd
CAP_ERR:	00000000	PCI_ERR:	00000000	MDPA_STAT:	00000000
MDPA_SYN:	00000000	MDPB_STAT:	00000000	MDPB_SYN:	00000000
INT_TARG:	0000003a	INT_ADR:	00006000	INT_ADR_EXT:	00000000
PERF_MON:	004e31a6	PERF_CONT:	00000000	CAP_DIAG:	00000000
DIAG_CHKA:	10000000	DIAG_CHKB:	10000000	SCRATCH:	00000000
W0_BASE:	00100001	W0_MASK:	00000000	T0_BASE:	00001000
W1_BASE:	00800001	W1_MASK:	00700000	T1_BASE:	00008000
W2_BASE:	80000001	W2_MASK:	3ff00000	T2_BASE:	00000000
W3_BASE:	00000000	W3_MASK:	1ff00000	T3_BASE:	0000a000
W_DAC:	00000000	SG_TBIA:	00000000	HBASE:	00000000


DECevent

DECevent produces bit-to-text ASCII reports derived from system event entries or user-supplied event logs.  The format of the reports is determined by commands, qualifiers, parameters, and keywords appended to the command.  The maximum command line length is 255 characters.

DECevent allows you to do the following:

•	Translate event log files into readable reports

•	Select alternate input and output files

•	Filter input events

•	Select alternative reports

•	Allow translation of events as they occur

•	Allow maintaining and customizing your environment with the interactive shell commands

Some DECevent commands are highlighted here.  To access on-line help:

OpenVMS

$ HELP DIAGNOSE  or

$ DIA /INTERACTIVE

DIA> HELP

Digital UNIX

> man dia   or

> dia hlp

Privileges Needed to Use DECevent

•	SYSPRV for the utility

•	DIAGNOSE to use the /CONTINUOUS qualifier

Translating Event Files

To produce a translated event report using the default event log file, SYS$ERRORLOG:ERRLOG.SYS, enter the command:

OpenVMS

              $ DIAGNOSE

Digital UNIX

              > dia -a

The DIAGNOSE command uses built-in defaults. This command produces a full report, directed to the terminal screen, from the input event file, SYS$ERRORLOG:ERRLOG.SYS.  The /TRANSLATE qualifier is understood on the command line.


Selecting Alternative Input and Output files
Select Alternative Input and Output Files

To select an alternate input file:

OpenVMS

              $ DIAGNOSE ERRORLOG.OLD

Digital UNIX

              > dia -a -f syserr-old.hostname

These commands select ERRORLOG.OLD as the event log to translate.  The file name can contain the directory or path specifications if needed.  The use of wildcard characters is also an option.

To send reports to an output file:

OpenVMS

              $ DIAGNOSE/OUTPUT=ERRLOG_OLD.TXT

Digital UNIX

              > dia -a > syserr-old.txt

These commands direct the output of DECevent to ERRLOG_OLD.TXT.

To reverse the order of the input events:

OpenVMS

              $ DIAGNOSE/TRANSLATE/REVERSE

Digital UNIX

              > dia -R

These commands reverse the order in which events are displayed.  The default order is chronological.


Filtering Events

/INCLUDE and /EXCLUDE qualifiers allow you to filter input event log files.

The /INCLUDE qualifier is used to create output for devices named in the command.

OpenVMS

              $ DIAGNOSE/TRANSLATE/INCLUDE=(DISK=RZ,DISK=RA92,CPU)

Digital UNIX

              > dia -i disk=rz disk=ra92 cpu

These commands create output using only the entries for RZ disks, RA92 disks, and

CPUs.

The /EXCLUDE qualifier is used to create output for all devices except those named in the command.

OpenVMS

              $ DIAGNOSE/TRANSLATE/EXCLUDE=(MEMORY)

Digital UNIX

              > dia -x mem

Use the /BEFORE and /SINCE qualifiers to select events before or after a certain time.

OpenVMS

              $ DIAGNOSE/TRANSLATE/BEFORE=15-JAN-1993:10:30:00

              or

              $ DIAGNOSE/TRANSLATE/SINCE=15-JAN-1993:10:30:00

Digital UNIX

              > dia -t s:15-jan-1993 e:20-jan-1993

If no time is specified, the default time is 00:00:00, and all events for that day are selected.

These selections can be combined to select a certain period of time as follows:

OpenVMS

              $ DIAGNOSE/TRANSLATE/SINCE=15-JAN-1993/BEFORE=20-JAN-1993

If no value is supplied with the /SINCE or /BEFORE qualifiers, DECevent defaults to TODAY.


Selecting Alternative Reports

The following table describes the different report formats available.  Report formats are mutually exclusive.  No combinations are allowed.  The default format is /Full.

Format	Description
/Full	Translates all available information for each event
/Brief	Translates key information for each event
/Terse	Provides binary event information and displays register values and other ASCII messages in a condensed format
/Summary	Produces a statistical summary of the events in the log
/Fsterr	Produces a one-line-per-entry report for disk and tape devices

The syntax is:

OpenVMS

$ DIAGNOSE/TRANSLATE/<format>

Digital UNIX

> dia -o <format>


System Drawer Description

The system drawer contains most of the basic components that make up a computer system.  The drawer, which can mount in either a cabinet or a pedestal, has four sections:

•	A system card cage section that holds up to two or four CPUs depending upon your system type, two to four memory pairs, one or two system bus to PCI bus bridges, and a power control module.

•	One or two PCI card cage sections depending upon your system type that contains eight to sixteen slots for I/O options.  Either five or thirteen of these slots are dedicated to PCI options.  The other three slots can be used for either PCI or EISA options.

•	A power supply section that holds up to three power supplies.  Three power supplies provide N+1 power for 4100 systems with three or four CPUs or for 4000 systems with two PCI card cages.  Two power supplies provide N+1 power for systems with one or two CPUs and a single PCI card cage.

•	A control panel section that holds a CD-ROM disk, a floppy, and an operator control panel.

The drawer measures 295mm x 444mm x 657mm (~12 x 17.5 x 26) and fully configured weighs approximately 45.5 kg (~100 lbs).

Click here [image] for a table showing the range of components by system type.

The figure shows components for an AlphaServer 4100.

AlphaServer 4100 drawer
AlphaServer 4000 drawer


System Drawer Figure
System Drawer for AlphaServer 4100


System Drawer for AlphaServer 4000


N+1 is the convention used to describe redundant power.  N is the required number of power supplies for a given configuration; the additional power supply provides redundancy.  Should one of the required power supplies fail, the backup power supply provides the necessary power for the system to continue operation.


Control Panel Assembly

System drawers and pedestal systems have different control panel assemblies.  The components are the same: a floppy, a CD-ROM, and an operator control panel.  The pedestal has an optional removable media SCSI drive.

On system drawers the entire control panel assembly is beneath the power supplies at the front of the system and is accessible when the front door is open.  On pedestal systems, the OCP and optional SCSI drive are accessible from the front when the plastic panel above the front door is tilted down; the other two components, the CD-ROM and floppy, are in the same location under the system drawer as they are in cabinet systems.

The location of the device controllers for the devices in the control panel assembly are:

•	The CD-ROM controller is embedded on PCI bus 1 (IOD 1).

•	The floppy controller is on the combo chip on the XBUS, off the EISA bus embedded on PCI bus 0 (IOD 0).

•	The On/Off button and Halt button are in the power circuit with the power supplies and cover interlocks.

•	The LCD display is controlled by the I2 C bus controller on the XBUS, off the EISA bus embedded on PCI bus 0 (IOD 0).

The table below describes each component and its function:

Component	Functional Description
CD-ROM drive	Used to load software, firmware, and updates.
Floppy drive	Used to load software, firmware, updates, and an image of the console if the fail-safe loader is loaded.
On button	Turns the system on.  When the LED in the button is lit, the system is running either console program or the operating system.
Halt button	Halts either OpenVMS or DIGITAL UNIX.  Depending upon the state of the machine at the time the button is pressed, it either hangs or starts the  SRM console.  If the system is hung and the machine state does not allow the halt signal to pass through the IOD, the CPU does not receive it and the system remains hung.  The Halt button does not affect the Windows NT operating system.  Assuming SRM console commands do not change the state of the machine and the system was not hung to begin with, a SRM console command continue issued to the console returns to the operating system it was running.  Note: After a continue command, to return to the console a second time the Halt button must be released (LED off) and depressed again.  A system crash can be forced by issuing the crash command to the SRM console.
Reset button	Initializes the system drawer.  If the Halt button is depressed (its LED lit) when the system is reset, the SRM console is loaded and remains in the system regardless of any other conditions.
Potentiometer	Accessed through a small hole located just above the Reset button, the potentiometer is used to control the light intensity of the LCD display.
OCP display	A 16-character LCD used to display power-up messages and system type.  See display messages  for further information.


Control Panel Assembly


Utilities

There are three major utilities needed for AlphaServers: ECU, RCU, and LFU.

•	ECU, the EISA Configuration Utility, is used to configure the EISA bus.

•	RCU, the RAID Configuration Utility, or RAID Standalone Configuration Utility, is used to configure RAID disk arrays.

•	LFU, the Loadable Firmware Update utility, is used to update other system and device firmware.

For further information on each utility, use the documentation that comes with each.  The material presented here is a brief overview of how to load and run utilities.

Running Utilities from a Graphics Monitor

Running Utilities from a Serial Terminal

Running ECU

Running RAID Standalone Configuration Utility

Starting LFU

Updating Firmware from CD-ROM

Updating Firmware from Floppy

Updating Firmware from the Network

Updating AlphaBIOS Firmware

LFU Commands

Creating Firmware Floppies


Running Utilities from a Graphics Monitor

Start AlphaBIOS and select Utilities from the menu.  The next selection depends on the utility to be run.  For example, to run ECU, select Run ECU from floppy.  To run RCU, select Run Maintenance Program.

Running a Utility from a Graphics Monitor


Running Utilities from a Serial Terminal

Utilities are run from a serial terminal in the same way as from a graphics monitor. The menus are the same, but some keys are different.

AlphaBIOS Option Key Mapping

AlphaBIOS Key	VTxxx Key
F1	Ctrl/A
F2	Ctrl/B
F3	Ctrl/C
F4	Ctrl/D
F5	Ctrl/E
F6	Ctrl/F
F7	Ctrl/P
F8	Ctrl/R
F9	Ctrl/T
F10	Ctrl/U
Insert	Ctrl/V
Delete	Ctrl/W
Backspace	Ctrl/H
Escape	Ctrl/[


ECU
Running ECU

The EISA Configuration Utility (ECU) is used to configure EISA options on AlphaServer systems.  The ECU can be run either from a graphics monitor or a serial terminal.

1.	Start AlphaBIOS Setup.  If the system is in the SRM console, issue the command alphabios. (If the system has a graphics monitor, you can set the SRM console environment variable to graphics.)

2.	From AlphaBIOS Setup, select Utilities, then from the submenu that displays select Run ECU and press Enter.

NOTE:	 The EISA Configuration Utility is supplied on diskettes shipped with the system.  There is a diskette for Microsoft Windows NT and a diskette for DIGITAL UNIX and OpenVMS.

3.	Insert the correct ECU diskette for the operating system and press Enter to run it.

The ECU main menu displays the following options:

EISA Configuration Utility
Steps in configuring your computer

STEP 1:  Important EISA configuration information
STEP 2:  Add or remove boards
STEP 3:  View or edit details
STEP 4:  Examine required details
STEP 5:  Save and exit

NOTE: Step 1 of the ECU provides online help.  It is recommended that you select this step and become familiar with the utility before proceeding.


Running the Standalone Configuration Utility
Running the RAID Standalone Configuration Utility

The RAID Standalone Configuration Utility is used to set up RAID disk drives and logical units.  The Standalone Utility is run from the AlphaBIOS Utility menu.

The AlphaServer 4100 system supports the KZPSC-xx PCI RAID controller (SWXCR).  The KZPSC-xx kit includes the controller, RAID Array 230 Subsystems software, and documentation.

1.	Start AlphaBIOS Setup.  If the system is in the SRM console, issue the command alphabios. (If the system has a graphics monitor, you can set the SRM console environment variable to graphics.)

2,	At the Utilities screen, select Run Maintenance Program.  Press Enter.

3.	In the Run Maintenance Program dialog box, type swxcrmgr in the Program Name: field.

4.	Press Enter to execute the program.  The Main menu displays the following options:

[01.View/Update Configuration]
 02.Automatic Configuration
 03.New Configuration
 04.Initialize Logical Drive
 05.Parity Check
 06.Rebuild
 07.Tools
 08.Select SWXCR
 09.Controller Setup
 10.Diagnostics

Refer to the RAID Array Subsystems documentation for information on using the Standalone Configuration Utility to set up RAID drives.


Starting LFU

Use the Loadable Firmware Update (LFU) utility to update system firmware.

You can start LFU from either the SRM console or the AlphaBIOS console.

• 	From the SRM console, start LFU by issuing the lfu command.

• 	From the AlphaBIOS console, select Update AlphaBIOS from the AlphaBIOS Setup screen.

A typical update procedure is:

1.	Start LFU.

2.	Use the LFU list command to show the revisions of modules that LFU can update and the revisions of update firmware.

3.	Use the LFU update command to write the new firmware.

4.	Use the LFU exit command to exit back to the console.


Starting LFU Example

Starting LFU from the SRM Console

P00>>> lfu

          ***** Loadable Firmware Update Utility *****

Select firmware load device (cda0, dva0, ewa0), or

Press <return> to bypass loading and proceed to LFU: cda0

.

.

.

UPD>

Starting LFU from the AlphaBIOS Console


Updating Firmware from the Internal CD-ROM

Insert the update CD-ROM, start LFU, and select cda0 as the load device.

1	Select the device from which firmware will be loaded. The choices are the internal CD-ROM, the internal floppy disk, or a network device. In this example, the internal CD-ROM is selected.
2	Select the file that has the firmware update, or press Enter to select the default file. The file options are:
	AS4X00FW (default)	SRM console, AlphaBIOS console, and I/O adapter firmware.
	AS4X00CP	SRM console and AlphaBIOS console firmware only.
	AS4X00IO	I/O adapter firmware only.
	In this example the file for console firmware (AlphaBIOS and SRM) is selected.
3	The LFU function table and prompt (UPD>) display.
4	Use the LFU list command to determine the revision of firmware in a device and the most recent revision of that firmware available in the selected file. In this example, the resident firmware for each console (SRM and AlphaBIOS) is at an earlier revision than the firmware in the update file.
5	The update command updates the device specified or all devices. In this example, the wildcard indicates that all devices supported by the selected update file will be updated.
6	For each device, you are asked to confirm that you want to update the firmware. The default is no. Once the update begins, do not abort the operation. Doing so will corrupt the firmware on the module.
7	The exit command returns you to the console from which you entered LFU (either SRM or AlphaBIOS).


Updating Firmware from CD-ROM

***** Loadable Firmware Update Utility *****

Select firmware load device (cda0, dva0, ewa0), or

Press <return> to bypass loading and proceed to LFU: cda0	1

Please enter the name of the options firmware files list, or

Press <return> to use the default filename [AS4X00FW]: AS4X00CP	2

Copying AS4X00CP from DKA500.5.0.1.1 .

Copying [as4x00]RHREADME from DKA500.5.0.1.1 .

Copying [as4x00]RHSRMROM from DKA500.5.0.1.1 ....................

Copying [as4x00]RHARCROM from DKA500.5.0.1.1 .............

-----------------------------------------------------------------

 Function    Description                                       	3

-----------------------------------------------------------------

 Display     Displays the system's configuration table.

 Exit        Done exit LFU (reset).

 List        Lists the device, revision, firmware name, and
             update revision.

 Lfu         Restarts LFU.

 Readme      Lists important release information.

 Update      Replaces current firmware with loadable data image.

 Verify      Compares loadable and hardware images.

 ? or Help   Scrolls this function table.

-----------------------------------------------------------------

UPD> list	4

Device         Current Revision    Filename       Update Revision

AlphaBIOS         V5.12-2          arcrom            V6.40-1

srmflash          V1.0-9           srmrom            V2.0-3

UPD> update *                                                  	5

WARNING: updates may take several minutes to complete for each device.

Confirm update on: AlphaBIOS       [Y/(N)] y                   	6

                          DO NOT ABORT!

AlphaBIOS     Updating to V6.40-1... Verifying V6.40-1... PASSED.

Confirm update on: srmflash        [Y/(N)] y

                          DO NOT ABORT!

srmflash        Updating to V2.0-3...  Verifying V2.0-3...  PASSED.

UPD> exit                                                        	7


Putting Update Firmware on Floppy
Creating Firmware Floppies

Create the update diskettes before starting LFU.

File Locations for Creating Update Diskettes on a PC

Console update diskette	I/O update diskette
AS4X00FW.TXT	AS4X00IO.TXT
AS4X00CP.TXT	RHREADME.SYS
RHREADME.SYS	CIPCA214.SYS
RHSRMROM.SYS	DFPAA246.SYS
RHARCROM.SYS	KZPAAA10.SYS

To update system firmware from floppy disk, you first must create the firmware update diskettes. You need to create two diskettes: one for console updates, and one for I/O.

1.	Download the update files from the Internet.

2	On a PC, copy files onto two FAT-formatted diskettes.

3	From an OpenVMS system, copy files onto two ODS2-formatted diskettes.


Creating an Update Floppy

Console update diskette

$ inquire ignore "Insert blank HD floppy in DVA0, then continue"
$ set verify
$ set proc/priv=all
$ init /density=hd/index=begin dva0: rhods2cp
$ mount dva0: rhods2cp
$ create /directory dva0:[as4x00]
$ copy as4x00fw.sys dva0:[as4x00]as4x00fw.sys
$ copy as4x00cp.sys dva0:[as4x00]as4x00cp.sys
$ copy rhreadme.sys dva0:[as4x00]rhreadme.sys
$ copy as4x00fw.txt dva0:[as4x00]as4x00fw.txt
$ copy as4x00cp.txt dva0:[as4x00]as4x00cp.txt
$ copy rhsrmrom.sys dva0:[as4x00]rhsrmrom.sys
$ copy rharcrom.sys dva0:[as4x00]rharcrom.sys
$ dismount dva0:
$ set noverify
$ exit

I/O update diskette

$ inquire ignore "Insert blank HD floppy in DVA0, then continue"
$ set verify
$ set proc/priv=all
$ init /density=hd/index=begin dva0: rhods2io
$ mount dva0: rhods2io
$ create /directory dva0:[as4x00]
$ create /directory dva0:[options]
$ copy as4x00fw.sys dva0:[as4x00]as4x00fw.sys
$ copy as4x00io.sys dva0:[as4x00]as4x00io.sys
$ copy rhreadme.sys dva0:[as4x00]rhreadme.sys
$ copy as4x00fw.txt dva0:[as4x00]as4x00fw.txt
$ copy as4x00io.txt dva0:[as4x00]as4x00io.txt
$ copy cipca214.sys dva0:[options]cipca214.sys
$ copy dfpaa246.sys dva0:[options]dfpaa246.sys
$ copy kzpsaA10.sys dva0:[options]kzpsaa10.sys
$ dismount dva0:
$ set noverify
$ exit


Internet Locations

Firmware for all AlphaServer systems is available to download from the Internet.  Access the firmware as follows:

•	Using a World Wide Web browser (such as AltaVista, Netscape, or Mosaic) follow links to AlphaServer 4100 systems, then to technical resources from URL:

http://www.digital.com/info/alphaserver/products.html

•	Using ftp, copy the file:

ftp://ftp.digital.com/pub/digital/alpha/firmware/

The files are structured as they are on firmware CDs and are separated by release.  For example, the contents of the V3.6 firmware CD are located at:

ftp://ftp.digital.com/pub/digital/alpha/firmware/v3.6

If firmware has been released since the last CD-ROM release, it is located at:

ftp://ftp.digital.com/pub/digital/alpha/firmware/interim/


Updating the Firmware from Floppy
Updating Firmware from Floppy

Insert an update diskette into the floppy drive. Start LFU and select dva0 as the load device.

1	Select the device from which firmware will be loaded. The choices are the internal CD-ROM, the internal floppy disk, or a network device. In this example, the internal floppy disk is selected.
2	Select the file that has the firmware update, or press Enter to select the default file. When the internal floppy disk is the load device, the file options are:
	AS4X00CP (default)	SRM console and AlphaBIOS console firmware only.
	AS4X00IO	I/O adapter firmware only.
	The default option shown when updating using CD-ROM (AS4X00FW) is not available, since the file is too large to fit on a 1.44 MB diskette. This means that when a floppy disk is the load device, you can update either console firmware or I/O adapter firmware, but not both in the same LFU session. If you need to update both, after finishing the first update, restart LFU with the lfu command and insert the floppy disk with the other file. In this example the file for I/O adapter firmware is selected.
3	Use the LFU list command to determine the revision of firmware in a device and the most recent revision of that firmware available in the selected file. In this example, the update revision for console firmware displays as Missing file because only the I/O firmware files are available on the floppy disk.
4	The update command updates the device specified or all devices.
5	For each device, you are asked to confirm that you want to update the firmware. The default is no. Once the update begins, do not abort the operation. Doing so will corrupt the firmware on the module.
6	The lfu command restarts the utility so that console firmware can be updated.
7	The default update file, AS4X00CP, is selected. The console firmware can now be updated, using the same procedure as for the I/O firmware.
8	The exit command returns you to the console from which you entered LFU (either SRM or AlphaBIOS).


Running Update from Floppy

          ***** Loadable Firmware Update Utility *****

Select firmware load device (cda0, dva0, ewa0), or

Press <return> to bypass loading and proceed to LFU: dva0             1

Please enter the name of the options firmware files list, or

Press <return> to use the default filename [AS4X00IO,(AS4X00CP)]: AS4X00IO    2

Copying AS4X00IO from DVA0 .

Copying RHREADME from DVA0 .

Copying CIPCA214 from DVA0 .

Copying DFPAA252 from DVA0 ...

Copying KZPSAA11 from DVA0 ...

.

.  (The function table displays, followed by the UPD> prompt.)

UPD> list                                                              3

Device         Current Revision    Filename       Update Revision

AlphaBIOS         V5.12-3          arcrom         Missing file

pfi0               2.46            dfpaa_fw           2.52

srmflash          T3.2-21          srmrom         Missing file

                                   cipca_fw        A214

                                   kzpsa_fw         A11

UPD> update pfi0                                                       4

WARNING: updates may take several minutes to complete for each device.

Confirm update on: pfi0            [Y/(N)] y                           5

                          DO NOT ABORT!

pfi0            Updating to 2.52... Verifying to 2.52... PASSED.

UPD> lfu                                                               6

          ***** Loadable Firmware Update Utility *****

Select firmware load device (cda0, dva0, ewa0), or

Press <return> to bypass loading and proceed to LFU: dva0

Please enter the name of the options firmware files list, or

Press <return> to use the default filename [AS4X00IO,(AS4X00CP)]:      7

.

. (The function table displays, followed by the UPD> prompt.
.  Console firmware can now be updated.)

UPD> exit                                                           8


Updating Firmware from a Network Device

Copy files to the local MOP servers MOP load area, start LFU, and select ewa0 as the load device.

Before starting LFU, download the update files from the Internet.  You will need the files with the extension .SYS. Copy these files to your local MOP servers MOP load area. Start LFU and select ewa0 as the load device.

1	Select the device from which firmware will be loaded. The choices are the internal CD-ROM, the internal floppy disk, or a network device. In this example, a network device is selected.
2	Select the file that has the firmware update, or press Enter to select the default file. The file options are:
	AS4X00FW (default)	SRM console, AlphaBIOS console, and I/O adapter firmware.
	AS4X00CP	SRM console and AlphaBIOS console firmware only.
	AS4X00IO	I/O adapter firmware only.
	In this example the default file, which has both console firmware (AlphaBIOS and SRM) and I/O adapter firmware, is selected.
3	Use the LFU list command to determine the revision of firmware in a device and the most recent revision of that firmware available in the selected file. In this example, the resident firmware for each console (SRM and AlphaBIOS) and I/O adapter is at an earlier revision than the firmware in the update file.
4	The update command updates the device specified or all devices. In this example, the wildcard indicates that all devices supported by the selected update file will be updated. Typically LFU requests confirmation before updating each consoles or devices firmware. The -all qualifier removes the update confirmation requests.
5	The exit command returns you to the console from which you entered LFU (either SRM or AlphaBIOS).


Updating from a Network Device Example
Updating from a Network Device

***** Loadable Firmware Update Utility *****

Select firmware load device (cda0, dva0, ewa0), or

Press <return> to bypass loading and proceed to LFU: ewa0          1

Please enter the name of the options firmware files list, or

Press <return> to use the default filename [AS4X00FW]:             2

Copying AS4X00FW from EWA0 .

Copying RHREADME from EWA0 .

Copying RHSRMROM from EWA0 ...........................

Copying RHARCROM from EWA0 ............

Copying CIPCA214 from EWA0 .

Copying DFPAA246 from EWA0 ...

Copying KZPSAA11 from EWA0 ...

.. (The function table displays, followed by the UPD> prompt)

UPD> list                                                          3

Device         Current Revision    Filename       Update Revision

AlphaBIOS         V5.12-2          arcrom            V6.40-1

kzpsa0           A10               kzpsa_fw         A11

kzpsa1           A10               kzpsa_fw         A11

srmflash          V1.0-9           srmrom            V2.0-3

                                   cipca_fw        A214

                                   dfpaa_fw           2.46

UPD> update * -all                                                 4

WARNING: updates may take several minutes to complete for each device.

                          DO NOT ABORT!

AlphaBIOS    Updating to V6.40-1... Verifying V6.40-1...  PASSED.

                          DO NOT ABORT!

kzpsa0        Updating to  A11    ...  Verifying A11...  PASSED.

                          DO NOT ABORT!

kzpsa1        Updating to  A11    ...  Verifying A11...  PASSED.

                          DO NOT ABORT!

srmflash      Updating to V2.0-3...  Verifying V2.0-3...  PASSED.

UPD> exit                                                          5


LFU Commands

Command	Function
display	Shows the system physical configuration.
exit	Terminates the LFU program.
help	Displays the LFU command list.
lfu	Restarts the LFU program.
list	Displays the inventory of update firmware on the selected device.
readme	Lists release notes for the LFU program.
update	Writes new firmware to the module.
verify	Reads the firmware from the module into memory and compares it with the update firmware.


display

The display command shows the system physical configuration. Display is equivalent to issuing the SRM console command show configuration. Because it shows the slot for each module, display can help you identify the location of a device.


exit

The exit command terminates the LFU program, causes system initialization and testing, and returns the system to the console from which LFU was called.


help

The help (or ?) command displays the LFU command list, shown below.

---------------------------------------------------------------------

 Function    Description

---------------------------------------------------------------------

 Display     Displays the system's configuration table.

 Exit        Done exit LFU (reset).

 List        Lists the device, revision, firmware name, and update
             revision.

 Lfu         Restarts LFU.

 Readme      Lists important release information.

 Update      Replaces current firmware with loadable data image.

 Verify      Compares loadable and hardware images.

 ? or Help   Scrolls this function table.

---------------------------------------------------------------------


lfu

The lfu command restarts the LFU program. This command is used when the update files are on a floppy disk. The files for updating both console firmware and I/O firmware are too large to fit on a 1.44 MB disk, so only one type of firmware can be updated at a time. Restarting LFU enables you to specify another update file.


list

The list command displays the inventory of update firmware on the CD-ROM, network, or floppy. Only the devices listed at your terminal are supported for firmware updates.

The list command shows three pieces of information for each device:

•	Current Revision  The revision of the devices current firmware

•	Filename  The name of the file used to update that firmware

•	Update revision  The revision of the firmware update image


readme

The readme command lists release notes for the LFU program.


update

The update command writes new firmware to the module.  Then LFU automatically verifies the update by reading the new firmware image from the module into memory and comparing it with the source image.

To update more than one device, you may use a wildcard but not a list. For example, update k* updates all devices with names beginning with k, and update * updates all devices. When you do not specify a device name, LFU tries to update all devices; it lists the selected devices to update and prompts before devices are updated. (The default is no.) The -all qualifier removes the update confirmation requests, enabling the update to proceed without operator intervention.

CAUTION:  Never abort an update operation. Aborting corrupts the firmware on the module.


verify

The verify command reads the firmware from the module into memory and compares it with the update firmware. If a module already verified successfully when you updated it, but later failed tests, you can use verify to tell whether the firmware has become corrupted.


Updating Firmware from AlphaBIOS
Updating AlphaBIOS Firmware

As new versions of Windows NT are released, it might be necessary to upgrade AlphaBIOS to the latest version. Additionally, as improvements are made to AlphaBIOS, it might be desirable to upgrade to take advantage of new AlphaBIOS features.

Use this procedure to upgrade from an earlier version of AlphaBIOS:

1.	Insert the diskette or CD-ROM containing the AlphaBIOS upgrade.

2.	If you are not already running AlphaBIOS Setup, start it by restarting your system and pressing F2 when the Boot screen is displayed.

3.	In the main AlphaBIOS Setup screen, select Upgrade AlphaBIOS and press Enter.

4.	The system is reset and the Loadable Firmware Update (LFU) utility is started.

5.	When the upgrade is complete, issue the LFU exit command. The system is reset and you are returned to AlphaBIOS.

If you press the Reset button instead of issuing the LFU exit command, the system is reset and you are returned to LFU.


SRM Console Commands and Environment Variables
SRM Console Commands

Here is a summary of the SRM console commands.  The test command is described in troubleshooting using diagnostics.  For complete reference information on the other SRM commands, see the AlphaServer 4100 System Drawer Users Guide or the Alpha Server 4000 System Drawer Users Guide.

Command	Function
alphabios	Loads and starts the AlphaBIOS console.
boot	Loads and starts the operating system.
clear envar	Resets an environment variable to its default value.
continue	Resumes program execution.
crash	Forces a crash dump at the operating system level.
deposit	Writes data to the specified address.
edit	Invokes the console line editor on a RAM file or on the nvram file (power-up script).
examine	Displays the contents of a memory location, register, or device.
halt	Halts the specified processor. (Same as stop.)
help	Displays information about the specified console command.
info num	Displays various types of information about the system: Info displays the information provided by each info qualifying num. Info 3 reads the impure area that contains the state of the CPU before it entered PAL mode. Info 5 reads the PAL built logout area that contains the data used by the operating system to create the error entry Info 8 reads the IOD registers.
initialize	Resets the system.
lfu	Runs the Loadable Firmware Update Utility.
man	Displays information about the specified console command.
more	Displays a file one screen at a time.
prcache	Initializes and displays status of the PCI NVRAM.
set envar	Sets or modifies the value of an environment variable.
set host	Connects to a MSCP DUP server on a DSSI device.
set rcm_dialout	Sets a modem dialout string.
show envar	Displays the state of the specified environment variable.
show config	Displays the configuration at the last system initialization.
show cpu	Displays the state of each processor in the system.
show device	Displays a list of controllers and their devices in the system.
show fru	Same as show config with the addition of serial numbers and part numbers of system bus options.
show memory	Displays memory module information.
show network	Displays the state of network devices in the system.
show pal	Displays the version of the privileged architecture library code (PALcode).
show power	Displays information about the power supplies, system fans, CPU fans, and temperature.
show rcm_dialout	Displays the modem dialout string.
show version	Displays the version of the console program.
start	Starts a program that was previously loaded on the processor specified
stop	Halts the specified processor. (Same as halt.)
test	Runs firmware diagnostics for the system.


Environment Variables

Environment variables pass configuration information between the console and the operating system.  Their settings determine how the system powers up, boots the operating system, and operates.  Environment variables are set or changed with the set envar command and returned to their default values with the clear envar command.  Their values are viewed with the show envar command.  Environment variables are specific to the SRM console. For complete reference information on the other SRM commands, see the AlphaServer 4000 System Drawer Users Guide or the AlphaServer 4100 System Drawer Users Guide.

Environment Variable	Function
auto_action	Specifies the consoles action at power-up, a failure, or a reset.
bootdef_dev	Specifies the default boot device string.
boot_osflags	Specifies the default operating system boot flags.
com2_baud	Changes the default baud rate of the COM2 serial port.
console	Specifies the device on which power-up output is displayed (serial terminal or graphics monitor).
cpu_enabled	Enables or disables a specific secondary CPU.
ew*0_mode	Specifies the connection type of the default Ethernet controller.
ew*0_protocols	Specifies network protocols for booting over the Ethernet controller.
kbd_hardware_ type	Specifies the default console keyboard type.
kzpsa*_host_id	Specifies the default value for the KZPSA host SCSI bus node ID.
language	Specifies the console keyboard layout.
memory_test	Specifies the extent to which memory will be tested. For Digital UNIX systems only.
ocp_text	Overrides the default OCP display text with specified text.
os_type	Specifies the operating system and sets the appropriate console interface.
pci_parity	Disables or enables parity checking on the PCI bus.
pk*0_fast	Enables fast SCSI mode.
pk*0_host_id	Specifies the default value for a controller host bus node ID.
pk*0_soft_term	Enables or disables SCSI terminators on systems that use the QLogic ISP1020 SCSI controller.
sys_model_num	Displays the system model number and is used by the operating system.  Must be restored after a PCI motherboard is replaced.
sys_serial_num	Restores the system serial number.  Must be set if the system motherboard is replaced.
sys_type	Displays the system type and computes certain information passed to the operating system.  Must be restored after a PCI motherboard is replaced.
tga_sync_green	Specifies the location of the SYNC signal generated by the Digital ZLXp-E PCI graphics accelerator option.
tt_allow_login	Enables or disables login to the SRM console firmware on other console ports.


Environment Variable Record Sheet

Environment Variable	System Name	System Name	System Name
auto_action
bootdef_dev
boot_osflags
com2_baud
console
cpu_enabled
ew*0_mode
ew*0_protocols
kbd_hardware_ type
kzpsa*_host_id
language
memory_test
ocp_text
os_type
pci_parity
pk*0_fast
pk*0_host_id
pk*0_soft_term
pk*0_soft_term
sys_model_num
sys_serial_num
sys_type
tga_sync_green
tt_allow_login


System Addressing

Command/address lines are 40 bits in length on the system bus making it possible to access 1 terabyte locations.  This address space is divided into two equal parts by address bit <39>, the most significant bit in the address.  When this bit is clear, memory is addressed; when the bit is set, I/O space is addressed.  In AlphaServer systems most of the I/O space is reserved however, the top 64 Gbytes is used to address nodes on the system bus.  The 64 Gbyte space is divided into 8 sections, each 8 Gbytes in size and each responded to by a node on the system bus (one section is reserved).  Each node responds to commands addressed to it.  (Each IOD monitors the system bus for errors.)

Memory I/O space is used to communicate with the memory ASIC.

CPU I/O space targets CPUs and is used for interrupts, acknowledges, halts, and DTAG enable and disable.  Click here [image] to see how these addresses are decoded.

IOD I/O space is used to communicate with PCIs.

On the system bus side of the IOD,PCI space is divided into six (6) fixed sections: sparse memory space, dense memory space, sparse I/O space, sparse configuration space, PCI bridge CSR space, and interrupt acknowledge space.  Each section is uniquely addressed and is mapped to address space on the PCI side of the bridge.

For a complete discussion of addressing see the Rawhide System Programmers Manual.


Sparse memory space, though not sparse in terms of its size, 4 Gbytes, on the system bus side of the bridge, allows byte, word, and longword access across the bridge.  Notice that the size of the space, 4 Gbytes, on the system bus side, maps to 128 Mbytes on the PCI side of the bridge.  The reason for this is that addresses on the system bus are longword or quadword aligned and are shifted 5-bits to the left to encode length information (byte, word, longword).  (2 to the fifth times 128 Mbytes = 4 Gbytes).


Dense memory space is 2 Gbytes in size on the system bus side of the bridge, and unlike sparse memory space allows only longword and quadword access.  It maps to dense memory space on the PCI side of the bridge.


Sparse I/O space is accessed only through sparse address space.


Sparse configuration space is used to configure, control, and provide status information for devices on the PCI.  Since it is sparse space, byte, word, or longword access is permissible.


PCI bridge CSR space contains the control and status registers associated with the system bus to PCI bus bridge.


The interrupt/acknowledge space contains the interrupt registers for the devices on the PCI.


System Address Space


An ASIC is an Application Specific Integrated Circuit.


CPU and IOD Error Registers

The following error registers are used to hold error information:

External Interface Status Register

External Interface Address Register

MC Error Information Register 0

MC Error Information Register 1

CAP Error Register

PCI Error Status Register


EI_STAT register
EI_STAT - External Interface Status Register

Address	FF FFF0 0168

Type	R

Click on the field mnemonic for the functional description.

The EI_STAT register is a read-only register that is unlocked and cleared by any PALcode read.  A read of this register also unlocks the EI_ADDR, BC_TAG_ADDR, and FILL_SYN registers subject to some restrictions.  The EI_STAT register is not unlocked or cleared by reset.

Fill data from B-cache or main memory could have correctable or uncorrectable errors in ECC mode.  In parity mode, fill data parity errors are treated as uncorrectable hard errors.  System address/command parity errors are always treated as uncorrectable hard errors irrespective of the mode.  The sequence for reading, unlocking, and clearing EI_STAT, EI_ADDR, BC_TAG_ADDR, and FILL_SYN is as follows:

1.	Read the EI_ADDR, BC_TAG_ADDR, and FIL_SYN registers in any order.  Does not unlock or clear any register.

2.	Read the EI_STAT register.  This operation unlocks the EI_ADDR, BC_TAG_ADDR, and FILL_SYN registers.  It also unlock the EI_STAT register subject to conditions given in the following table, which defines the loading and locking rules for external interface registers.

See the table below for loading and locking rules for external interface registers.

NOTE:  If the first error is correctable, the registers are loaded but not locked.  On the second correctable error, the registers are neither loaded nor locked.

Registers are locked on the first uncorrectable error except the second hard error bit.  This bit is set only for an uncorrectable error that follows an uncorrectable error.  A correctable error that follows an uncorrectable error is not logged as a second error.  B-cache tag parity errors are uncorrectable in this context.

Loading and Locking Rules for External Interface Registers

Correct-able Error	Uncor- rectable Error	Second Hard Error	Load Regr	Lock Reg	Action when EI_STAT Is Read
0	0	Not possible	No	No	Clears and unlocks all registers
1	0	Not possible	Yes	No	Clears and unlocks all registers
0	1	0	Yes	Yes	Clears and unlocks all registers
11	1	0	Yes	Yes	Clear bit (c) does not unlock.  Transition to 0,1,0 state.
0	1	1	No	Already locked	Clears and unlocks all registers
11	1	1	No	Already locked	Clear bit (c) does not unlock.  Transition to 0,1,1 state.
1 These are special cases.  It is possible that when EI_ADDR is read, only the correctable error bit is set and the registers are not locked.  By the time EI_STAT is read, an uncorrectable error is detected and the registers are loaded again and locked.  The value of EI_ADDR read earlier is no longer valid.  Therefore, for the 1,1,x case, when EI_STAT is read correctable, the error bit is cleared and the registers are not unlocked or cleared.  Software must reexecute the IPR read sequence.  On the second read operation, error bits are in 0,1,x state, all the related IPRs are unlocked, and EI_STAT is cleared.


EI_STAT<27:24>

CHIP_ID<3:0>                  R

Chip Identification

Read as 4.  Future update revisions to the chip will return new unique values.


EI_STAT<28>

BC_TPERR                       R

B-Cache Tag Address Parity Error

Indicates that a B-cache read transaction encountered bad parity in the tag address RAM.


EI_STAT<29>

BC_TC_PERR                       R

B-Cache Tag Control Parity Error

Indicates that a B-cache read transaction encountered bad parity in the tag control RAM.


EI_STAT<30>

 EI_ES                      R

External Interface Error Source

When set,  indicates that the error source is fill data from main memory or a system address/command parity error.  When clear, the error source is fill data from the B-cache.

This bit is only meaningful when <COR_ECC_ERR>, <UNC_ECC_ERR>, or <EI_PAR_ERR> is set in this register.

This bit is not defined for a B-cache tag error (BC_TPERR) or a B-cache tag control parity error (BC_TC_ERR).


EI_STAT<31>

 COR_ECC_ERR                      R

Correctable ECC Error

Indicates that fill data received from outside the CPU contained a correctable ECC error.


EI_STAT<32>

UNC_ECC_ERR                      R

Uncorrectable ECC Error

Indicates that fill data received from outside the CPU contained an uncorrectable ECC error.  In parity mode, this bit indicates data parity error.


EI_STAT<33>

EI_PAR_ERR           R

External Interface Command/Address Parity Error

Indicates that an address and command received by the CPU has a parity error.


EI_STAT<34>

FIL_IRD                  R

Fill I-Ref D-Ref

When set, indicates that the error occurred during an I-ref fill.  When clear, indicates that the error occurred during a D-ref fill. This bit has meaning only when one of the ECC or parity error bits is set.

This bit is not defined for a B-cache tag parity error (BC_TPERR) or a B-cache tag control parity error (BC_TC_ERR).


EI_STAT<35>

SEO_HRD_ERR                 R

Second External Interface Hard Error

Indicates that a fill from B-cache or main memory, or a system address/command received by the CPU has a hard error while one of the hard error bits in the EI_STST register is already set.


EI_ADDR - External Interface Address Register

Address	FF FFF0 0148

Type	R

The EI_ADDR register contains the physical address associated with errors reported by the EI_STAT register.  It is unlocked by a read of the EI_STAT register.

This register is meaningful only when one of the error bits is set.


MC Error Information Register 0 (MC_ERR0 - Offset = 800)

The low order MC bus address bits are latched into this register when the MC-PCI bridge detects an error event. If the event is a hard error, the register bits are locked. A write to clear symptom bits in the CAP_ERR register unlocks this register. When the valid bit (MC_ERR_VALID) in the CAP_ERR register is clear, the contents are undefined.

Name	Bits	Type	Description
reserved	<3:0>	RO
ADDR <31:4>	<31:4>	RO	Contains the address of the current transaction on the MC bus when an error is detected.


MC Error Information Register 0 Figure
MC Error Information Register 0


MC Error Information Register 1 (MC_ERR1 - Offset = 840)

The high order MC bus address bits and error symptoms are latched into this register when the MC-PCI bridge detects an error event. If the event is a hard error, the register bits are locked. A write to clear symptom bits in the CAP_ERR register unlocks this register. When the valid bit (MC_ERR_VALID) in the CAP_ERR register is clear, the contents are undefined.

Name	Bits	Type	Description
ADDR <39:32>	<7:0>	RO	Address bits <39:32> of the transaction on the MC bus when an error is detected.
MC_CMD <5:0>	<13:8>	RO	Active command at the time the error was detected
Reserved	<19:17>	RO	Reads as 111
DEVICE_ID	<16:14>	RO	MC slot number of bus master at the time of the error.
Dirty	<20>	RO	Set if the MC bus error was associated with a Read/Dirty transaction. When set, the device ID field <19:14> does not indicate the source of the data.
Reserved	<30:21>	RO
VALID	<31>	RO	Logical OR of bits <30:23> in the CAP_ERR register. Set if MC_ERR0 & MC_ERR1 contain a valid address.


MC Information Register 1
MC Error Information Register 1


CAP Error Register (CAP_ERR - Offset = 880)

CAP_ERR is used to log information pertaining to an error detected by the CAP or MDP ASIC. If the error is a hard error the register is locked. All bits, except the LOST_MC_ERR bit, are locked on hard errors. CAP_ERR will remain locked until the CAP_ERR is written to clear each individual error bit.

Name	Bits	Type	Description
PERR	<0>	RW1C	PCI master state machine observed PERR#.
SERR	<1>	RW1C	PCI target state machine observed SERR#. CAP asserts SERR when it is master and detects target abort.
MAB	<2>	RW1C	PCI master state machine detected PCI Target Abort (likely cause: NXM) (except Special Cycle). On reads fill error is also returned.
PTE_INV	<3>	RW1C	Invalid page table entry on scatter/gather access.
PCI_ERR_VALID	<4>	RO	Logical OR of bits <3:0> of this register. When set, the PCI error address register is locked.
Reserved	<22:5>	RO
PIO_OVFL	<23>	RW1C	Set when a transaction that targets this MC-PCI bus bridge is not serviced because the buffers are full. This is a symptom of setting the PEND_NUM field in CAP_CNTL to an incorrect value.
LOST_MC_ERR	<24>	RW1C	Set when an error is detected but not logged because the associated symptom fields and registers are locked with the state of an earlier error.
MC_ADR_PERR	<25>	RW1C	Set when an MC bus command/address parity error is detected.
NXM	<26>	RW1C	MC bus master transaction status NXM (Read with Address bit <39> set but transaction not pended or transaction target above the top of memory register). CPU will also get fill error on reads.
CRDA	<27>	RW1C	Correctable ECC error detected by MDPA. Clear state in MDPA_STAT before clearing this bit.
CRDB	<28>	RW1C	Correctable ECC error detected by MDPB. Clear state in MDPB_STAT before clearing this bit.
RDSA	<29>	RW1C	Uncorrectable ECC error detected by MDPA. Clear state in MDPA before clearing this bit.
RDSB	<30>	RW1C	Uncorrectable ECC error detected by MDPB. Clear state in MDPB before clearing this bit.
MC_ERR VALID	<31>	RO	Logical OR of bits <30:23> in this register. When set, MC_ERR0 and MC_ERR1 are latched.


CAP Error Register Figure


PCI Error Status Register 1 (PCI_ERR1 - Offset = 1040
PCI Error Status Register 1 (PCI_ERR1 - Offset = 1040)

The PCI_ERR1 register is used by the MC-PCI bridge to log bus address <31:0> pertaining to an error condition logged in CAP_ERR. This register always captures PCI address <31:0>, even for a PCI DAC cycle. When the PCI_ERR_VALID bit in CAP_ERR is clear, the contents are undefined.

Name	Bits	Type	Description
ADDR<31:0>	<31: 0>	R0	Contains address bits <31:0> of the current transaction on the PCI bus when an error is detected.


PCI Error Status Register Figure


MDPA Status Register (MDPA_STAT - Offset = 4000
MDPA Status Register (MDPA_STAT - Offset = 4000)

Contains status information related to the error stored in the CAP_ERR register.

Name	Field	Type	Description
MDPA_REV	3:0	RO	Chip revision level
Reserved	29:4	RO	Reserved
CRD	30	R/W1C	MDPA_SYN contains syndrome of a CRD. Write one clears both bits <31:30>.
RDS	31	R/W1C	MDPA_SYN contains syndrome of a RDS. Write one clears both <31:30>.


 MDPA Error Syndrome Register (MDPA_SYN - Offset = 4040)

The MDPA_SYN register is used by the MC-PCI bridge to log information pertaining to an error in the low 64 bits on the MC bus detected by the ECC checkers. The syndrome is latched into the MDPA_SYN register upon an MC-PCI Bridge error. A write to clear MDPA_STAT<31 or 30> unlocks this register.

Name	Bits	Type	Description
Cycle 0 ECC_SYNDROME	<7:0>	RO	ECC  syndrome bits
Cycle 1 ECC_SYNDROME	<15:8>	RO	ECC  syndrome bits
Cycle 2 ECC_SYNDROME	<23:16>	RO	ECC syndrome bits
Cycle 3 ECC_SYNDROME	<31:24>	RO	ECC  syndrome bits


MDPB Status Register (MDPB_STAT - Offset = 8000)

Contains status information related to the error stored in the CAP_ERR register.

Name	Bits	Type	Initial State	Description
MDPB_REV	3:0	RO	REV	Chip revision level
reserved	29:4	RO	0
CRD	30	R/W1C	0	MDPB_SYN contains syndrome of a CRD. Write one clears both bits <31:30>
RDS	31	R/W1C	0	MDPB_SYN contains syndrome of a RDS. Write one clears both <31:30>


 MDPB Error Syndrome Register (MDPB_SYN - Offset = 8040)

The MDPB_SYN register is used by the MC-PCI bridge to log information pertaining to an error in the high 64 bits on the MC bus detected by the ECC checkers. The syndrome is latched into the MDPB_SYN register upon an MC-PCI bridge error. A write to clear MDPB_STAT<31 or 30> unlocks this register.

Name	Bits	Type	Description
Cycle 0 ECC_SYNDROME	<7:0>	RO	ECC syndrome bits
Cycle 1 ECC_SYNDROME	<15:8>	RO	ECC syndrome bits
Cycle 2 ECC_SYNDROME	<23:16>	RO	ECC syndrome bits
Cycle 3 ECC_SYNDROME	<31:24>	RO	ECC syndrome bits


Systems with one or two CPUs require one power supply: redundant power is provided by two.


The Memory Connect bus, or the MC bus for short, is the technical name for the system bus.  It is not to be confused with the MC or Memory Channel option.


CPU Types
CPU Types (B3001, B3002, or B3004)

AlphaServer 4000 and 4100 systems can be configured with one of several CPU variants.  Variants are differentiated by CPU speeds, the technology used EV5 or EV56, and the presence or absence of a backup synchronous data cache external to the Alpha microprocessor chip.  AlphaServer 4000 support only CPUs made using EV56 technology.

The Alpha chip is made using state-of-the-art technology, has a transistor count of 9.3 million, consumes 50 watts of power, and is air cooled (a fan is placed on the chip).  The default cache system is write-back and when the module has an external cache, it too is write-back.

Alpha Chip Composition:
CPU Variants:
Configuration Rules:
LEDs:
Color Codes:


CPU Module Layout and Placement


Unit	Description
Instruction	8 Kbyte cache, 4 way issue
Execution	4 way execution: 2 integer units, 1 floating-point adder, and 1 floating-point multiplier
Memory	Merge logic, 8-Kbyte write-through first-level data cache, 96-Kbyte write-back 3-way set assciative second level data cache, bus interface unit


Module Variant	Clock Frequency	External Cache	Technology Used
B3001-CA	300 MHz	none	EV5
B3002-AB	300 MHz	2 Mbytes	EV5
B3004-AA	400 MHz	4 Mbytes	EV56
B3004-BA	300 MHz	2 Mbyte	EV56
B3004-DA	466 MHz	4 Mbytes	EV56


1	The first CPU must be in slot CPU 0 since the system bus receives its clock from the CPU in slot 0.

2	All CPUs must have the same Alpha chip clock speed.  The system bus will hang without an error message if the ocillators clocking the CPUs are different.

3	Mixing of cached and uncached CPUs is not permitted.

4	Mixing modules that have processor chip made using different technologies is permitted as long as clock speeds are the same.  If EV5 and EV56 modules are mixed, the EV5 module must be placed in CPU slot 0.  Note, however, that the AlphaServer 4000 supports only processors using EV56 technology.


LEDs on the CPU module can be seen from the back of the system drawer.  The LEDs are clustered together near the middle of the module.  Modules made with EV5 processor chips have three LEDs; modules made with EV56 processor chips have four.

LED Location	Name	Description
Top	DC-OK	Lit if DC power is OK.  Driven by the PCM module.
Middle	SROM Clock	Lit when the SROM clock is functioning.  Normally off.
Bottom	Self-Test	Lit when the CPU self-test passes.
Bottom (EV56)	Regulator OK	On board regulator functioning.


The top edge of CPU modules is color coded for easy identification.  The color code designations are as follows:

Color	Option Number	Description
Dark Blue	B3001-CA	EV5, 300 MHz, uncached
Green	B3002-AB	EV5, 300 MHz, 2MB cached
Green	B3004-BA	EV56, 300 MHz, 2MB cached
Red	B3004-CA	EV56, 466 MHz, 4 MB cached
Orange	B3004-AA	EV56, 400 MHz, 4MB cached


FRU List

This table lists or points to all the electrical FRUs in the system.

Part Number	Description	Removal & Replacement
B3001,B3002, B3004	CPU Types	CPU
12-24701-34		CPU Fan
B3020, B3030	Memory Types	Memory
B3040-AA, B3040-AB	System Bus to PCI Bus Bridge	System Bus to PCI Bus Bridge Module System Bus to PCI Bus Bridge Module
54-24117-01	Power Control Module	Power Control Module
54-23803-01,  54-23803-02, 54-23805-01	System Bus	System Bus Motherboard (4100) System Bus Motherboard (4000)
B3050, B3051	PCI I/O Subsystem	PCI/EISA Bus Motherboard PCI Bus Motherboard
54-24674-01	Server Control Module	Server Control Module
	Power System
30-44712-01		Power Supply
17-04217-01, 17-04385-01		Power Harness (4100 and early 4000) Power Harness (4000)
12-23609-21		System Fan
70-32016-01, 70-33002-01	Power Circuit and Cover Interlock	Cover Interlocks (4100 and early 4000) Cover Interlocks (4000)
30-45353-01 30-45353-02	AC input box for H9A10-EB (N.A. & A.P.) AC input box for H9A10-EC (Europe & A.P.)
12-45334-02	AC power strip, 3 per HA10-EB or -EC cabinet
H7600-AA H7600-DB	Power controller for H9A10-EL cabinet (N.A. & Japan) Power controller for H9A10-EM cabinet (Europe, A.P.)
12-23501-01
	Control Panel Assembly
54-24364-01 54-24366-01 30-43049-01	OCP logic module OCP switch module OCP display	Operator Control Panel (Cabinet) Operator Control Panel (Pedestal)
RX28L-AB		Floppy
RRD4x-AB		CD-ROM
	Cabinet System Fan Tray	Cabinet Fan Tray
30-46788-01 17-04324-01	Internal power supply Internal power harness	Fan Tray Power Supply
12-23609-21		Fan Tray Fan
54-24691-01		Fan Tray Fan Fail-Detect Module

Power and Signal Cables

	Power and Signal Cables (4100 and early 4000) (cabinet)
	Power and Signal Cables (4000) (cabinet)
	Power and Signal Cables (4100 and early 4000) (pedestal)
	Power and Signal Cables (4000) (pedestal)


P00>>> test pci*
Console is in diagnostic mode
System test, runtime 120 seconds
Type ^C to stop testing

Configuring all PCI buses..
polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1   SCSI Bus ID 7
dka500.5.0.1.1     DKa500                   RRD45  1645
polling ncr1 (NCR 53C810) slot 3, bus 0 PCI, hose 1   SCSI Bus ID 7
dkb200.2.0.3.1     DKb200                   RZ29B  0007
dkb400.4.0.3.1     DKb400                   RZ29B  0007
polling tulip0 (DECchip 21040-AA) slot 2, bus 0 PCI, hose 1
ewa0.0.0.2.1: 08-00-2B-E5-B4-1A
polling floppy0 (FLOPPY) PCEB - XBUS hose 0
dva0.0.0.1000.0    DVA0                      RX23
Testing all PCI buses..
Testing EWA0 network device
Testing VGA (alphanumeric mode only)
Testing SCSI disks (read-only)
Testing floppy (dva0, read-only)
 ID       Program      Device       Pass  Hard/Soft Bytes Written  Bytes Read
-------- ------------ ------------ ------ --------- ------------- ------------
00002c29     exer_kid dkb200.2.0.3     27    0    0             0     14642176
00002c2a     exer_kid dkb400.4.0.3     27    0    0             0     14642176
00002c5e     exer_kid dva0.0.0.100      0    0    0             0            0
 ID       Program      Device       Pass  Hard/Soft Bytes Written  Bytes Read
-------- ------------ ------------ ------ --------- ------------- ------------
00002c29     exer_kid dkb200.2.0.3     92    0    0             0     48689152
00002c2a     exer_kid dkb400.4.0.3     92    0    0             0     48689152
00002c5e     exer_kid dva0.0.0.100      0    0    0             0       286720
Testing aborted. Shutting down tests.
Please wait..
Testing complete
^C
P00>>>


P00>>> test memory

Console is in diagnostic mode

System test, runtime 120 seconds

Type ^C to stop testing

Starting background memory test, affinity to all CPUs..

Starting memory thrasher on each CPU..

Starting memory thrasher on each CPU..

Starting memory thrasher on each CPU..

Starting memory thrasher on each CPU..

 ID       Program      Device       Pass  Hard/Soft Bytes Written  Bytes Read

-------- ------------ ------------ ------ --------- ------------- ------------

000046d7      memtest memory            1    0    0      48234496     48234496

000046e0      memtest memory          122    0    0     126862208    126862208

000046e9      memtest memory          111    0    0     115329280    115329280

000046f2      memtest memory          109    0    0     113232384    113232384

000046fb      memtest memory           41    0    0      41937920     41937920

 ID       Program      Device       Pass  Hard/Soft Bytes Written  Bytes Read

-------- ------------ ------------ ------ --------- ------------- ------------

000046d7      memtest memory            1    0    0     226492416    226492416

000046e0      memtest memory          566    0    0     592373120    592373120

000046e9      memtest memory          555    0    0     580840192    580840192

000046f2      memtest memory          554    0    0     579791744    579791744

000046fb      memtest memory          211    0    0     220174080    220174080

 ID       Program      Device       Pass  Hard/Soft Bytes Written  Bytes Read

-------- ------------ ------------ ------ --------- ------------- ------------

.

.

.

000046d7      memtest memory            1    0    0     937426944    937426944

000046e0      memtest memory         2346    0    0    2458610560   2458610560

000046e9      memtest memory         2337    0    0    2449174528   2449174528

000046f2      memtest memory         2333    0    0    2444980736   2444980736

000046fb      memtest memory          890    0    0     932070272    932070272

Memory test complete

Test time has expired...

P00>>>


P00>>> show config

Digital Equipment Corporation

                    AlphaServer 4000

Console V3.0-10 OpenVMS PALcode V1.19-2, DIGITAL UNIX PALcode V1.21-14

Module                          Type     Rev    Name

System Motherboard              0        0000   mthrbrd0

Memory  128 MB SYNC             0        0000   mem0

CPU (2MB Cache)                 1        0000   cpu0

Bridge (IOD0/IOD1)              600      0021   iod0/iod1

PCI Motherboard                 8        0002   saddle0

Bridge (IOD2/IOD3)              600      0021   iod2/iod3

PCI Motherboard                 8        0000   saddle1

Bus 0 iod0 (PCI0)

Slot   Option Name              Type     Rev    Name

1      PCEB                     4828086  0005   pceb0

2      S3 Trio64/Trio32         88115333 0000   vga0

Bus 1 pceb0 (EISA Bridge connected to iod0, slot1)

Slot   Option Name              Type     Rev    Name

Bus 0 iod1 (PCI1)

Slot   Option Name              Type     Rev    Name

1      NCR 53C810               11000    0002   ncr0

Bus 0 iod2 (PCI2)

Slot   Option Name              Type     Rev    Name

2      PCI-PCI Bridge           11011    0002   pcb0

Bus 2  pcb0 (PCI-PCI Bridge connected to iod2, slot 2)

Slot   Option Name              Type     Rev    Name

0      ISP1020                  10201077 0002   isp0

Bus 0  iod3 (PCI3)

Slot   Option Name              Type     Rev    Name

P00>>>


P00>>> show cpu

Primary CPU:      00

Active CPUs:      00    01

Configured CPUs:  00    01

SROM Revision:    V2.0  V2.0

P00>>>


   P00>>> show memory

Slot    Type       MB     Base

----    ----      ----    --------

 0       EDO       256    0

 1       EDO       128    10000000

Total              384

P00>>>


P00>>> show device

polling ncr0 (NCR 53C810) slot 1, bus 0 PCI, hose 1   SCSI Bus ID 7

dka500.5.0.1.1     DKa500                   RRD45  1645

polling ncr1 (NCR 53C810) slot 3, bus 0 PCI, hose 1   SCSI Bus ID 7

dkb100.1.0.3.1     DKb100                   RZ29B  0007

dkb200.2.0.3.1     DKb200                   RZ29B  0007

dkb400.4.0.3.1     DKb400                   RZ29B  0007

polling floppy0 (FLOPPY) PCEB - XBUS hose 0

dva0.0.0.1000.0    DVA0                      RX23

polling tulip0 (DECchip 21040-AA) slot 2, bus 0 PCI, hose 1

ewa0.0.0.2.1: 08-00-2B-E5-B4-1A

P00>>>


The set command sets or modifies the value of an environment variable. It can also be used to create a new environment variable if the name used is unique. Environment variables are used to pass configuration information between the console and the operating system. The setting of these variables determines how the system powers up, boots the operating system, and operates. The syntax is:

set [-default] envar value

-default	Restores an environment variable to its default setting.
envar	The name of the environment variable to be modified.
value	The new value of the environment variable.

Whenever you modify the value of any of the following environment variables, the new value takes effect only after you reset the system by pressing the Reset button or issuing the initialize command:

console
kbd_hardware_type
language
ocp_text
os_type


The show envar command displays the current value (or setting) of an environment variable. The syntax is:

show envar

envar	The name of the environment variable to be displayed. The wildcard * displays all environment variables.


The set sys_serial_num console command causes the SRM console to write the system serial number supplied with the command to the EEPM on the system motherboard.


FRU Removal and Replacement

Caution:  Wear an antistatic wrist strap whenever you work on a system.  Cabinet systems have two wrist straps connected to the frame at the front and rear of.  Pedestal systems do not have an attached strap so you will have to bring one to the site.

This section contains information on removal and replacement of the following:

Drawer Exposure

System Drawer Exposure (Cabinets)

System Drawer Exposure (Pedestal)

System Card Cage Section

CPU

CPU Fan

Memory

Power Control Module

System Bus to PCI Bus Bridge Module (AA)

System Bus to PCI Bus Bridge Module (AB)

System Bus Motherboard (4100 and early 4000)

System Bus Motherboard (4000)

PCI Card Cage Section

PCI/EISA Bus Motherboard

PCI Bus Motherboard

Server Control Module

PCI/EISA Option

Power Section

Power Supply

Power Harness (4100 and early 4000)

Power Harness (4000)

System Fan

Cover Interlocks (4100 and early 4000)

Cover Interlocks (4000)

Control Panel Assembly

Operator Control Panel (Cabinet)

Operator Control Panel (Pedestal)

Floppy

CD-ROM

StorageWork Shelves

StorageWorks Shelf

Cabinet Fan Tray

Cabinet Fan Tray

Fan Tray Power Supply

Fan Tray Fan

Fan Tray Fan Fail Detect Module

Signal and Power Cables

Power and Signal Cables (4100 and early 4000)(cabinet)

Power and Signal Cables (4000)(cabinet)

Power and Signal Cables (4100 and early 4000)(pedestal)

Power and Signal Cables $4000)(pedestal)


CPU Removal and Replacement
CPU (B3001-xx, B3002-xx, B3004-xx) Removal and Replacement

Warning:  CPU modules have parts that operate at high temperatures.  Wait 2 minutes after power is removed before handling this module.

Caution: Several different CPU modules work in these systems.  Unless you are upgrading, be sure you are replacing the broken module with the same variant.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage. Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Identify and  remove the faulty CPU.  A label to the left of the system card cage identifies which slot contains CPUx.  The CPU is held in place with levers at both ends; simultaneously raise the levers and lift the CPU from the cage.

Replacement

1	Reverse the above procedure.

2	Bring the system up to the SRM console by pressing the Halt button if necessary.

Verification

1	Power up the system and issue the show cpu  command at the console prompt to verify that the CPU you replaced is seen.


CPU Replacement


CPU Fan Removal and Replacement
CPU Fan (12-24701-34) Removal and Replacement

The CPU fan sits on the heatsink on the Alpha chip.

Removal

1	Follow the CPU removal and replacement procedure.

2	Unplug the fan from the module.

3	Remove the four Phillips head screws holding the fan to the Alpha chip.

Replacement

1	Reverse the above procedure.

Verification

If the system powers up, the CPU fan is working.


CPU Fan Replacement


System Drawer Exposure (Cabinets)

There are two major cabinet variants each with power variations for different parts of the world:

Cabinets Without Drawer Trays

The H9A10-EB for North America and Japan
The H9A10-EC for Europe and Asia Pacific

Cabinets With Drawer Trays

The H9A10-EL for North America and Japan
The H9A10-EM for Europe and Asia Pacific

Exposing the system drawer is different for the two major cabinet variants.  Click on the appropriate hot spot for instructions.

System Drawer Exposure (Cabinets Without Drawer Trays)

System Drawer Exposure (Cabinets With Drawer Trays)


System Drawer Exposure
System Drawer Exposure (H1A10-EB &-EC Cabinet)

In a cabinet, system drawers are stacked above one another.  If you need to look at PCM LEDs, do so before you proceed. See power control module LEDs.

To expose the system bus or PCI bus card cages

1	Open the front and rear doors of the cabinet.

2	At the front of the cabinet, unplug the power supplies.

3	At the rear, remove the two Phillips screws holding the shipping bracket on the right rail so that the drawer can be pulled out.

4	Using a flathead screwdriver, disengage the lock mechanism at the lower left hand corner of the drawer.

5	Pull the drawer out part way and release the lock mechanism by removing the screwdriver.  (If you wish to remove the whole drawer for some reason, leave the screwdriver in place.)

6	Once the lock mechanism has been released, continue to pull the drawer from the cabinet until it locks.

7	Remove the system bus card cage cover.  Unscrew the two Phillips head screws holding the cover in place and slide it off the drawer.

8	Remove the PCI bus card cage cover.  Unscrew the three Phillips head screws holding the cover to the left side of the drawer and slide it off the drawer.

To expose the power system or system fans

1	Open the front and rear doors of the cabinet.

2	At the rear of the cabinet, remove any cables from PCI options that may interfere with pulling the drawer forward.

3	At the front, remove the shipping brackets on the right and left rails that hold the drawer in place.

4	Pull out the drawer until it locks.

5	Remove the power section cover.  Unscrew the two Phillips head retaining screws and slide the cover off the drawer.


System Drawer
System Drawer Exposure (H9A10-EB &-EC Cabinet)


System Drawer Exposure (H9A10-EL, & EM Common Cabinet)
System Drawer Exposure (H9A10-EL & -EM Cabinet)

Caution:  The cabinet could tip over if a system drawer is pulled out and the stabilizing bar is not fully extended with its leveler foot on the floor.

Exposing any section of the system drawer in an H9A10-EL or -EM cabinet

1	Open the front door of the cabinet.

2	Pull out the stabilizer bar at the bottom of the cabinet until it stops.

3	Unplug the drawer's power supplies.

4	Remove the Phillips screws holding the shipping bracket to the rails so that the drawer can be pulled out.

5	Pull the drawer all the way out until it locks.

6	To access the system bus card cage cover, unscrew the two Phillips head screws holding the cover in place and slide it off.

7	To access the PCI/EISA bus card cage, unscrew the three Phillips head screws holding the cover to the right side of the drawer and slide it off.

8	To access the PCI bus card cage, unscrew the three Phillips head screws holding the cover to the left side of the drawer and slide it off.

9	To access the power or fan section, unscrew the two Phillips head screws holding the cover in place and slide it off.


System Drawer Exposure (H9A10-EL & -EM Cabinet)


System Drawer Exposure (Pedestal)

In a pedestal system, the system drawer is at the top of the system.

To expose the entire drawer

1	Open the front door and remove it by lifting and pulling it away from the system.

2	Remove the top cover.  Unscrew the two Phillips head retaining screws midway up on each side of the pedestal, tilt the cover up and lift it away from the frame.

3	Remove the system bus card cage cover at the back of the pedestal if you need to.  To remove the cover, unscrew the two Phillips head retaining screws and slide the cover off the drawer.

4	Remove the PCI bus card cage cover at the back of the pedestal if you need to.  To remove the cover, unscrew the three Phillips head screws holding the cover to the side of the drawer and slide the cover off the drawer.

5	Remove the pedestal tray if you need to.  To remove the tray: Remove the tray cover by loosening the retaining screws at the back of the tray. Disconnect the cables from the OCP and any optional SCSI device from the bulkhead connector in the rear right corner of the tray.  Unscrew the Phillips head retaining screw holding the bulkhead to the tray.  Finally, unscrew the two Phillips head retaining screws and slide the tray off the drawer.


Pedestal Drawer Exposure
System Drawer Exposure (Pedestal)


Memory Module Removal and Replacement
Memory Module (B3020 or B3030) Removal and Replacement

Warning:  Memory modules have parts that operate at high temperatures.  Wait 2 minutes after power is removed before handling this module

Caution:  Several different memory modules work in these systems. Be sure you are replacing the broken module with the same variant.  See memory configuration rules for more information.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage.  Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Identify and remove the faulty module.  A label to the left of the system card cage identifies which slot contains the high or low halves of memory banks.  The memory module is held in place by a flathead captive screw attached to the top brace of the module.   Unscrew the screw and lift the module from the cage.

Replacement

1	Reverse the above procedure.

Verification

1	Bring the system up to the SRM console by pressing the Halt button if necessary.

2	Power up the system and issue the show memory  command at the console prompt to verify that the memory you replaced is seen.

3	Issue the test memory command to verify memory.


Memory Module Replacement


Power Control Module Removal and Replacement
Power Control Module (54-24117-01) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage. Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Remove the faulty PCM.  The PCM is located in the back left corner of the system bus card cage.  A captive flathead screw and the rear card guide hold the PCM in place.  Remove the screw and lift the module from the cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system.  If the PCM is faulty or not seated properly, the system will not come up.


Power Control Module Replacement


System Bus to PCI Bus Bridge Module (B3040-AA) Removal and Replacement
System Bus to PCI Bus Bridge (B3040-AA) Module Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage. Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Expose the PCI bus card cage on the left of the drawer when viewing it from the rear. Remove the three Phillips head screws holding the cover in place and slide it off the drawer.

5	Remove all the PCI/EISA options.  If necessary, see PCI/EISA option removal.

6	Remove the server control module.  If necessary, see server control removal.

7	Remove the PCI motherboard.  If necessary, see PCI motherboard removal.

8	Remove the two Phillips head screws holding the system bus to PCI bus bridge module to the sheet metal between the system bus card cage and the PCI bus card cage.

9	Remove enough CPU and memory modules to the right of the system bus to PCI bus bridge module to allow a flathead screwdriver to be inserted in the slot in the middle of the top bracket of the bridge module.  If necessary, see CPU removal and memory removal.

10	Place a flathead screwdriver into the slot in the middle of the top bracket of the bridge and into the corresponding slot in the sheet metal between the two card cages.  Use the screwdriver as a lever to disconnect the bridge module from the connector on the system bus motherboard.

11	Remove the bridge module from the system bus card cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the show configuration  command at the console prompt to verify that all system options are seen.


System Bus to PCI Bus Bridge Replacement
System Bus to PCI Bus Bridge Module Replacement


System Bus to PCI Bus Bridge Module (B3040-AB) Removal and Replacement
System Bus to PCI Bus Bridge (B3040-AB) Module Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage. Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Expose the PCI bus card cage on the right of the drawer when viewing it from the rear. Remove the three Phillips head screws holding the cover in place and slide it off the drawer.

5	Remove all the PCI/EISA options.  If necessary, see PCI/EISA option removal.

6	Remove the PCI motherboard.  If necessary, see PCI motherboard removal.

7	Remove the two Phillips head screws holding the system bus to PCI bus bridge module to the sheet metal between the system bus card cage and the PCI bus card cage.

8	Remove enough CPU and memory modules to the left of the system bus to PCI bus bridge module to allow a flathead screwdriver to be inserted in the slot in the middle of the top bracket of the bridge module.  If necessary, see CPU removal and memory removal.

9	Place a flathead screwdriver into the slot in the middle of the top bracket of the bridge and into the corresponding slot in the sheet metal between the two card cages.  Use the screwdriver as a lever to disconnect the bridge module from the connector on the system bus motherboard.

10	Remove the bridge module from the system bus card cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the show configuration  command at the console prompt to verify that all system options are seen.


System Bus to PCI Bus Bridge Replacement
System Bus to PCI Bus Bridge Module Replacement


System Bus Motherboard Removal and Replacement
System Motherboard (54-23803-01(4100), 54-23803-02(early 4000)) Removal and Replacement

The system motherboard contains an NVRAM that holds the system serial number (or more appropriately the system drawer serial number).  On early shipments this number, written in several languages, is found on a large barcode label located on the right side of the drawer at the power supply end.  On later shipments the label is at the back of the system drawer below the system card cage.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage by removing the two Phillips head screws holding it in place and sliding the cover off the drawer.

4	Remove all CPUs, memory modules, and the PCM from the system bus motherboard.

5	Expose the PCI bus card cage. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

6	Remove all the PCI/EISA options.  If necessary, see PCI/EISA option removal.

7	Remove the server control module.  If necessary, see server control removal.

8	Remove the PCI motherboard.  If necessary, see PCI motherboard removal.

9	Remove the system bus to PCI bus bridge module from the system bus motherboard.  If necessary, see system bus to PCI bus bridge module removal.

10	Remove the bracket holding the power cables in place as they pass from the system bus section to the power section of the drawer.

11	Disconnect all cables to the system motherboard and lay them back over the power supply section of the system drawer.

Caution:  Do not let the power cables flop around in the card cage.  The pins in the CPU connectors are fragile and can easily be damaged by the power cables.

12	Remove both the front and back module card guides.  Unscrew the two screws that hold the guides in place.

13	Remove the system motherboard from the card cage by removing the 15 Phillips head screws holding it in place.

Replacement

1	Reverse the above procedure.  To align the motherboard in the cage, start replacing the screws in the corners next to the system bus to PCI bus bridge module and then the PCM module.  Remaining screws should align properly.

2	Bring the system up to the SRM console by pressing the Halt button if necessary.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the show configuration command at the console prompt to verify that all system options are seen.

2	Restore the system serial number by issuing the set sys_serial_num command at the SRM console prompt.  See discussion above for its location.


System Bus Motherboard Replacement
System Bus Motherboard (4100 and early 4000) Replacement


System Bus Motherboard Removal and Replacement
System Motherboard (54-23805-01 (4000)) Removal and Replacement

The system motherboard contains an NVRAM that holds the system serial number (or more appropriately the system drawer serial number).  On early shipments this number, written in several languages, is found on a large barcode label located on the right side of the drawer at the power supply end.  On later shipments the label is at the back of the system drawer below the system card cage.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the system bus card cage by removing the two Phillips head screws holding it in place and sliding the cover off the drawer.

4	Remove all CPUs, memory modules, and the PCM from the system bus motherboard.

5	Expose both PCI bus card cages. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

6	Remove all the PCI/EISA options.  If necessary, see PCI/EISA option removal.

7	Remove the server control module.  If necessary, see server control removal.

8	Remove both PCI motherboard.  If necessary, see PCI motherboard removal.

9	Remove both system bus to PCI bus bridge module from the system bus motherboard.  If necessary, see system bus to PCI bus bridge module removal.

10	Remove the bracket holding the power cables in place as they pass from the system bus section to the power section of the drawer.

11	Disconnect all cables to the system motherboard and lay them back over the power supply section of the system drawer.

Caution:  Do not let the power cables flop around in the card cage.  The pins in the CPU connectors are fragile and can easily be damaged by the power cables.

12	Remove both the front and back module card guides.  Unscrew the two screws that hold the guides in place.

13	Remove the system motherboard from the card cage by removing the Phillips head screws holding it in place.

Replacement

1	Reverse the above procedure.  To align the motherboard in the cage, start replacing the screws in the corners next to the system bus to PCI bus bridge module and then the PCM module.  Remaining screws should align properly.

2	Bring the system up to the SRM console by pressing the Halt button if necessary.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the show configuration command at the console prompt to verify that all system options are seen.

2	Restore the system serial number by issuing the set sys_serial_num command at the SRM console prompt.  See discussion above for its location.


System Bus Motherboard Replacement
System Bus Motherboard (4000) Replacement


PCI/EISA Motherboard (B3050) Removal and Replacement

Removal

1	The PCI motherboard has an NVRAM on the XBUS that contains local customized environment variables.  If the console runs, execute a  show * command at the console prompt and record their values.  Otherwise:

2	Shut down the operating system and power down the system.

3	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

4	Expose the PCI bus card cage. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

5	Remove all PCI and EISA options.  If necessary, see PCI/EISA option removal.

6	Disconnect all cables connected to the PCI/EISA motherboard.

7	Remove the server control module.  Be very careful removing this module; careless removal can damage pins on the PCI/EISA motherboard.  If necessary, see server control module removal.

8	Unscrew the two screws holding the system bus to PCI bus bridge module in the system bus card cage to the PCI motherboard.

9	Remove the nine Phillips head screws that hold the PCI motherboard in place.  To reach the screws on the bottom of the board, thread your screwdriver through the three holes in the sheet metal.

10	Carefully pry the motherboard loose from the bridge module on the other side of the sheet metal separating the system bus card cage from the PCI card cage.

Caution:  There are two ASICs located in the lower right corner of the module mounted on delicate pins.  It is easy to damage these pins during removal and installation.  Be careful not to hit the pins against the standoffs that hold the SCM module in place.

11	Remove the PCI motherboard from the card cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the  show configuration or show device command at the console prompt to verify that all options are seen.

2	Issue the test pci command to test the PCI.

3	Once you have verified that the system recognizes all its options, issue any  set <envar> commands necessary to restore the local customized environment.


PCI Motherboard Replacement


PCI/EISA Motherboard (B3051) Removal and Replacement
PCI Motherboard (B3051) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the PCI bus card cage on the right when viewing the drawer from the rear. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

4	Remove all PCI options.  If necessary, see PCI/EISA option removal.

5	Disconnect all cables connected to the PCI motherboard.

6	Unscrew the two screws holding the system bus to PCI bus bridge module in the system bus card cage to the PCI motherboard.

7	Remove the nine Phillips head screws that hold the PCI motherboard in place.  To reach the screws on the bottom of the board, thread your screwdriver through the three holes in the sheet metal.

8	Carefully pry the motherboard loose from the bridge module on the other side of the sheet metal separating the system bus card cage from the PCI card cage.

9	Remove the PCI motherboard from the card cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the show configuration or show device command at the console prompt to verify that all options are seen.

2	Issue the test pci command to test the PCI.


PCI Motherboard Replacement


Server Control Module Removal and Replacement
Server Control Module (54-24674-01) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the PCI bus card cage. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

4	Disconnect the cables connected at the bulkhead to the server control module.

5	If necessary, remove several PCI and EISA options from the bottom of the PCI card cage up until you have space enough to access the server control module.  If necessary, see PCI/EISA option removal.

6	Disconnect the two cables connected to the PCI motherboard at the server control module end.

7	Disconnect the twisted pair power cable from the module.

8	Place a credit card or a piece of cardboard between the edge of the SCM module and the B3050 module to portect the delicate pins of the ASICs located in the lower right corner of the B3050 module.

9	Using a flat head screwdirver gently pry the server control module off the snaps that hold it in place and remove it.  Make sure you do not hit the pins of the ASICs on the B3050 module during removal.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the  show configuration command at the console prompt to verify that all options are seen.


Server Control Replacement
Server Control Module Replacement


PCI/EISA Option Removal and Replacement

Warning:  To prevent fire, use only modules with current limited outputs.  See National Electrical Code NFPA 70 or Safety of Information Technology Equipment, Including Electrical Business Equipment EN 60 950.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the PCI bus card cage. Remove three Phillips head screws holding the cover in place and slide it off the drawer.

4	Remove the faulty option.  Diagnosis should have identified the faulty option and the slot in which it sits ( [image]).  Disconnect cables connected to the option.  Unscrew the small Phillips head screw securing the option to the card cage.  Slide the option from the card cage.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console) and issue the  show configuration or show dev command at the console prompt to verify that the option you replaced is seen.  Run any diagnostic appropriate for the option you replaced.


PCI Option Replacement
PCI/EISA Option Replacement


Power Supply Removal and Replacement
Power Supply (30-44712-01) Removal and Replacement

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the power section of the drawer by removing its cover.  Remove the two Phillips head screws holding the cover in place and slide it off the drawer.

4	Release the power supply tray by removing the two Phillips head screws on the side of the drawer.

5	Lift the power supply tray to release it from the sheet metal and slide it out from the drawer until it locks (about 4 inches).

6	Tilt the tray to allow easier access to the back of the power supplies.

7	Unplug the connectors at the rear of the supply to be replaced.

8	Unscrew the four Phillips head screws at the front of the tray that hold the front of the power supply and the two Phillips head screws on the bottom rear of the power supply that hold the supply in place.

9	Remove the power supply.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system.  If the system has redundant power, the system will power up regardless of whether the replaced power supply is faulty.  In this case look at the PCM LEDs to determine that the power supply is functioning properly.  If the system does not have redundant power and the power supply just replaced is good, the system should power up.


Power Supply Replacement


System Fan Removal and Replacement
System Fan (12-23609-21) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the power and system bus card cage sections of the drawer by removing the two covers.  Unscrew the two Phillips head screws holding each cover in place and slide the covers off the drawer.

4	If you want more space to work on the fans, do this step and the next, otherwise skip to step 7.  Release the power supply tray by removing the two Phillips head screws on the side of the drawer.

5	Lift the power supply tray to release it from the sheet metal and slide it out from the drawer until it locks.

6	Tilt the tray to allow easier access to the fans.

7	Remove the bracket holding the power harness as it passes from the power section to the system bus card cage section of the drawer.  Remove the three Phillips head screws holding the bracket in place.

8	Disconnect the power harness from the system bus motherboard and fold the harness back over the power supplies.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

9	Release the three lever latches on the bracket holding the fans in place.

10	Disconnect the power cable of thebroken fan from the power harness and lift the fan from the drawer.

Replacement

1	Reverse the above procedure.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

Verification

1	Power up the system.  If the fan you installed is faulty, the system will not power up.  Look at the PCM LEDs to determine that the fan you replaced is functioning properly.


Fan Replacement
System Fan Replacement


Power Harness Removal and Replacement
Power Harness (17-04217-01 (4100 and early 4000)) Removal and Replacement

This harness is used in the 4100 and early shipments of the 4000.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the power system, the system bus card cage, and the PCI card cage sections of the drawer by removing all three covers.  Unscrew the Phillips head screws holding each cover in place and slide them off the drawer.

4	Release the power supply tray by removing the two Phillips head screws on the side of the drawer.

5	Lift the power supply tray to release it from the sheet metal and slide it out from the drawer.

6	Tilt the tray to allow easier access to the fans.

7	Remove the bracket holding the power harness as it passes from the power section to the system bus card cage section of the drawer.  Remove the three Phillips head screws holding the bracket in place.

8	Disconnect the power harness from the system bus motherboard and fold the harness back over the power supplies.  Remove any modules that prevent you from disconnecting the harness from the system bus motherboard.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

9	Disconnect the two power connectors from the PCI motherboard and pass them through the hole from the PCI card cage to the power section of the drawer.

10	Disconnect the fan power cables from the power harness.

11	Remove the four Phillips head screws holding the OCP tray to the system drawer.

12	Slide the tray out of the system drawer far enough to disconnect power cables attached to the OCP, the floppy, and the CD-ROM drive.

13	Remove the tray from the system.

14	Push the power cables through the hole from the tray into the power section of the drawer.

15	Disconnect the power harness from the power supplies.

16	Remove the harness from the system.

Replacement

1	Reverse the above procedure.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

Verification

1	Power up the system.  If the power harness you installed is faulty, the system will not power up.


Power Harness Replacement
Power Harness (4100 and early 4000) Replacement (connectors are hotspots)


Power Harness Removal and Replacement
Power Harness (17-04358-01 (4000)) Removal and Replacement

This harness is used in later shipments of the 4000.

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Expose the power system, the system bus card cage, and the PCI card cage sections of the drawer by removing all four covers.  Unscrew the Phillips head screws holding each cover in place and slide them off the drawer.

4	Release the power supply tray by removing the two Phillips head screws on the side of the drawer.

5	Lift the power supply tray to release it from the sheet metal and slide it out from the drawer.

6	Tilt the tray to allow easier access to the fans.

7	Remove the bracket holding the power harness as it passes from the power section to the system bus card cage section of the drawer.  Remove the three Phillips head screws holding the bracket in place.

8	Disconnect the power harness from the system bus motherboard and fold the harness back over the power supplies.  Remove any modules that prevent you from disconnecting the harness from the system bus motherboard.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

9	Disconnect the two power connectors from the PCI/EISA motherboard and pass them through the hole from the PCI/EISA card cage to the power section of the drawer.

10	Disconnect the three power connectors from the PCI (IOD2 and 3) motherboard and pass them through the hole from the PCI card cage to the power section of the drawer.

11	Disconnect the fan power cables from the power harness.

12	Remove the four Phillips head screws holding the OCP tray to the system drawer.

13	Slide the tray out of the system drawer far enough to disconnect power cables attached to the OCP, the floppy, and the CD-ROM drive.

14	Remove the tray from the system.

15	Push the power cables through the hole from the tray into the power section of the drawer.

16	Disconnect the power harness from the power supplies.

17	Remove the harness from the system.

Replacement

1	Reverse the above procedure.

Caution:  Do not let the power harness connectors flop around in the system bus card cage; they can easily damage the pins in the CPU connectors.

Verification

1	Power up the system.  If the power harness you installed is faulty, the system will not power up.


Power Harness Replacement
Power Harness (4000) Replacement (connectors are hotspots)


Cover Interlock Removal and Replacement
Cover Interlock (70-32016-01 (4100 and early 4000)) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Remove all three section covers exposing the interlock switch assembly.

4	Remove the two screws holding the interlock in place.

5	To remove the interlock, push it toward the opposite side of the system drawer (be sure not to twist it) and tilt it so that the switches affected by the power and system card cage covers clear the openings in the side of the drawer.  Slide it toward the front of the drawer and remove letting it hang loosely over the side of the drawer.

6	If you are working on a pedestal system, disconnect the switch connection from the tray bulkhead and remove the interlock switch assembly.

7	If you are working on a system drawer, unscrew the four screws holding the OCP tray assembly in place beneath the drawer in front.

8	Slide the tray out and remove from the system.  See floppy removal, if needed.

7	Pull the interlock switch connection to the OCP back through the access hole and remove the entire shitch assembly.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system.  If the switch you installed is faulty, the system will not power up.


Cover Interlock Replacement
Cover Interlock (4100 and ealry 4000) Replacement


Cover Interlock Removal and Replacement
Cover Interlock (70-33002-01 (4000)) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Remove all three section covers exposing the interlock switch assembly.

4	Remove the two screws holding the interlock in place.

5	To remove the interlock, push it toward the opposite side of the system drawer (be sure not to twist it) and tilt it so that the switches affected by the power and system card cage covers clear the openings in the side of the drawer.  Slide it toward the front of the drawer and remove letting it hang loosely over the side of the drawer.

6	If you are working on a pedestal system, disconnect the switch connection from the tray bulkhead and remove the interlock switch assembly.

7	If you are working on a system drawer, unscrew the four screws holding the OCP tray assembly in place beneath the drawer in front.

8	Slide the tray out and remove from the system.  See floppy removal, if needed.

7	Pull the interlock switch connection to the OCP back through the access hole and remove the entire shitch assembly.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system.  If the switch you installed is faulty, the system will not power up.


Cover Interlock Replacement
Cover Interlock (4000) Replacement


Operator Control Panel Removal and Replacement (Pedestal)
Operator Control Panel Assembly Removal and Replacement (Pedestal)

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	While you need not remove the tray containing the OCP, you do need to slide it forward to access the OCP retaining screws under the tray.  The tray is attached to the power section cover.  To slide the tray forward: Remove the tray cover by loosening the retaining screws at the back of the tray and sliding it toward the back of the system.  Disconnect the cables from the OCP, and any optional SCSI device in the tray from the bulkhead at the rear right of the tray.  Unscrew the Phillips head retaining screw holding the bulkhead to the tray.  Finally, unscrew the two Phillips head retaining screws at the front of the system drawer and slide the tray forward.

4	Remove the white power interconnect wire and the signal ribbon cable from the OCP.

5	Remove the two Phillips head screws holding the OCP in place and remove it from the tray.

6	Once the assembly is removed remove whatever part you need to replace.

•	OCP logic module	54-24364-01

•	OCP switch module	54-24366-01

•	OCP display	30-43049-01

Replacement

1	Reverse the above procedure.

2	Adjust the potentiometer located just above the reset button with a small Phillips head screwdriver so that the LCD has the desired intensity.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console).  If the OCP you installed is faulty, the system will not power up or you will not see messages on the OCP display.


Operator Control Panel Replacement (Pedestal)


Operator Control Panel Removal and Replacement (Rackmount)
Operator Control Panel Assembly Removal and Replacement (Cabinet)

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Remove the four Phillips head screws holding the OCP tray to the system drawer.

4	Slide the tray out of the system drawer far enough to disconnect cables attached to the OCP, the floppy, and the CD-ROM drive.

5	Remove the tray from the system.

6	Move the tray to some handy work surface;  holding the tray vertically, remove the two Phillips head screws holding the OCP in place from the bottom and remove the OCP assembly.

7	Once the assembly is removed remove whatever part you need to replace.

•	OCP logic module	54-24364-01

•	OCP switch module	54-24366-01

•	OCP display	30-43049-01

Replacement

1	Reverse the above procedure.  As you replace the tray in the drawer, be sure that the slides on the sides of the tray are placed on the rails in the drawer.

2	Adjust the potentiometer located just above the reset button with a small Phillips head screwdriver so that the LCD has the desired intensity.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console).  If the OCP you installed is faulty, the system will not power up or you will not see messages on the OCP display.


Operator Control Panel Replacement (Rackmount)
Operator Control Panel Replacement (cabinet)


Floppy Removal and Replacement
Floppy (RX23L-AB) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Remove the four Phillips head screws holding the OCP tray to the system drawer.

4	Slide the tray out of the system drawer and disconnect cables attached to the OCP (unnecessary on a pedestal system), the floppy, and the CD-ROM drive.  (In the pedestal system the OCP is in the pedestal tray above the power supplies, but the floppy is in the tray beneath them.)

5	Move the tray to some handy work surface;  holding the tray vertically, from the bottom remove the four Phillips head screws that hold the floppy in place and remove it from the tray.

Replacement

1	Reverse the above procedure.  As you replace the tray in the drawer, be sure that the slides on the sides of the tray are placed on the rails in the drawer.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console).  Use the  show configuration console command to verify that the CD-ROM is configured into the system.  Test the floppy by trying to write and read a file using it.


Floppy Replacement


CD-ROM Removal and Replacement
CD-ROM (RRD45-AB) Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Expose the system drawer.  If necessary, see system drawer exposure for cabinet or pedestal systems.

3	Remove the four Phillips head screws holding the OCP tray to the system drawer.

4	Slide the tray out of the system drawer and disconnect cables attached to the OCP (unnecessary on a pedestal system), the floppy, and the CD-ROM drive.  (In the pedestal system the OCP is in the pedestal tray above the power supplies, but the CD-ROM drive is in the tray beneath them.)

5	Move the tray to some handy work surface;  holding the tray vertically, from the bottom remove the four Phillips head screws that hold the CD-ROM in place and remove it from the tray.

Replacement

1	Reverse the above procedure.  As you replace the tray in the drawer be sure that the slides on the sides of the tray are placed on the rails in the drawer.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console).  Use the show configuration or show device console command to verify that the CD-ROM is configured into the system.  Test the CD-ROM by trying to read something from it.


CD-ROM Replacement


StorageWorks Removal and Replacement
StorageWorks Shelf Removal and Replacement

Removal

1	Shut down the operating system and power down the system.

2	Remove the power cord and signal cord(s) from the StorageWorks shelf.

3	Remove the two retaining brackets holding the shelf in the mounting rail by removing the Phillips head screws holding the brackets in place..

4	Slide the shelf out of the system.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system (press the Halt button if necessary to bring up the SRM console).  Use the show device console command to verify that the StorageWorks shelf is configured into the system.


StorageWorks Shelf Replacemtent


Cabinet Fan Tray Removal and Replacement

Removal

1	Shut down the operating system and power down the system.  Unplug the AC power cable from the cabinet tray power supply.

2	If present, unplug any power cables going to the server control modules at the back of system drawers.

3	Unscrew the four Phillips head screws securing the tray to the top front of the cabinet.

4	Loosen the four hexnuts that hold the tray to the top of the cabinet.

5	Holding the bottom of the tray slide it forward so that the holes in the tray frame slip over the loosened hexnuts.

6	Move the tray to some handy work surface to remove whatever component is being replaced.

Replacement

1	Reverse the above procedure.

Verification

1	Power up the system.  If the green power LED comes on, and the fan LED is off, the cabinet tray is verified.


Cabinet Fan Tray Replacement


Fan Tray Power Supply Removal and Replacement
Fan Tray Power Supply (30-46788-01) Removal and Replacement

Removal

1	Remove the cabinet fan tray.  If necessary, see cabinet fan tray removal and replacement.

2	Disconnect the power harness from the fan fail detect module and each fan.

3	Remove the power supply cover.  It is held in place by two screws that go through the AC bulkhead spot welded to the tray weldment.

4	Disconnect the power harness from the power supply and the fan directly behind the supply.

5	Disconnect the neutral and load leads from the power supply.

6	Remove the fan directly behind the power supply.

7	Remove the four screws holding the power supply to the tray weldment.  To access the screws holding the top of the supply to the weldment, pass your screwdriver through the access holes made available when you removed the fan in step 6.  Keep track of the standoffs that provide space between the power supply and weldment.  You will need them during replacement.

Replacement

1	Reverse the above procedure.

2	Place the fan tray back in the cabinet.

Verification

1	Power up the system.  If the green power LED comes on and the fan LED is off, the cabinet tray is verified.


Fan Tray Power Supply Replacement


Fan Tray Fan Removal and Replacement
Fan Tray Fan (12-23609-21) Removal and Replacement

Removal

1	Remove the cabinet fan tray.  If necessary, see cabinet fan tray removal and replacement.

2	Disconnect the power harness from the fan to be replaced.

3	Remove the fan finger guard.

4	Remove the two remaining screws holding the fan to the tray weldment and remove the fan.

5	If the new fan does not have clip nuts, remove them from the fan.

Replacement

1	Reverse the above procedure taking care to orient the fan so that the connection to the power harness is dressed nicely.

2	Place the fan tray back in the cabinet.

Verification

1	Power up the system.  If the green power LED comes on, and the fan LED is off, the cabinet tray is verified.


Fan Tray Fan Replacement


Fan Tray Power Fail Detect Module Removal and replacement
Fan Tray Fan Fail Detect Module (54-24691-01) Removal and Replacement

Removal

1	Remove the cabinet fan tray.  If necessary see cabinet fan tray removal and replacement.

2	Disconnect the power harness from the fan fail detect module.

3	Remove the fan fail detect module.  In early systems, the module is held in place by three screws that go through the weldment, through three standoffs, through the module to nuts.  In later systems, the module snaps in place.

Replacement

1	Reverse the above procedure.

2	Place the fan tray back in the cabinet.

Verification

1	Power up the system.  If the green power LED comes on, and the fan LED is off, the cabinet tray is verified.


Fan Tray Power Fail Detect Module Replacement
Fan Tray Fan Fail Detect Module Replacement


System Drawer Power and Signal Cables
System Drawer (4100 and early 4000) Power and Signal Cables (cabinet)

The figure and table show where each power and signal cable go.

	Part Number	Description
1	17-04217-01	Main power harness
2	17-04199-01	Currebt share
3	17-04200-01	Floppy signal 34 pos
4	17-04201-01	OCP to B3050
5	17-04201-02	OCP button to board
6	17-04292-01	SCSI CD-ROM to bulkhead
7	70-32016-01	Interlock switch assembly
8	17-04196-01	RIO DC_EN signal cable
9	17-04349-01	SCM power cable from cabinet fan tray to SCM bulkhead
10	17-04350-01	SCM on-board jumper
11	17-04351-01	SCM 12V power
12	17-04363-01	PCI signal cable to SCM


System Drawer Power and Signal Cables (cabinet)
System Drawer (4100 and early 4000) Power and Signal Cables (cabinet)


System Drawer Power and Signal Cables (pedestal)
System Drawer (4100 and early 4000) Power and Signal Cables (pedestal)

The figure and table show where each power and signal cable go.

	Part Number	Description
1	17-04217-01	Main power harness
2	17-04199-01	Current share
3	17-04200-01	Floppy signal 34 pos
4	17-04302-01	OCP signal, PCI motherboard to pedestal tray bulkhed
5	17-04201-02	OCP button to board
6	17-04292-01	SCSI CD-ROM to bulkhead
7	70-32016-01	Interlock switch assembly
8	17-04196-01	RIO DC_EN signal cable
9	17-04349-01	SCM power cable from cabinet fan tray to SCM bulkhead
10	17-04350-01	SCM on-board jumper
11	17-04351-01	SCM 12V power
12	17-04363-01	PCI signal cable to SCM

Additional pedestal cables

13	17-04305-01	SCSI signal
14	17-04306-01	01SCSI power
15	17-04293-01	power cable from main power harness to pedestal tray bulkhead
16	17-04380-01	OCP signal bulkhead to OCP


System Drawer Power and Signal Cables (pedestal)
System Drawer (4100 and early 4000) Power and Signal Cables (pedestal)


System Drawer Power and Signal Cables
System Drawer (4000) Power and Signal Cables (cabinet)

The figure and table show where each power and signal cable go.

	Part Number	Description
1	17-04385-01	Main power harness
2	17-04199-01	Currebt share
3	17-04200-01	Floppy signal 34 pos
4	17-04201-01	OCP to B3050
5	17-04201-02	OCP button to board
6	17-04292-01	SCSI CDROM to bulkhead
7	70-33002-01	Interlock switch assembly
8	17-04196-01	RIO DC_EN signal cable
9	17-04349-01	SCM power cable from cabinet fan tray to SCM bulkhead
10	17-04350-01	SCM on-board jumper
11
12	17-04363-01	PCI signal cable to SCM


System Drawer Power and Signal Cables (cabinet)
System Drawer (4000) Power and Signal Cables (cabinet)


System Drawer Power and Signal Cables (pedestal)
System Drawer (4000) Power and Signal Cables (pedestal)

The figure and table show where each power and signal cable go.

	Part Number	Description
1	17-04385-01	Main power harness
2	17-04199-01	Currebt share
3	17-04200-01	Floppy signal 34 pos
4	17-04302-01	OCP signal, PCI motherboard to pedestal tray bulkhed
5	17-04201-02	OCP button to board
6	17-04292-01	SCSI CDROM to bulkhead
7	70-33002-01	Interlock switch assembly
8	17-04196-01	RIO DC_EN signal cable
9	17-04349-01	SCM power cable from cabinet fan tray to SCM bulkhead
10	17-04350-01	SCM on board jumper
11
12	17-04363-01	PCI signal cable to SCM

Additional pedestal cables

13	17-04305-01	SCSI signal
14	17-04306-01	01SCSI power
15	17-04293-01	power cable from main power harness to pedestal tray bulkhead
16	17-04380-01	OCP signal bulkhead to OCP


System Drawer Power and Signal Cables (pedestal)
System Drawer (4000) Power and Signal Cables (pedestal)


AC Input Box Removal and Replacement


AC Input Box Replacement


Power Strip Removal and Replacement (Cabinet)


Power Strip Replacement (Cabinetl)
Power Strip Replacement (Cabinet)


Power Strip Removal and Replacement (Pedestal)


Power Strip Replacement (Pedestal)


Power-Up Test Strategy
Power-Up Tests

Most power-up tests reside not on the CPU nor on any other module on the system bus but on the I/O subsystem.  For the console to run, the path from the CPU to FEPROM 0 must be functional ( CPU to FEROM 0 path).  The XSROM resides in FEPROM0 on the XBUS, off the EISA bus, off PCI 0, off IOD 0.  This path is minimally tested by SROM, a ROM that resides on each CPU on the system bus, after it tests the CPU chip.

The SROM contents are loaded into each CPUs I-cache and executed on power-up/reset.  After testing the caches on each processor chip, the SROM tests the path to the XSROM.  Once this path is tested and found reliable, layers of the XSROM are loaded sequentially into the processor chip on each CPU.  None of the SROM or XSROM power-up tests are run from memory - all run from the caches in the CPU chip thus providing excellent diagnostic isolation. If SROM or XSROM tests fail, memory is not at fault.  Later power-up tests run under the console are used to complete testing of the I/O subsystem.

There are no field-loadable diagnostics - all are built-in.  The SRM console test command is used to run console-based exercisers on the system.

Note: there are two console programs, the SRM console (for OpenVMS and DIGITAL UNIX) and an AlphaBIOS console (for Windows NT).  The SRM console is always loaded and system tests are run under it.  If the environment variable  (envar) os_type is NT and the Halt button is out, then AlphaBIOS is loaded; otherwise the SRM console remains in the system.

Topics in this section include:

SROM Power-Up Test Flow

XSROM Power-Up Test Flow

Console Power-Up Test Flow

OCP Display

Console Device Determination

Console Display at Power-Up

LEDs and Power-Up

Error Reports

Fail-Safe Loader


Power-Up Test Flow


The SROM is a 128-Kbit socketed ROM on each CPU module.  The ROM contains minimal diagnostics that test the Alpha chip and the path to the XSROM.  Once the path is verified, the SROM loads XSROM code into the Alpha chip and jumps to it.


The XSROM, or eXtended SROM, contains backup cache and memory tests, and a fail-safe loader (FSL).  The XSROM code resides in sector 0 of FEPROM 0 on the XBUS.  Sector 2 of FEPROM 0 contains a duplicate copy of the code and is used if sector 0 is bad.


The SRM console is used when the operating system is either OpenVMS or Digital UNIX.  SRM stands for Alpha System Reference Manual where the console and operating system interface is defined.  The SRM console resides in FEPROM 0 on the XBUS.


The AlphaBIOS console is used when the operating system is NT and when ECU, RCU, and other ARC-based utilities that require a graphics monitor are run.  The AlphaBIOS console resides in FEPROM 1 on the XBUS.


Environment variables are software parameters that define, among other things, the system configuration.  They are used to pass information to different pieces of software running in the system at various times.  The envar, os_type, which can be VMS, UNIX, or NT, determines, among other things, which of the two consoles is left in the system.  (The SRM console is always brought into memory but AlphaBIOS is loaded if os_type = NT and the Halt button is out.)


There are two 1 Mbyte programmable ROMs on the XBUS on the PCI 0.  FEPROM 0 contains two copies of the XSROM, PALcode, and the SRM console and decompression code.  FEPROM 1 contains the AlphaBIOS and NT HAL code.  These two FEPROMs can be flash updated using LFU.


The I-cache, instruction cache, in the EV5 and EV56 Alpha chip, is an 8-Kbyte cache that issues instructions to four different execution units in the chip.


SROM Power-Up Test Flow

The primary function of the SROM is to test the CPU chip and the path to the XSROM.

The Alpha chip has a single built-in self-test that tests the I-cache at power-up and upon reset.  Though a failure is ignored, it is highly unlikely that the SROM tests will run and the CPU will need to be replaced.

Each CPU chip loads its SROM code into its I-cache and starts executing it.  If the chip is partially functional, the SROM code continues to execute.  However, if the chip cannot perform most of its functions, that CPU hangs and its CPU pass/fail LED remains off.

If the system has more than one CPU and at least one passes both the SROM and XSROM power-up tests, the system will bring up the console.  The console checks the FW_SCRATCH  register where evidence of the power-up failure is left.  Upon finding the error, the console sends these messages to COM1 and the OCP:

COM1:	Power-up tests have detected a problem with your system

OCP:	Power-up failure

The specific tests the SROM performs are as follows:

Test Name	Logic Tested
D-cache RAM March test	D-cache access, D-cache data, D-cache address logic
D-cache Tag RAM March test	D-cache Tag store RAM, D-cache bank address logic
S-cache Data March test	S-cache RAM cells, S-cache data path, S-cache address path
S-cache Tag RAM March test	S-cache Tag store RAM, S-cache bank address logic
IOD Access test	Access to IOD CSRs, data path through CAP chip and MDP0 on each IOD, PCI0 A/D lines <31:0>


SROM Power-Up Flowchart


The SROM, XSROM, and SRM console use the FW_SCRATCH register to communicate during power-up.  The SROM or XSROM can set an error bit, and the console reads the bit and prints an error message.


XSROM Power Up Test  Flow
XSROM Power-Up Test Flow

Once the SROM has completed its tests and verified the path to the FEPROM containing the XSROM code, it loads the first 8 Kbytes of XSROM into the primary CPUs S-cache and jumps to it.  The code intentionally puts itself in I-cache and is completely register based, the D-stream is not used except for reads/writes during memory testing.  The XSROM continues to test the system after it detects and reports an error to the OCP and console device (if console = serial).

The FEPROM has sixteen 64 Kbyte sectors.  The first (XSROM) sector contains B-cache tests, memory test, and the fail-safe loader.  The second sector contains PALcode.  The third sector contains a copy of the first sector.  And the remaining thirteen sectors contain the SRM console and decompression code.

Note:  Memory tests are affected by the state of  the envar memory_test which can have the following values:

FULL 	Tests all memory

PARTIAL 	Tests up to the first 256 Mbytes

NONE	Tests 32 Mbytes

CPU Tests
Memory Tests
XSROM Power-Up Flow Chart


XSROM CPU Tests

All failures indicate a CPU failure.

Test	Test Name	New Logic Tested
11	B-cache Tag Data Line test	Access to B-cache Tags, shorts between tag data and its status and parity bits
12	B-cache Tag March test	B-cache Tag store RAMs, B-cache STAT store RAMs
13	B-cache Data Line test	B-cache data lines to B-cache data RAMs, B-cache read/write logic
14	B-cache Data March test	B-cache data RAMs, CPU chip B-cache control, CPU chip B-cache address decode, INDEX_H<2x:6> (address bus)
15	B-cache ECC Data Line test	CPU chip ECC generation and checking logic, ECC lines from CPU chip to B-cache, B-cache ECC RAMs
16	B-cache Data ECC March test	Portion of B-cache data RAMs used for ECC
17	CPU chip ECC Single/Double bit Error test	CPU chip ECC single-bit error detection and correction, ECC double-bit error detection, ECC error reporting
18	B-cache Tag Store Parity Error test	B-cache Tag array, CPU parity detection, EI_ADDR and EI_STAT register operation
19	B-cache STAT Store Parity Error test	B-cache STAT array, CPU chip B-cache STAT parity generation/detection


XSROM Memory Tests

Failure could indicate memory, CPU, or system motherboard failure.  There is no test 22.

Test	Test Name	New Logic Tested	Error Number and Description
20	Memory Data test	Data path to and from memory, Data path on memory and RAMs	01 - FF  Errors are reported as an 8-bit binary field.  A set bit indicates a module failure.  Bit <0> indicates pass/fail of MEM0_L; <1> indicates pass/fail of MEM0_H: <2> indicates pass/fail of MEM1_L;...; <7> indicates pass/fail of MEM3_H.
21	Memory Address test	Address path to and from memory Address path on memory and RAMs	Same as test 20.
23	Memory Bitmap Building	No new logic.	NA  (Maps out bad memory by way of the bitmap.  It does not completely fail memory.)
24	Memory March test	Only test that writes every data and ECC location in memory with a one and a zero	NA


The S-cache, secondary cache, in the EV5 and EV56 Alpha chip is a 96-Kbyte write-back second-level data cache.


XSROM Power-Up Flowchart


Console Power-Up Test Flow

Once the SRM console is loaded, it does further testing of the IOD and on the PCI 0 and 1.

IOD Tests
PCI 0 and 1 Tests
For both IOD tests and PCI tests trace and failure status is sent to the OCP. If any of these tests fail, a warning is sent to the SRM console device after the console prompt (or AlphaBIOS pop-up box).  The LEDs on the system bus to PCI bus bridge are controlled by the diagnostics.  If a LED is off, a failure occurred.  See LEDs and Power-Up.


IOD Tests

Test Number	Test Name	Description
1	IOD CSR Access test	Read and write all CSRs in each IOD.
2	Loopback test	Dense space writes to the IODs PCI dense space to check the integrity of ECC lines on the IODs.
3	ECC test	Loopback tests similar to test 2 but with a varying pattern to create an ECC of 0s.  Single- and double-bit errors are checked.
4	Parity Error and Fill Error tests	Parity errors are forced on the address and data lines on system bus and PCI buses.  A fill error transaction is forced on the system bus.
5	Translation Error test	A loopback test using scatter/gather address translation logic on each IOD.
6	Write Pending test	Runs test 2 with the write-pending bit set and clear in the CAP chip control register.
7	PCI Loopback test	Loops data through each PCI on each IOD testing the mask field of the system bus.
8	PCI peer-to-peer Byte Mask test	Tests that devices on the same PCI and on different PCIs can communicate.


PCI Tests

Test Name	Diagnostic Name	Description
PCEB	pceb_diag	Tests the PCI to EISA bridge chip
ESC	esc_diag	Tests the EISA system controller
8K NVRAM	nvram_diag	Tests the NVRAM
Real-Time Clock	ds1287_diag	Tests the real-time clock chip
Keyboard & Mouse	i8242_diag	Tests the keyboard/mouse chip
Flash ROM	flash_diag	Dumps contents of flash ROM
Serial and Parallel Ports and Floppy	combo_diag	Tests COM ports 1 and 2, the parallel port, and the floppy
CD-ROM	ncr810_diag	Tests the CD-ROM controller


OCP Display

The OCP, operator control panel, contains a 16-character LCD display controlled by the I2C bus chip on the XBUS.

The OCP port is enabled late in the SROM power-up flow and therefore is not available for internal CPU chip test or IOD loopback test reporting.  LEDs must be relied on for determining the results of these tests.

Once the OCP port is enabled, test progress and error reporting for both SROM and XSROM tests is sent to the display.

When there are no errors, the display shows test progress.

On a fatal error, the display identifies the suspected FRU.

If a nonfatal error is detected, the display identifies the suspected FRU, holds the message visible on the display for 3 seconds, and then continues to report power-up test progress.

During memory test 24, a rotating * pattern is displayed in OCP bit 16 to signify that the test is still executing and the system is not hung.  Test 24 can take several seconds or over a minute to run depending on memory size.

Callouts on the figure correspond to callouts listed below.

Field	Content	Display	Meaning
1	CPU number	P0P3	CPU reporting status
2	Status	TEST	Tests are executing
		FAIL	Failure has been detected
		MCHK	Machine check has occurred
		INTR	Error interrupt has occurred
3	Test number (for Digital use only)
4	Suspected device	CPU03	CPU module number
		MEM03 and L, H, or *	Memory pair number and low module, high module, or either
		IOD0	Bridge to PCI bus 0
		IOD1	Bridge to PCI bus 13
		FROM0	Flash ROM
		COMBO	COM controller4
		PCEB	PCI-to-EISA bridge4
		ESC	EISA system controller4
		NVRAM	Nonvolatile RAM4
		TOY	Real-time clock4
		I8242	Keyboard and mouse controller4


OCP Display Format
OCP Display


LEDs and Power-Up

Power-up LEDs can be seen through the screen at the back of the system drawer. There are 3 LEDs on CPU modules, 4 on the system bus to PCI bus bridge module, and 11 on the power control module. There are no LEDs on memory modules.  For information on the PCM LEDs, see PCM LEDs .

CPU LEDs
System bus to PCI bus Bridge (B3040-AA)
System bus to PCI bus Bridge (B3040-AB)


CPU LEDs	State	Description
DC_OK	On Off	DC power okay DC power present, but nothing is running.  Or AC power is not applied or is broken.
SROM Oscillator Functioning	On Off	SROM oscillator is functioning.  Should be on only very early during power-up or resst. SROM oscillator is functioning unless this LED is off at power-up or reset.
CPU Self-Test Pass	On Off	CPU chip passed self-test. CPU chip failed self-test.
2.5 Volt Regulator  (EV56 only)	On Off	On-board regulator functioning propperly On-board regulator not functioning propperly.

The CPU self-test pass LED does not mean that the entire module passed or failed self-test, only that the CPU chip did or did not pass.


During normal operation all four LEDs on the B3040-AA bridge module are on.

Bridge LEDs	State	Description
IOD 0	On Off	IOD 0 passed SROM CSR loopback test. IOD 0 failed SROM CSR loopback test.
IOD 1	On Off	IOD 1 passed SROM CSR loopback test. IOD 1 failed SROM CSR loopback test.
POWER_FAN_OK	On Off	System power and fans are okay. System power or fan failure.
TEMP_OK	On Off	System temperature is within normal limits.   Overtemperature condition has occurred.

The IOD LEDs do not mean that the entire module passed or failed self-test, only that the CSR loopback tests did or did not pass.


During normal operation the two LEDs on the B3040-AB bridge module are on.

Bridge LEDs	State	Description
IOD 2	On Off	IOD 2 passed SROM CSR loopback test. IOD 2 failed SROM CSR loopback test.
IOD 3	On Off	IOD 3 passed SROM CSR loopback test. IOD 3 failed SROM CSR loopback test.

The IOD LEDs do not mean that the entire module passed or failed self-test, only that the CSR loopback tests did or did not pass.


LED Display at Power-Up


Console Device Determination

Console Device Options

The console device can be either  a serial terminal connected to COM port 1, or a VGA device off an adapter on PCI0.  Systems running NT must have a graphics monitor as the console device and run AlphaBIOS as the console program.

During power-up, the SROM and the XSROM always send progress and error messages to the OCP and to COM port 1 if the console envar is set to serial.  If the console envar is set to graphics, no messages are sent to COM1.  On AlphaServer 4100 systems the presence of a terminal attached to COM1 is not guaranteed (a modem could be attached to it for example).

After the SROM and XSROM have completed their tasks, the SRM console program, as it starts, determines where to send its power-up messages.

If the console device is connected to COM1, both the SROM and XSROM send messages to it once it has been initialized.  If the console device is a VGA device, console power-up messages are sent to it but SROM and XSROM power-up messages are lost. No matter what the console environment variable, each of the three programs send messages to the LCD display on the OCP.

These conditions are described by the following table:

Messages	Console Set To
Sent By	Serial	Graphics
SROM	COM 1	Lost
XSROM	COM 1	Lost
Console	COM 1	VGA
Changing Where Console Ouput Is Displayed

If the console envar is set to serial and no terminal is attached to COM port 1, pressing a carriage return on a graphics monitor attached to the system makes it the console device and the console prompt is sent to it.  If the console envar is set to graphics and no graphics monitor is attached to the adapter, pressing a carriage return on a character terminal attached to COM port 1 makes it the console device and the console prompt is sent to it.  This condition only occurs after the console has completely powered up and the os_type environment variable is not set to NT.


COM port 1 is one of two serial ports on the server control module in at the bottom of the PCI card cage.


COM1 is another name for COM port 1.


Console Device Determination Flowchart


Console Display at Power-Up

If the environment variable was set to graphics, the display would be missing the lines beginning with the line that reads SROM V1.0 on cpu0 and ends with the line that reads Memory testing complete on cpu1.  In other words all the SROM and XSROM messages would be missing.  See Console Device Determination.

1   On power-up or reset, each CPU chip loads SROM code into its I-cache and tests the processor chip. If all tests pass, the modules LED lights. If any test fails, the LED remains off and power-up terminates for that particular CPU.

      The primary CPU, CPU0, unless it fails, executes a loopback test on each PCI bridge. If this test passes, the bridge LED lights. If it fails, the LED remains off and power-up continues. The PCI0 command/address lines are tested and EISA system controller, PCI-to-EISA bridge, COM1 port, and control panel port are all initialized.

      Each CPU prints an SROM message to the device attached to the COM1 port and to the control panel display. (The banner prints to COM1 if the console environment variable is set to serial. If it is set to graphics, nothing prints to the console terminal, only to the control panel display, until the graphics controller is initialized late in the power-up process.)

2    The S-cache on each CPU module is initialized, and the XSROM code from sector 0 in FEPROM0 on PCI 0 is unloaded into them. (If the unload is not successful, the SROM unloads XSROM code from sector 2 of FEPROM0.  If the second try fails, the CPU loads the fail-safe loader.)

      Each CPU starts the XSROM code, which prints an XSROM banner to COM1 and to the control panel display.

3    Each CPU tests if present, its B-cache.  If a failure occurs, a message is printed to the COM1 port and to the control panel display immediately.

      Each CPU prints a B-cache completion message to COM1.

4     The primary CPU is again determined.  The primary then sizes memory by requesting that information from the I squared C bus.

       Information on memory pairs is sent to COM1.  If an illegal memory configuration is detected, a warning message is sent to COM1 and the control panel display.

5    Memory is initialized and tested, and test traces are sent to COM1 and the control panel display. (The numbers for tests 20 and 21 might appear interspersed; this is normal behavior. Test 24 can take several minutes if the memory is very large. The message P0 TEST 24 MEM** is displayed on the control panel display; the second asterisk rotates to indicate that testing is continuing. All CPUs in a multiprocessor system share the memory testing to minimize test time.  If a failure occurs, a message is printed to the COM1 port and to the control panel display immediately.

      Each CPU sends a test completion message to COM1.

6    The primary CPU is determined for the last time. The primary CPU unloads PALcode and decompression code from the FEPROM on the PCI 0 to its S-cache (and B-cache if present).  The primary CPU then jumps to the PALcode to start the SRM console.

      The primary CPU prints starting console on CPU 0 indicating that it is running the console.  Beginning with this message, the power-up display is printed to any console terminal, regardless of the state of the console environment variable. (If console is set to graphics, the display from here to the end is saved in a memory buffer and printed to the graphics monitor after the PCI buses are sized and the graphics device is initialized.)

7    The console is started on each of the secondary CPUs.  A status message prints for each CPU.

8     The PCI bridges (indicated as IODn) are probed and the devices are reported. I/O adapters are configured.

9    The SRM console banner and prompt are printed. (The SRM prompt is shown as P00>>>. It can, however, be P01>>>, P02>>>, or P03>>>. The number indicates the primary processor.) If the auto_action environment variable is set to boot or restart and the os_type environment variable is set to unix or openvms, the Digital UNIX or OpenVMS operating system boots.

     If the system is running the Windows NT operating system (the os_type environment variable is set to nt), the SRM console loads and starts the AlphaBIOS console.


In AlphaServer 4000/4100 systems, CPU0 is always the primary unless it fails self-test; in which case CPU1 becomes the primary.  It is not possible to prevent a CPU from becoming primary.  Primary determination is sequential: CPU0 first, and if present CPU1 second, CPU2 third, and CPU3 fourth.


The IOD is the acronym used by software to refer to the system bus to PCI bus bridge.  IOD 0 connects to PCI 0; IOD 1 connects to PCI bus 1.  In AlphaServer 4000 systems if a second PCI I/O card cage is present, IOD 2 connects to PCI 2; IOD 3 connects to PCI 3.


The OCP, operator control panel, has the On/Off button, the Halt button, the Reset button, and the display panel.  In the pedestal version of the system it is located at the front top of the cabinet.  In the cabinet version it is located under the front of the system drawer on the right.


Power-Up Display

SROM V1.0 on cpu0                                   1

SROM V1.0 on cpu1

SROM V1.0 on cpu2

SROM V1.0 on cpu3

XSROM V1.0 on cpu2                                  2

XSROM V1.0 on cpu1

XSROM V1.0 on cpu3

XSROM V1.0 on cpu0

BCache testing complete on cpu2                     3

BCache testing complete on cpu0

BCache testing complete on cpu3

BCache testing complete on cpu1

mem_pair0 - 128 MB                                  4

mem_pair1 - 128 MB

20..20..21..20..21..20..21..21..23..24..24..24..24. 5

Memory testing complete on cpu0

Memory testing complete on cpu1

Memory testing complete on cpu3

Memory testing complete on cpu2

starting console on CPU 0                           6

sizing memory                                       7

  0    128 MB SYNC

  1    128 MB SYNC

starting console on CPU 1

starting console on CPU 2

starting console on CPU 3

probing IOD1 hose 1                                 8

  bus 0 slot 1 - NCR 53C810

  bus 0 slot 2 - DECchip 21041-AA

  bus 0 slot 3 - NCR 53C810

  bus 0 slot 4 - DECchip 21040-AA

probing IOD0 hose 0

  bus 0 slot 1 - PCEB

Configuring I/O adapters...

AlphaServer 4100 Console V1.0, 13-MAR-1996 18:18:26 9

P00>>>


Error Reporting on the Console

SROM Errors

Click here for SROM error reports  [image].

The SROM reports machine checks, pending interrupt/exception errors, and errors related to corruption of FEPROM0.  If SROM failures are fatal, the particular CPU will hang and only the CPU self-test pass LEDs and or the LEDs on the system bus to PCI bus module will indicate the failure.

For information on SROM tests, see SROM power-up test flow.

XSROM Errors

Click here for XSROM error reports  [image].

The XSROM reports errors related to all its tests.

For information on XSROM tests, see XSROM power-up test flow.


SROM Error Report

Unexpected MCHK (CPU error)

UNEX MCHK on CPU 0

EXC_ADR 42a9

EISTAT fffffff004ffffff

EIADDR ffffff000000801f

SCSTAT 0

SCADDR FFFFFF0000005F2F

Pending Interrupt/Exception (CPU error)

INT-EXC on CPU0

ISR	400000

EISTAT fffffff007ffffff

EIADDR ffffff7fffffffdf

FILSYN 631B

BCTGADR ffffffa7fffcafff

Messages reported for FEPROM failures (PCI 0 error)

Sctr 0 -XSROM headr PTTRN fail

Sctr 0 -XSROM headr CHKSM fail

Sctr 0 -XSROM code CHKSM fail

Sctr 2 -XSROM headr PTTRN fail

Sctr 2 -XSROM headr CHKSM fail

Sctr 2 -XSROM code CHKSM fail


XSROM Error Report

The XSROM reports B-cache test errors and memory test errors.  It also reports a warning if memory is illegally configured.

B-cache error (CPU error)

TEST ERR on cpu0	#CPU running the test

FRU	cpu0

err#	2

tst#	11

exp:	5555555555555555	#Expected data

rcv:	aaaaaaaaaaaaaaaa	#Received data

adr:	ffff8	#B-cache location error occurred

Memory error (memory module indicated)

20..21..

TEST ERR on cpu0	#CPU running test

FRU:	MEM1L	#The Low member of memory pair 1

err#	c

tst#	21

22..23..24..Memory testing complete on cpu0

Memory configuration error (operator error)

ERR!  mempair0 misconfigured

ERR!  mempair1 card size mismatch

ERR!  mempair1 card type mismatch

ERR!  mempair1 EMPTY

Messages reported for FEPROM failures (PCI 0 error)

Sctr 1 -PAL headr PTTRN fail

Sctr 1 -PAL headr CHKSM fail

Sctr 1 -PAL code CHKSM fail

Sctr 3 -CONSLE headr PTTRN fail

Sctr 3 -CONSLE headr CHKSM fail

Sctr 3 -CONSLE code CHKSM fail


The Fail-safe Loader
Fail-Safe Loader

The fail-safe loader is a small software routine that loads the SRM console image from a floppy.  Once the console is running, run LFU to update FEROM0 with a new image.

If the fail-safe loader loads, the following conditions exist on the machine:

1.	The SROM has passed its tests and successfully unloaded the XSROM.  Should the SROM fail to unload the XSROM, it will report the failure to the OCP display and COM1 if it can, and the system will hang.  See console device determination.

2.	The XSROM has completed its B-cache and memory tests but has failed to unload the PALcode in FEPROM0 sector 1 or the decompression code in FEPROM0 sector 2.

3.	The XSROM reports the errors encountered and loads the fail-safe loader.


FEROM0 contains images of the XSROM, PALcode, decompression, and console code.


Server Control Module
Server Control Module (54-24674-01)

The server control module is placed at the bottom of the PCI card cage on the left for the drawer fron the back and is connected to the PCI motherboard.  The module has a passive function and an active function.  It passively passes through to its bulkhead COM port 1 (the serial line for the SRM console), COM port 2, a mouse connection, a keyboard connection, and a parallel port connection.  Actively it contains the necessary hardware for the remote console monitor (RCM).

The RCM is used to monitor and control the system remotely through a modem or locally by entering the escape sequence at the SRM console prompt on the local serial console terminal.  The RCM firmware, not part of the SRM console, has its own command interface that allows the user to perform the tasks that can usually be done from the serial console terminal.  RCM console commands are used to reset, halt, and power the system on or off, regardless of the operating system or hardware state.

The RCM also provides an autonomous and automatic, when enabled, dial-out capability when it detects a power failure within the system.  When triggered, the RCM dials a paging service at 30-minute intervals until the administrator clears the alert within the RCM.

For extensive information on the RCM, see Remote Console Monitor help file.  Note that taking this jump leaves this help file.  Use the Back button to return.


Server Control Module


Entering and Leaving Command Mode

Use the default escape sequence shown below to enter RCM command mode.  You can enter RCM command mode from the SRM console, the operating system, or an application by entering:

^]^]rcm

The character string "^]" is created by simultaneously holding down the Ctrl key and pressing the ] key (right square bracket).  The firmware prompt, RCM>, should now be displayed.

The RCM quit command reconnects the terminal to the system console port.


Dial-Out Alerts

The RCM can be configured to automatically dial out through the modem (usually to a paging service) only when the managed server loses primary power by either a power fault or a manual shutdown (turning the system off using the On/Off button).