Contents of DEC 7000 Pocket Service Guide

This document is intended for Digital service engineers. It supplies key information on DEC 7000 systems in these sections:

Section	Description
Addressing	Provides information on address space layout, addresses, and device types.
Console	Contains a list of the console commands, syntax, and examples.
Controls and Indicators	Discusses the controls and indicators on various components of the system.
FRU Locations	Identifies the field-replaceable units in the platform.
Registers	Lists the registers in this system and provides an illustration of each.
Restoring Corrupted ROMs	Provides instructions for restoring corrupted EEPROMs and for updating corrupted firmware.
Self-Test and Diagnostics	Lists the tests in each self-test and shows examples of running diagnostics on adapters and device controllers.
System Errors	Includes information on the EEPROM error logs and the system error log.

See the Glossary for definitions of terms related to this system.

For information on conventions used in this document and lists of related documents, see the Preface.


Registers

Each of these topics is a compilation of the major registers in a component of the DEC 7000 system.

KN7AA LSB Required Registers

KN7AA CPU-Specific Registers

KN7AA Internal Processor Registers

KN7AA Console Registers

MS7AA Registers

I/O Port Registers

DWLMA Registers

DWLAA Registers


KN7AA LSB Required Registers

How to examine these registers

Mnemonic	Register Name	Offset	Access
LDEV	Device	BB + 0000	R/W
LBER	Bus Error	BB + 0040	R/W
LCNR	Configuration	BB + 0080	R/W
LMMR0	Memory Mapping 0	BB + 0200	R/W
LMMR1	Memory Mapping 1	BB + 0240	R/W
LMMR2	Memory Mapping 2	BB + 0280	R/W
LMMR3	Memory Mapping 3	BB + 02C0	R/W
LMMR4	Memory Mapping 4	BB + 0300	R/W
LMMR5	Memory Mapping 5	BB + 0340	R/W
LMMR6	Memory Mapping 6	BB + 0380	R/W
LMMR7	Memory Mapping 7	BB + 03C0	R/W
LBESR0	Bus Error Syndrome 0	BB + 0600	RO
LBESR1	Bus Error Syndrome 1	BB + 0640	RO
LBESR2	Bus Error Syndrome 2	BB + 0680	RO
LBESR3	Bus Error Syndrome 3	BB + 06C0	RO
LBECR0	Bus Error Command 0	BB + 0700	RO
LBECR1	Bus Error Command 1	BB + 0740	RO
LIOINTR	I/O Interrupt	BSB + 0000	R/W
LIPINTR	Interprocessor Interrupt	BSB + 0040	R/W


BB

BB is the LSB node space base address (in hex) of the CPU module.

If the module  is in this slot	BB is
0	3 F800 0000
1	3 F840 0000
2	3 F880 0000
3	3 F8C0 0000
4	3 F900 0000
5	3 F940 0000
6	3 F980 0000
7	3 F9C0 0000


BSB

BSB is the broadcast space base address in hex, 3 FE00 0000.


KN7AA Device Register

Mnemonic:	LDEV
Offset:	BB + 0000
Access:	R/W
Click in a field or on its name for the description.

The LDEV register is loaded during initialization with information that identifies a node.


KN7AA Bus Error Register

Mnemonic:	LBER
Offset:	BB + 0040
Access:	R/W

Click in a field or on its name for the description.

The LBER register stores the error bits that are flagged when an LSB node detects errors in the LSB operating environment and logs the failing commander ID. The status of this register remains locked until software resets the error bit(s).


KN7AA Configuration Register

Mnemonic:	LCNR
Offset:	BB + 0080
Access:	R/W

Click in a field or on its name for the description.

The LCNR register contains LSB configuration setup and status information.


KN7AA Memory Mapping Registers 0--7

Mnemonic:	LMMR0--7
Offset:	BB+ 0200 -- BB + 03C0
Access:	R/W

Click in a field or on its name for the description.

Eight LMMR registers define the memory configuration for all memory modules installed in the system. They are copies of the equivalent AMR registers in memory modules installed in the system. Each LMMR register is associated with the LSB module whose node ID matches the three lower bits of the LMMR address. Thus, LMMR0 is associated with node 0, LMMR1 is associated with node 1, and so on. LMMR registers are loaded during system initialization when the memory modules are initialized and configured.


KN7AA Bus Error Syndrome Registers 0--3

Mnemonic:	LBESR0--3
Offset:	BB + 0600 -- BB + 06C0
Access:	RO

Click in a field or on its name for the description.

The LBESR registers contain the syndrome computed from the LSB Data and ECC fields received during the cycle when an error was detected. The syndrome is the bit-by-bit difference between the ECC check code generated from the received data and the ECC field received over the bus. The LBESR registers lock only on the first occurrence of an ECC error (LBER<CE> or LBER<UCE>). Subsequent ECC errors set LBER<CE2> or LBER<UCE2> until software clears those error bits.

See Syndrome Values


KN7AA Bus Error Command Registers 0--1

Mnemonic:	LBECR0--1
Offset:	BB + 0700, BB + 0740
Access:	RO

Click in a field or on its name for the description.

The LBECR registers save the contents of the LSB command and address fields during the command cycle when an error is detected. The following errors detected by the CPU module lock the LBECR registers:

•	LSB uncorrectable ECC error (LBER<1>)

•	LSB correctable ECC error (LBER<3>)

•	LSB command parity error (LBER<5>)

•	LSB CSR data parity error (LBER<7>)

•	LSB nonexistent address error (LBER<12>)

•	LSB arbitration drop error (LMERR<10>

•	LEVI P-map parity error (LMERR<3:0>)

•	LEVI B-cache tag parity error (LMERR<4>)

•	LEVI B-cache status parity error (LMERR<5>)

•	LEVI B-map parity error (LMERR<6>)


KN7AA I/O Interrupt Register

Mnemonic:	LIOINTR
Offset:	BSB + 0000
Access:	R/W

Click in a field or on its name for the description.

The LIOINTR register is used by the LSB I/O module to signal interrupts from the LSB I/O system to processors.

NOTE: A maximum of four processors can receive interrupts regardless of the system configuration. In a multiprocessor system with more than four CPU modules, only CPU0 to CPU3 can receive interrupts.

See Interrupt Mapping.


Interrupt Mapping

Each interrupt target is assigned four bits of interrupt in the LIOINTR register corresponding to the four I/O interrupt levels. A given CPU only looks at the four bits that correspond to its target assignment. This allows interrupts to be targeted to a single CPU or up to four CPUs, depending on the data supplied in the bus CSR write transaction from the I/O module.

This register appears in LSB broadcast space. Writes that address this location are accepted without regard to node ID. Thus, all CPUs accept writes to the register. The register bits are write one to set (W1S). Multiple writes with a value of one to a given bit in this register post an equal number of interrupts to the targeted CPU. Reads to this location are undefined. Any given CPU implements only four bits of this register.

The following table shows the mapping of LSB interrupt levels to DECchip 21064 interrupt levels.

LSB Interrupt Level	DECchip 21064 IPL (Dec)
3	IPL 23
2	IPL 22
1	IPL 21
0	IPL 20

When any of the four interrupt-pending bits is set, the LEVI gate array correspondingly asserts the IOINTR<3:0> signals. The CPU module then uses these signals to assert the appropriate interrupt request to the DECchip 21064. The LEVI-A gate array also watches for LSB CSR reads to the LILID0-3 registers in the IOP module. When an LSB CSR read for LILID0 is asserted on the LSB bus, the LEVI-A gate array correspondingly deasserts IOINTR<0>. The LEVI-A gate array performs the same function on LILID3, LILID2, and LILID1.

At least one CPU module must reside in slots 0 to 3.


KN7AA Interprocessor Interrupt Register

Mnemonic:	LIPINTR
Offset:	BSB + 0040
Access:	R/W

Click in a field or on its name for the description.

The LIPINTR register is used by the CPU modules to signal interprocessor interrupts.

See Interprocessor Interrupt.


Interprocessor Interrupt

When a processor wishes to post an interrupt to another processor, it simply writes to the LIPINTR register to set the relevant bit. The bits in LIPINTR<5:0> are write one to set (W1S).

This register appears in LSB broadcast space. Writes that address this location are accepted without regard to node ID. Thus, all CPUs accept writes to the register. Reads to this location are undefined.

The contents of LIPINTR<5:0> are qualified by the node ID. If a given CPU node is selected, the LEVI-A gate array asserts the IPINTR signal for one processor external clock. The CPU module ORs this signal and issues the appropriate interrupt request to the DECchip 21064.


KN7AA CPU-Specific Registers

How to examine these registers

Mnemonic	Register Name	Offset	Access
LMODE	Mode	BB + C00	R/W
LMERR	Module Error	BB + C40	R/W
LLOCK	Lock Address	BB + C80	RO
LDIAG	Diagnostic Control	BB + D00	R/W
LTAGA	Tag Address	BB + D40	R/W
LTAGW	Tag Write Data	BB + D80	R/W
LCON	Console Communication	BB + E00 BB + E40	R/W
LPERF	Performance Counter Control	BB + F00	R/W
LCNTR	Performance Counter	BB + F40 BB + F80	R/W
LMISSADDR	Last Miss Address	BB + FC0	RO


KN7AA Mode Register

Mnemonic:	LMODE
Offset:	BB + C00
Access:	R/W

Click in a field or on its name for the description.

The LMODE register contains mode setup for an operational CPU module (as opposed to the LDIAG register which provides mode setup for a CPU module while running diagnostics).

NOTE: To determine if this register is in a LEVI pass 1, 2, or 3 chip, examine bits <19:16>.


KN7AA Module Error Register

Mnemonic:	LMERR
Offset:	BB + C40
Access:	R/W

Click in a field or on its name for the description.

The LMERR register provides module-specific error information. If any bits are set in this register, NSES (LBER<18>) is also set.


KN7AA Lock Address Register

Mnemonic:	LLOCK
Offset:	BB + C80
Access:	RO

Click in a field or on its name for the description.

The LLOCK register contains the physical address and lock bit of the most recently executed LDxL instruction that referenced memory space.


KN7AA Diagnostic Control Register

Mnemonic:	LDIAG
Offset:	BB + D00
Access:	R/W

Click in a field or on its name for the description.

The LDIAG register allows a diagnostic program to manipulate various sections of the CPU module for complete testing.

See Diagnostic Notes.


Diagnostic Notes

The following notes offer additional information for performing diagnostics on the CPU module.

How to Make the B-Cache Emulate Main Memory

The CPU module can be made to present its cache as main memory to the LSB environment by setting BIU_CTL<FHIT>, LDIAG<FDIRTY>, and LMODE<WMODE>=10 (bin). The selection of this mode is possible under the following two conditions: (1) Only a single CPU module is placed in this mode; (2) No memory module is present in the system.

How to Read/Write Tags

The combinations of LDIAG, LTAGA, LTAGW, and Gbus$LtagRW registers allow diagnostic programs or error recovery programs to read or write any tag store on the CPU module. LDIAG<TAG_SEL> selects the tag store of interest; LTAGA selects the location in the tag store; LTAGW supplies the value to be written into the tag; and Gbus$LtagRW provides the mechanism. The use of the Gbus register allows LEVI to perform the tag access without the need for any special setup (that is, FRIGN). Even though the Gbus registers are specified to be a byte in length, reads from Gbus$LtagRW return a full longword of data, since no physical Gbus location is actually being read. Gbus address space is used for convenience only.

Writing Tags

1	Write LDIAG<TAG_SEL> to select the tag store.

2	Write LTAGA to select the location.

3	Write LTAGW to specify the value to be written.

4	Write Gbus$LtagRW with any random data. This action triggers LEVI to perform the tag write as set up.

Reading Tags

1	Write LDIAG<TAG_SEL> to select the tag store.

2	Write LTAGA to select the location.

3	Read Gbus$LtagRW. This action triggers LEVI to perform the tag read as set up. The data returned is the value from the selected tag location in the format specified by the LTAGW register.


KN7AA Tag Address Register

Mnemonic:	LTAGA
Offset:	BB + D40
Access:	R/W

Click in a field or on its name for the description.

The LTAGA register provides a means by which a diagnostic program can specify the location to be accessed in the CPU cache data and tag RAM structures.


KN7AA Tag Write Data Register

Mnemonic:	LTAGW
Offset:	BB + D80
Access:	R/W

Click in a field or on its name for the description.

The LTAGW register provides a means by which a diagnostic program can specify the value to be loaded into the CPU caches and tag RAM structures.


KN7AA Console Communication Registers

Mnemonic:	LCON
Offset:	BB + E00 -- BB + E40
Access:	R/W

Click in a field or on its name for the description.

The LCON register provides a nonmemory communication location for the KN7AA console firmware. The value contained in this register has no direct effect on any CPU module hardware.


KN7AA Performance Counter Control Register

Mnemonic:	LPERF
Offset:	BB + F00
Access:	R/W

Click in a field or on its name for the description.

The LPERF register defines how the LEVI performance registers (LCNTR0, LCNTR1, and LMISSADDR) behave. Each counter register has an event select field, control bits, and an overflow bit. Some of the events to be counted are subject to the node ID mask. The LMISSADDR register loads miss addresses based on the value of the Miss Address Frequency field.

NOTE: See LMODE<LEVI_REV> for the LEVI revision.


KN7AA Performance Counter Registers

Mnemonic:	LCNTR
Offset:	BB + F40 -- BB + F80
Access:	R/W

Click in a field or on its name for the description.

The LCNTR registers count events selected by the Select (LC0_SEL and LC1_SEL) and N_MASK fields of the LPERF register. Each register is a 32-bit counter with an associated overflow bit (LPERF<0> for LCNTR0 and LPERF<1> for LCNTR1). With the correct values of the Select fields, the LCNTR registers can be cascaded to form a single 64-bit register. The two counters are enabled and disabled independently through their associated LPERF control bits. The LCNTR registers can be read while the counters are stopped or running. The registers can also be stopped and restarted without resetting to zero. A write to an LCNTR register resets the counter and the associated overflow bit in the LPERF register, and sets the counter to the stopped state. Writes to LCNTR registers are ignored.


KN7AA Last Miss Address Register

Mnemonic:	LMISSADDR
Offset:	BB + FC0
Access:	RO

Click in a field or on its name for the description.

The LMISSADDR register captures every nth B-cache miss address determined by LPERF<MA_FREQ>. The miss may be due to a read, a write, or a shared block.

NOTE: See LMODE<LEVI_REV> for the LEVI revision.


KN7AA Internal Processor Registers

These registers cannot be examined, but some are listed in response to the mchk command and some in error log reports.

Mnemonic	Register Name	Index	Access
Ibox

TB_TAG	Translation Buffer Tag	0	W
ITB_PTE	Instruction Translation Buffer PTE	1	R/W
ICCSR	Instruction Cache Control/ Status	2	R/W
ITB_PTE_TEMP	Instruction Translation Buffer PTE_TEMP	3	R
EXC_ADDR	Exception Address	4	R/W
SL_RCV	Serial Line Receive	5	R
ITBZAP	Instruction Translation Buffer ZAP	6	W
ITBASM	Instruction Translation Buffer ASM	7	W
ITBIS	Instruction Translation Buffer IS	8	W
PS	Processor Status	9	R/W
EXC_SUM	Exception Summary	10	R/W
PAL_BASE	PAL Base Address	11	R/W
HIRR	Hardware Interrupt Request	12	R
SIRR	Software Interrupt Request	13	R/W
ASTRR	Asynchronous Trap Request	14	R/W
HIER	Hardware Interrupt Enable	16	R/W
SIER	Software Interrupt Enable	17	R/W
ASTER	AST Interrupt Enable	18	R/W
SL_CLR	Serial Line Interrupt Clear	19	W
SL_XMIT	Serial Line Transmit	22	W

Abox

TB_CTL	Translation Buffer Control	0	W
DTB_PTE	Data Translation Buffer PTE	2	R/W
DTB_PTE_TEMP	Data Translation Buffer PTE_TEMP	3	R
MMCSR	Memory Management CSR	4	R
VA	Virtual Address	5	R
DTBZAP	Data Translation Buffer ZAP	6	W
DTBASM	Data Translation Buffer ASM	7	W
DTBIS	Data Translation Buffer IS	8	W
BIU_ADDR	Bus Interface Unit Address	9	R
BIU_STAT	Bus Interface Unit Status	10	R
DC_STAT	D-Cache Status	12	R
FILL_ADDR	Fill Address	13	R
ABOX_CTL	Abox Control	14	W
ALT_MODE	Alternate Processor Mode	15	W
CC	Cycle Counter	16	W
CC_CTL	Cycle Counter Control	17	W
BIU_CTL	Bus Interface Unit Control	18	W
FILL_SYND	Fill Syndrome	19	R
BC_TAG	B-Cache Tag	20	R
FLUSH_IC	Flush IC	21	W
FLUSH_IC_ASM	Flush IC_ASM	23	W

PAL

PAL_TEMP	PALcode Temporary	31--00	R/W


Register Cannot Be Examined

Because this register cannot be examined, no illustration is provided.


KN7AA Translation Buffer Tag Register

Mnemonic:	TB_TAG

Click in a field or on its name for the description.

The TB_TAG IPR holds the tag for the next translation buffer update operation in the instruction translation buffer (ITB) or the data translation buffer (DTB). The tag is written to a temporary register and not transferred to the ITB or DTB until the Instruction Translation Buffer Page Table Entry (ITB_PTE) or the Data Translation Buffer Page Table Entry (DTB_PTE) IPR is written. The entry to be written is chosen at the time of the ITB_PTE or DTB_PTE write operation by a not-last-used (NLU) algorithm, implemented in hardware.


KN7AA Instruction Translation Buffer PTE Register

Mnemonic:	ITB_PTE
The ITB_PTE IPR represents 12 page table entries split into two distinct arrays. The first eight PTEs provide small page (8 Kbytes) translations while the remaining four provide large page (4 Mbytes) translations. The entry to be written is selected by a not-last-used algorithm implemented in hardware for each array independently, and the status of the TB_CTL IPR. Writes to the ITB_PTE IPR use the memory format bit positions as described in the Alpha Architecture Reference Manual, with the exception that some fields are ignored.

Refer to the chapter discussing the appropriate operating system support in the KN7AA CPU Technical Manual for the bit definitions of the PTE.


KN7AA Instruction Cache Control/Status Register

Mnemonic:	ICCSR

Click in a field or on its name for the description.

The ICCSR IPR contains various Ibox hardware enables. The only architecturally defined bit in this register is the floating-point enable (FPE), which enables floating-point instructions. When cleared, all floating-point instructions generate FEN exceptions. Most bits of this IPR are cleared by hardware at reset. Fields that are not cleared at reset include ASN, PC0, and PC1.

NOTE: The hardware enable bit allows the PALcode instructions to execute in kernel mode. This bit is intended for diagnostic or operating system alternative PALcode routines only. It does not allow access to the ITB IPRs if not running in PALmode.


KN7AA Instruction Translation Buffer PTE_TEMP Register

Mnemonic:	ITB_PTE_TEMP
The ITB_PTE_TEMP IPR is a holding register for ITB_PTE read data. Reads of ITB_PTE require two instructions to return data to the register file. The two instructions are as follows:

1	Read the ITB_PTE IPR data to the ITB_PTE_TEMP IPR.

2	Read the ITB_PTE_TEMP IPR data to the integer register file.

The ITB_PTE_TEMP IPR is updated on all ITB accesses, both read and write. A read of the ITB_PTE to the ITB_PTE_TEMP should be followed closely by a read of the ITB_PTE_TEMP to the register file.

Refer to the chapter discussing the appropriate operating system support in the KN7AA CPU Technical Manual for the bit definitions of the PTE.


KN7AA Exception Address Register

Mnemonic:	EXC_ADDR

Click in a field or on its name for the description.

The EXC_ADDR IPR is a read/write register used to restart the system after exceptions or interrupts.

See EXC_ADDR IPR Usage.


KN7AA Serial Line Receive Register

Mnemonic:	SL_RCV

Click in a field or on its name for the description.

The SL_RCV IPR contains a single read-only bit (RCV) which is used with the interrupt control registers, the sRomD_h signal, and the sRomClk_h signal to provide an on-chip serial line function.


KN7AA Processor Status Register

Mnemonic:	PS
The PS IPR contains only the current mode bits of the architecturally defined PS. Refer to the Alpha Architecture Reference Manual for the functional descriptions of the current mode bits.


KN7AA Exception Summary Register

Mnemonic:	EXC_SUM

Click in a field or on its name for the description.

The EXC_SUM IPR records the various types of arithmetic traps that occurred since the last time the EXC_SUM was written (cleared). When the result of an arithmetic operation produces an arithmetic trap, the corresponding EXC_SUM bit is set.

The register containing the result of the operation is recorded in the Exception Register Write Mask parameter (see the Alpha Architecture Reference Manual), as a single bit in a 64-bit field specifying registers F31-F0 and I31-I0. The EXC_SUM IPR provides a one-bit window to the Exception Register Write Mask parameter. This is visible only through the EXC_SUM IPR. Each read to the EXC_SUM shifts one bit in order F31-F0 then I31-I0. The read also clears the corresponding bit. The EXC_SUM must be read 64 times to extract the complete mask and clear the entire register. If no integer traps are present (IOV=0), only the first 32 bits of the corresponding register in the floating-point register file need to be read and cleared.

Any write to EXC_SUM clears bits <8:2> and does not affect the write mask bit. The write mask parameter bit clears three cycles after a read. Code intended to read the parameter must allow at least three cycles between reads. This allows the clear and shift operations to complete in order to ensure reading successive bits.


KN7AA PAL Base Address Register

Mnemonic:	PAL_BASE

Click in a field or on its name for the description.

The PAL_BASE IPR contains the base address for PALcode. This register is cleared by the hardware at reset. It establishes the reference (base) address to which an offset is added to determine the entry point to the PALcode.


KN7AA Hardware Interrupt Request Register

Mnemonic:	HIRR

Click in a field or on its name for the description.

The HIRR IPR provides a record of all currently outstanding interrupt requests and summary bits at the time of the read. For each bit of the HIRR<5:0>, there is a corresponding bit of the Hardware Interrupt Enable IPR (HIER) that must be set to enable that interrupt.

In addition to returning the status of the hardware interrupt requests, a read of the HIRR returns the state of the software interrupt and AST requests.

NOTE: A read of the HIRR can return a value of zero if the hardware interrupt was released before the read (passive release).

The register guarantees that the HWR bit reflects the status as shown by the HIRR bits. All interrupt requests are blocked while executing in PALmode.


KN7AA Software Interrupt Request Register

Mnemonic:	SIRR

Click in a field or on its name for the description.

The SIRR IPR is used to control software interrupt requests. For each bit of the SIRR there is a corresponding bit of the Software Interrupt Enable IPR (SIER) that must be set to request an interrupt. Reads of the SIRR return the complete set of interrupt request registers and summary bits. All interrupt requests are blocked while executing in PALmode.


KN7AA Asynchronous Trap Request Register

Mnemonic:	ASTRR

Click in a field or on its name for the description.

The ASTRR IPR contains bits to request AST interrupts in each of the processor modes. To generate an AST interrupt, the corresponding enable bit in the ASTER IPR must be set. Also, the processor must be in the selected processor mode or higher privilege as described by the current value of the PS CM bits. AST interrupts are enabled if SIER[2] is asserted. This provides a mechanism to lock out AST requests over certain IPL levels.

All interrupt requests are blocked while executing in PALmode. Reads of the ASTRR IPR return the complete set of interrupt request registers and summary bits.


KN7AA Hardware Interrupt Enable Register

Mnemonic:	HIER

Click in a field or on its name for the description.

The HIER IPR is used to enable corresponding bits of the HIRR requesting interrupt. The PC0, PC1, SLE, and CRE bits of this register enable:

1	Performance counter interrupts

2	Serial line interrupts

3	Correctable read error interrupts

There is a one-to-one correspondence between the interrupt requests and enable bits. As with the reads of the interrupt request registers, reads of the HIER IPR return the complete set of interrupt enable registers.


KN7AA Software Interrupt Enable Register

Mnemonic:	SIER

Click in a field or on its name for the description.

The SIER IPR is used to enable corresponding bits of the SIRR request interrupts. There is a one-to-one correspondence between the interrupt requests and enable bits. As with the reads of the interrupt request registers, reads of the SIER return the complete set of interrupt enable registers.


KN7AA AST Interrupt Enable Register

Mnemonic:	ASTER

Click in a field or on its name for the description.

The ASTER IPR is used to enable corresponding bits of the ASTRR requesting interrupts. There is a one-to-one correspondence between the interrupt requests and enable bits. As with the reads of the interrupt request registers, reads of the ASTER return the complete set of interrupt enable registers.


KN7AA Serial Line Interrupt Clear Register

Mnemonic:	SL_CLR

Click in a field or on its name for the description.

The SL_CLR IPR is a write-only register that clears:

1	Serial line interrupt requests

2	Performance counter interrupt requests

3	CRD interrupt requests.

The indicated bit must be written with a zero to clear the selected interrupt source.


KN7AA Serial Line Transmit Register

Mnemonic:	SL_XMIT
The SL_XMIT IPR contains a single write-only bit. This bit is used with the interrupt control registers, the sRomD_h signal, and the sRomClk_h signal to provide an on-chip serial line function. The TMT bit isfunctionally connected to the sRomClk_h signal after the I-cache is loaded from the external SROM. Writing the TMT bit can be used to transmit data off chip, one bit at a time, under a software timing loop.


KN7AA Translation Buffer Control Register

Mnemonic:	TB_CTL

Click in a field or on its name for the description.

The TB_CTL IPR controls the granularity of the translation buffer.


KN7AA Data Translation Buffer PTE Register

Mnemonic:	DTB_PTE
The DTB_PTE IPR represents the 32-entry DTB. The entry to be written is chosen by a not-last-used (NLU) algorithm implemented in the hardware. Writes to the DTB_PTE IPR use the memory format bit positions as described in the Alpha Architecture Reference Manual, with the exception that some fields are ignored. The valid bit is not represented in hardware.

Refer to Chapter 11 (OpenVMS AXP System Support) or Chapter 12 (DEC OSF/1 System Support) of the KN7AA CPU Technical Manual for the bit definitions of the PTE.


KN7AA Data Translation Buffer PTE_TEMP Register

Mnemonic:	DTB_PTE_TEMP
The DTB_PTE_TEMP IPR is a holding register for the DTB_PTE read data. Reads of the DTB_PTE require two instructions to return the data to the register file. The two instructions are as follows:

1	Read the DTB_PTE register data to the DTB_PTE_TEMP.

2	Read the DTB_PTE_TEMP register data to the integer register file.

The ITB_PTE_TEMP IPR is updated on all ITB accesses, both read and write. A read of the ITB_PTE to the ITB_PTE_TEMP should be followed closely by a read of the ITB_PTE_TEMP to the register file.

Refer to Chapter 11 (OpenVMS AXP System Support) or Chapter 12 (DEC OSF/1 System Support) of the KN7AA CPU Technical Manual for the bit definitions of the PTE.


KN7AA Memory Management CSR Register

Mnemonic:	MMCSR

Click in a field or on its name for the description.

The MMCSR IPR saves information about D-stream faults. The VA and MMCSR IPRs are locked against further updates until the software reads the VA. PALcode must explicitly unlock this register whenever its entry point is higher in priority than a DTB miss. The MMCSR bits are only modified by the hardware when the register is not locked, and a memory management error or a DTB miss occurs. The MMCSR IPR is unlocked after reset.


KN7AA Bus Interface Unit Address Register

Mnemonic:	BIU_ADDR

Click in a field or on its name for the description.

The BIU_ADDR IPR contains the physical address associated with errors reported by BIU_STAT<7:0>. Its contents are meaningful only when one of BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR are set. Reads of the BIU_ADDR register unlock both BIU_ADDR and BIU_STAT<7:0>.


KN7AA Bus Interface Unit Status Register

Mnemonic:	BIU_STAT

Click in a field or on its name for the description.

Bits <6:0> of the BIU_STAT IPR are locked against further updates when one of the following bits is set:

•	BIU_HERR

•	BIU_SERR

•	BC_TPERR

•	BC_TCPERR

The address associated with the error is latched and locked in the BIU_ADDR IPR. BIU_STAT<7:0> and BIU_ADDR are unlocked when the BIU_ADDR register is read. When FILL_ECC or FILL_DPERR is set, BIU_STAT<13:8> are locked against further updates. The address associated with the error is latched and locked in the FILL_ADDR IPR. BIU_STAT<14:8> and FILL_ADDR are unlocked when the FILL_ADDR IPR is read.

This register is not unlocked or cleared by reset and needs to be explicitly cleared by PALcode.


KN7AA Data Cache Status Register

Mnemonic:	DC_STAT

Click in a field or on its name for the description.

The DC_STAT IPR is intended for use by diagnostics. For chip revision less than 3, PALcode must first issue the following instruction before issuing the load or store whose D-cache lookup result is to be recorded into DC_HIT: HW_MTPR R31, 4B (hex). For pass 3 chips, software need not execute the HW_MTPR instruction before using DC_STAT. Also, the field marked Unpredictable reads zero in the pass 3 chips.


KN7AA Fill Address Register

Mnemonic:	FILL_ADDR

Click in a field or on its name for the description.

The FILL_ADDR IPR stores the physical address associated with errors reported by BIU_STAT<14:8>. The contents of this IPR are meaningful only when FILL_ECC or FILL_DPERR is set. Reads of the FILL_ADDR unlock FILL_ADDR, BIU_STAT<14:8>, and FILL_SYNDROME.


KN7AA Control Register

Mnemonic:	ABOX_CTL

Click in a field or on its name for the description.

The ABX_CTL IPR controls the Abox functions. PALcode writes to this register at initialization and keeps an image of the register which appears in error log entries and is readable by the user.


KN7AA Alternate Processor Mode Register

Mnemonic:	ALT_MODE

Click in a field or on its name for the description.

The ALT_MODE IPR stores information that specifies the alternate processor mode.


KN7AA Cycle Counter Register

Mnemonic:	CC
The DECchip 21064 supports a cycle counter, as described in the Alpha Architecture Reference Manual. When enabled, the CC IPR increments once each CPU cycle. The HW_MTPR Rn, CC writes the CC<63:32> with the value held in the Rn<63:32>; bits <31:0> are not changed.

This IPR is read by the RPCC instruction and is written to by the HW_MTPR Rn, CC instruction as defined in the Alpha Architecture Reference Manual.


KN7AA Cycle Counter Control Register

Mnemonic:	CC_CTL
The CC_CTL IPR is used to write to the CC IPR. The HW_MTPR Rn, CC_CTL instruction writes the CC<31:0> with the value held in Rn <31:0>; bits <63:32> bits are not changed. The CC<3:0> must be written with zero. If Rn<32> is set, then the counter is enabled; otherwise, the counter is disabled.


KN7AA Bus Interface Unit Control Register

Mnemonic:	BIU_CTL

Click in a field or on its name for the description.

The BIU_CTL IPR is a write-only register that controls the operating parameters of the BIU interface and the B-cache. PALcode writes to this register atinitialization and keeps an image of the register which appears in error log entries and is readable by the user.


KN7AA Fill Syndrome Register

Mnemonic:	FILL_SYND

Click in a field or on its name for the description.

The FILL_SYND IPR stores the syndrome bits. If the DECchip 21064 is in ECC mode and an ECC error is recognized during a P-cache fill operation, the syndrome bits associated with the bad quadword are locked in the FILL_SYND IPR. A syndrome value of zero means that no errors were found in the associated longword. The FILL_SYND IPR is unlocked when the FILL_ADDR IPR is read. Table 1-28 lists the syndromes associated with correctable single-bit errors.

If the processor is in parity mode and a parity error is recognized during a P-cache fill operation, the FILL_SYND IPR indicates which of the longwords in the quadword got bad parity.

See Syndromes for Single-Bit Errors.


KN7AA B-Cache Tag Register

Mnemonic:	BC_TAG

Click in a field or on its name for the description.

The BC_TAG IPR is loaded with the results of every B-cache tag probe, unless locked. When a tag, tag control parity, or primary fill data error (parity or ECC) occurs, BC_TAG is locked against further updates. PALcode may read the LSB of this register by using the HW_MFPR instruction. Each time an HW_MFPR from BC_TAG completes, the contents of BC_TAG are shifted one bit position to the right, so that the entire register can be read using a requence of HW_MRPRs. PALcode can unlock the BC_TAG with an HW_MTPR to BC_TAG. Successive HW_MFPRs from the BC_TAG must be separated by at least one null cycle.


KN7AA Console Registers

How to examine these registers

Register	Address	Access
Gbus$WHAMI	3 F700 0000	RO
Gbus$LEDs	3 F700 0040	R/W
Gbus$PMask	3 F700 0080	R/W
Gbus$Intr	3 F700 00C0	R/W
Gbus$Halt	3 F700 0100	R/W
Gbus$LSBRST	3 F700 0140	R/W
Gbus$Misc	3 F700 0180	R/W
Gbus$RMode	3 F780 0000	R/W
Gbus$LTagRW	3 F780 0100	R/W


Gbus$WHAMI Register

Address:	3 F700 0000
Access:	RO

Click in a field or on its name for the description.

The Gbus$WHAMI register provides information on system configuration and reflects the status of certain backplane signals.


Gbus$LEDs Register

Address:	3 F700 0040
Access:	R/W

Click in a field or on its name for the description.

The Gbus$LEDs register is used for lighting a series of LEDs on the module to aid in debug and to indicate self-test status. Writing a zero to a bit in this register lights the corresponding LED.


Gbus$PMask Register

Address:	3 F700 0080
Access:	R/W

Click in a field or on its name for the description.

The Gbus$PMask register controls halts to the processor.


Gbus$Intr Register

Address:	3 F700 00C0
Access:	R/W

Click in a field or on its name for the description.

The Gbus$Intr register stores interrupt summary information. Specifically, it provides a means to determine the source of IPL 14, IPL 15, and IPL 16 interrupts to the processor.


Gbus$Halt Register

Address:	3 F700 0100
Access:	R/W

Click in a field or on its name for the description.

The Gbus$Halt register summarizes halt and power conditions.


Gbus$LSBRST Register

Address:	3 F700 0140
Access:	R/W

The Gbus$LSBRST register is used for initiating a system reset sequence. When the CPU chip writes any value to this register, the LSB RESET signal is asserted for 512 LSB cycles.


Gbus$Misc Register

Address:	3 F700 0180
Access:	R/W

Click in a field or on its name for the description.

The Gbus$Misc register controls various system functions.


Gbus$RMode Register

Address:	3 F780 0000
Access:	R/W

The Gbus$RMode register is a write-only register. A write to it sets LDIAG<FRIGN> and logically disconnects the CPU module from the LSB bus. This register is intended for use as a backup system should there be a problem with the LSB interface and writes to the LDIAG register be unsuccessful (writes to the LDIAG register require a successful LSB transaction while writes to Gbus space are completed without any LSB access). Note that software should write to the LDIAG register as a first choice and use the Gbus$RMode register only if the write to the LDIAG register fails.


Gbus$LTagRW Register

Address:	3 F780 0100
Access:	R/W

The Gbus$LTagRW register, when used with LTAGA, LTAGW, and LDIAG registers, allows software to read and write the B-cache, B-map, and P-map tags. See descriptions of the LTAGA, LTAGW, and LDIAG registers in Chapter .


MS7AA Registers

How to examine these registers

Mnemonic	Register Name	Offset
LDEV	Device	BB + 0000
LBER	Bus Error	BB + 0040
LCNR	Configuration	BB + 0080
IBR	Information Base Repair	BB + 00C0
LBESR0	Bus Error Syndrome 0	BB + 0600
LBESR1	Bus Error Syndrome 1	BB + 0640
LBESR2	Bus Error Syndrome 2	BB + 0680
LBESR3	Bus Error Syndrome 3	BB + 06C0
LBECR0	Bus Error Command 0	BB + 0700
LBECR1	Bus Error Command 1	BB + 0740
MCR	Memory Configuration	BB + 2000
AMR	Address Mapping	BB + 2040
MSTR0	Memory Self-Test 0	BB + 2080
MSTR1	Memory Self-Test 1	BB + 20C0
FADR	Failing Address	BB + 2100
MERA	Memory Error A	BB + 2140
MSYNDA	Memory Syndrome A	BB + 2180
MDRA	Memory Diagnostic A	BB + 21C0
MCBSA	Memory Check Bit Substitute A	BB + 2200
MERB	Memory Error B	BB + 4140
MSYNDB	Memory Syndrome B	BB + 4180
MDRB	Memory Diagnostic B	BB + 41C0
MCBSB	Memory Check Bit Substitute B	BB + 4200


BB

BB is the LSB node space base address (in hex) of the memory module.

If the module  is in this slot	BB is
0	3 F800 0000
1	3 F840 0000
2	3 F880 0000
3	3 F8C0 0000
4	3 F900 0000
5	3 F940 0000
6	3 F980 0000
7	3 F9C0 0000


MS7AA Device Register

Mnemonic:	LDEV
Offset:	BB + 0000

Click in a field or on its name for the description.

The LDEV register is loaded during initialization with information that identifies a node.


MS7AA Bus Error Register

Mnemonic:	LBER
Offset:	BB+ 0040

Click in a field or on its name for the description.

The LBER register stores the error bits that are flagged in memory operations and logs the failing commander ID. The status of this register remains locked until software resets the error bit(s).


MS7AA Configuration Register

Mnemonic:	LCNR
Offset:	BB + 0080

Click in a field or on its name for the description.

The LCNR register contains LSB systemwide configuration setup and status information.


MS7AA Information Base Repair Register

Mnemonic:	IBR
Offset:	BB + 00C0

Click in a field or on its name for the description.

The IBR register is used to access the EEPROM on the LSB memory and I/O modules. The EEPROM access is accomplished through continual updates of this register by software.


MS7AA Bus Error Syndrome Registers 0--3

Mnemonic:	LBESR0--3
Offset:	BB + 0600
	BB + 06C0

Click in a field or on its name for the description.

The LBESR registers contain the syndrome computed from data received on the LSB D and ECC fields during the cycle when an error was detected. These registers are locked upon the first ECC detected error and remain locked until all LSB ECC error bits in LBER are cleared.


MS7AA Bus Error Command Registers 0--1

Mnemonic:	LBECR0-1
Offset:	BB + 0700, BB + 0740

Click in a field or on its name for the description.

The LBECR registers hold the contents of the LSB command and address fields for the operation during which an error was detected.


MS7AA Memory Configuration Register

Mnemonic:	MCR
Offset:	BB + 2000

Click in a field or on its name for the description.

The MCR register provides information about the DRAM array. It is accessed by console software to determine module capacity, that is, the DRAM type (4-Mbit or 16-Mbit) and number of strings installed. This information is necessary to set up the eight AMR registers in each LSB commander node and the AMR register located on each memory module at BB+2040.


MS7AA Address Mapping Register

Mnemonic:	AMR
Offset:	BB + 2040

Click in a field or on its name for the description.

The AMR register is used with the LSB memory address issued during a command/address cycle to select a memory module, a bank within a module, and adjust the address on memory modules based upon the interleave level selected, the number of strings, and the DRAM type.

This register is a single copy of the eight mapping registers that CPU modules and the IOP module must implement. When the console in the primary CPU configures memory, it determines the slots occupied by the memory modules and loads the slot number of each memory module in the AMR register of the module. Copies of the AMR registers are written into the corresponding mapping registers on all CPU nodes and the IOP node. The AMR contents for nodes 0 to 7 are placed into LMMR0-7 registers. If a module is not present in a memory slot, the console writes a zero to bit <0> (Enable) of the corresponding LMMR register.


MS7AA Memory Self-Test Registers 0--1

Mnemonic:	MSTR0-1
Offset:	BB + 2080, BB + 20C0

Click in a field or on its name for the description.

The MSTR registers are used to isolate self-test failures to a given address segment or segments (if multiple failures) within a module. The two registers combined break up a memory module into 64 distinct address segments. Each segment resides in a range of addresses that are sized according to the selected DRAM component (4 Mbits or 16 Mbits).


MS7AA Failing Address Register

Mnemonic:	FADR
Offset:	BB + 2100

Click in a field or on its name for the description.

The FADR register contains the failing 32-bit LSB address any time the 64-bit ECC logic detects an ECC error during memory reads. This register is locked upon either a correctable or uncorrectable ECC error.

NOTE: The FADR register does not capture the entire LSB address. It drops address bits D<34:32>.


MS7AA Memory Error Register A

Mnemonic:	MERA
Offset:	BB + 2140

Click in a field or on its name for the description.

The MERA register provides additional error information about node-specific error conditions that are captured in the MIC-A. This register includes two bits that, when set, indicate the occurrence of an error on the MIC-B.


MS7AA Memory Syndrome Register A

Mnemonic:	MSYNDA
Offset:	BB + 2180

Click in a field or on its name for the description.

The MSYNDA register is used to determine which bit is in error when a correctable ECC error is detected by the module during an LSB memory read transaction. This register contains the syndrome bits generated by memory's 64-bit ECC logic protecting D<63:0>. The error syndrome is decoded by software to the bit in error so that it can be logged accordingly. This register is locked when either a correctable read error bit (CER) or an uncorrectable read error bit (UCER) is set in the MERA register. MSYNDA is unlocked when the error bit or bits are cleared in the MERA register. If this register is already locked with the failing syndrome of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the uncorrectable error syndrome.


MS7AA Memory Diagnostic Register A

Mnemonic:	MDRA
Offset:	BB + 21C0

Click in a field or on its name for the description.

The MDRA register is used by diagnostics to help isolate failures and to force specific error conditions within the module and the MIC-A chip. When MDRA is written, MDRB<7:0> are written concurrently. This feature allows syncronization of diagnostic operations between MIC-A and MIC-B. Bits<7:0> of MDRA and MDRB registers have one-to-one matching functions.

NOTE: This register is reserved for Digital use.


MS7AA Memory Check Bit Substitute Register A

Mnemonic:	MCBSA
Offset:	BB + 2200

Click in a field or on its name for the description.

The MCBSA register is used to check the 64-bit ECC logic on the memory module during memory read transactions. This register is first loaded by diagnostics with substitute bits for DRAM check bits. The contents of the MCBSA register is then written to a selected memory location. When the write transaction is complete, each of the four octawords contains the substituted check bits and data issued on the bus. The location in memory written with substitute check bits will contain an UNDEFINED ECC code. Software executing such tests must ensure that memory is initialized to good ECC by reexecuting self-test or by other means.


MS7AA Memory Error Register B

Mnemonic:	MERB
Offset:	BB + 4140

Click in a field or on its name for the description.

The MERB register provides additional error information about node-specific error conditions that are captured in the MIC-B chip.


MS7AA Memory Syndrome Register B

Mnemonic:	MSYNDB
Offset:	BB + 4180

Click in a field or on its name for the description.

The MSYNDB register is used to determine which bit is in error when a correctable ECC error is detected by the module during an LSB memory read transaction. This register contains the syndrome bits generated by memory's 64-bit ECC logic protecting D<63:0>. The error syndrome is decoded by software to the bit in error so that it can be logged accordingly. This register is locked when either a correctable read error bit (CER) or an uncorrectable read error bit (UCER) is set in the MERB register. MSYNDB is unlocked when the error bit or bits are cleared in the MERB register. If this register is already locked with the failing syndrome of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the uncorrectable error syndrome.


MS7AA Memory Diagnostic Register B

Mnemonic:	MDRB
Offset:	BB + 41C0

Click in a field or on its name for the description.

The MDRB register is used by diagnostics to help isolate failures and to force specific error conditions within the module and the MIC-B chip. When the MDRA register is written, MDRB<7:0> are written concurrently. This feature allows syncronization of diagnostic operations between MIC-A and MIC-B. Bits<7:0> of MDRA and MDRB registers have one to one matching functions.

NOTE: This register is reserved for Digital use.


MS7AA Memory Check Bit Substitute Register B

Mnemonic:	MCBSB
Offset:	BB + 4200

Click in a field or on its name for the description.

The MCBSB register is used to check the 64-bit ECC logic on the memory module during memory read transactions. This register is first loaded by diagnostics with substitute bits for DRAM check bits. The contents of the MCBSB register is then written to a selected memory location. When the write transaction is complete, each of the four octawords contains the substituted check bits and data issued on the bus. The location in memory written with substitute check bits will contain an UNDEFINED ECC code. Software executing such tests must ensure that memory is initialized to good ECC by reexecuting self-test or by other means.


I/O Port Registers

How to examine these registers

Mnemonic	Register Name	Offset	Access
LDEV	Device	BB + 0000	R/W
LBER	Bus Error	BB + 0040	R/W
LCNR	Configuration	BB + 0080	R/W
IBR	Information Base Repair	BB + 00C0	R/W
LMMR0	Memory Mapping 0	BB + 0200	R/W
LMMR1	Memory Mapping 1	BB + 0240	R/W
LMMR2	Memory Mapping 2	BB + 0280	R/W
LMMR3	Memory Mapping 3	BB + 02C0	R/W
LMMR4	Memory Mapping 4	BB + 0300	R/W
LMMR5	Memory Mapping 5	BB + 0340	R/W
LMMR6	Memory Mapping 6	BB + 0380	R/W
LMMR7	Memory Mapping 7	BB + 03C0	R/W
LBESR0	Bus Error Syndrome 0	BB + 0600	RO
LBESR1	Bus Error Syndrome 1	BB + 0640	RO
LBESR2	Bus Error Syndrome 2	BB + 0680	RO
LBESR3	Bus Error Syndrome 3	BB + 06C0	RO
LBECR0	Bus Error Command 0	BB + 0700	RO
LBECR1	Bus Error Command 1	BB + 0740	RO
LILID0	Interrupt Level 0 IDENT	BB + 0A00	RTC
LILID1	Interrupt Level 1 IDENT	BB + 0A40	RTC
LILID2	Interrupt Level 2 IDENT	BB + 0A80	RTC
LILID3	Interrupt Level 3 IDENT	BB + 0AC0	RTC
LCPUMASK	CPU Interrupt Mask	BB + 0B00	R/W
LMBPR0	Mailbox Pointer 0	BB + 0C00	R/W
LMBPR1	Mailbox Pointer 1	BB + 0C00	R/W
LMBPR2	Mailbox Pointer 2	BB + 0C00	R/W
LMBPR3	Mailbox Pointer 3	BB + 0C00	R/W
IPCNSE	I/O Port Chip Node-Specific Error	BB + 2000	R/W
IPCVR	I/O Port Chip Vector	BB + 2040	R/W
IPCMSR	I/O Port Chip Mode Selection	BB + 2080	R/W
IPCHST	I/O Port Chip Hose Status	BB + 20C0	R/W
IPCDR	I/O Port Chip Diagnostic	BB + 2100	R/W


BB

BB is the LSB node space base address (in hex) of the IOP module. The IOP module is node 8; BB is 3 FA00 0000.


IOP Device Register

Mnemonic:	LDEV
Offset:	BB + 0000
Access:	R/W

Click in a field or on its name for the description.

The LDEV register is loaded during initialization with information that identifies a node.


IOP Bus Error Register

Mnemonic:	LBER
Offset:	BB + 0040
Access:	R/W

Click in a field or on its name for the description.

The LBER register stores the error bits that are flagged when an LSB node detects errors and logs the failing commander ID. The status of this register remains locked until software resets the error bit(s).


IOP Configuration Register

Mnemonic:	LCNR
Offset:	BB + 0080
Access:	R/W

Click in a field or on its name for the description.

The LCNR register contains LSB systemwide configuration setup and status information.


IOP Information Base Repair Register

Mnemonic:	IBR
Offset:	BB + 00C0
Access:	R/W

Click in a field or on its name for the description.

The IBR register is used to access the SEEPROM located on the IOP module. Access of the SEEPROM is made by repeated access to this register. Writing an alternating one and zero pattern to the SCLK bit implements the serial data clock used for the SEEPROM protocol. Command, address, and write data are serially transferred to the SEEPROM by writing to the XMT_SDAT bit and clocked by the SCLK bit. SEEPROM read data and response are read serially from the RCV_SDAT bit and clocked in by the SCLK bit. When receiving SEEPROM read data and responses, XMT_SDAT must be one.


IOP Memory Mapping Registers 0-7
IOP Memory Mapping Registers 0--7

Mnemonic:	LMMR0--7
Offset:	BB + 0200 -- BB + 03C0
Access:	R/W

Click in a field or on its name for the description.

Eight LMMR registers define the configuration for all memory modules installed in the system. They are copies of the equivalent AMR registers in the memory modules. Each LMMR register is associated with the LSB module whose node ID matches the three least significant bits of the LMMR address. Thus, LMMR0 is associated with node 0, LMMR1 is associated with node 1, and so on. LMMR registers are loaded during system initialization when the memory modules are initialized and configured.


IOP Bus Error Syndrome Registers 0-3
IOP Bus Error Syndrome Registers 0--3

Mnemonic:	LBESR0--3
Offset:	BB + 0600 -- BB + 06C0
Access:	RO

Click in a field or on its name for the description.

The LBESR registers contain the syndrome computed from the LSB Data and ECC fields received during the cycle when an error was detected. The syndrome is the bit-by-bit difference between the ECC check code generated from the received data and the ECC field received over the bus. The LBESR registers lock only on the first occurrence of an ECC error (LBER<CE> or LBER<UCE>). Subsequent ECC errors set LBER<CE2> or LBER<UCE2> until software clears those error bits.


IOP Bus Error Command Registers 0-1
IOP Bus Error Command Registers 0--1

Mnemonic:	LBECR0--1
Offset:	BB + 0700, BB + 0740
Access:	RO

Click in a field or on its name for the description.

The LBECR registers save the contents of the LSB command and address fields during the command cycle when an error is detected. The following errors lock the LBECR registers:

•	LSB uncorrectable ECC error (LBER<1>)

•	LSB correctable ECC error (LBER<3>)

•	LSB command parity error (LBER<5>)

•	LSB CSR data parity error (LBER<7>)

•	LSB nonexistent address error (LBER<12>)

•	LSB arbitration drop error (LMERR<10>

•	LEVI P-map parity error (LMERR<3:0>)

•	LEVI B-cache tag parity error (LMERR<4>)

•	LEVI B-cache status parity error (LMERR<5>)

•	LEVI B-map parity error (LMERR<6>)


IOP Interrupt Level 0-3 IDENT Registers
IOP Interrupt Level 0--3 IDENT Registers

Mnemonic:	LILID0--3
Offset:	BB + 0A00 -- BB + 0AC0
Access:	RTC

Click in a field or on its name for the description.

Each of the four registers contains a four-deep queue (one entry per hose) of the interrupts for that IPL. A read to this register sends the "oldest" interrupt IDENT information to the CPU that requests it. The "next oldest" interrupt IDENT information can then be read at that address. When no active interrupts exist at a given level, reads of the corresponding LILIDn register return zeros.


IOP CPU Interrupt Mask Register

Mnemonic:	LCPUMASK
Offset:	BB + 0B00
Access:

Click in a field or on its name for the description.

The LCPUMASK register is used to determine which CPU is to service a given level of interrupts. A logical AND of the interrupt level posted from the I/O subsystem and this register form the write data sent from the IOP to the LIOINTR register in the CPU.


IOP Mailbox Pointer Registers 0-3
IOP Mailbox Pointer Registers 0--3

Mnemonic:	LMBPR0--3
Offset:	BB + 0C00
Access:	R/W

Click in a field or on its name for the description.

To access remote I/O registers, software loads the LMBPR with the 64-byte aligned physical address of the mailbox data structure in main memory. When this register is loaded, the IOP uses the address to fetch information contained in the mailbox data structure in memory.

The I/O system architecture requires a single software address for the LMBPR. The IOP, however, implements four LMBPR registers, each of which represents a two-deep queue. Therefore, up to eight mailbox transactions can be outstanding at any given time since the IOP processes only one transaction at a time. A NO ACK is returned on LMBPR register writes to a full queue. Each CPU transforms the single software address of the LMBPR (A00 0C00) during the command cycle by adding the CPU node ID on D<2:1> so that its designated LMBPR on the IOP is accessed. Note that the high-order bit of the node ID is ignored. Therefore, CPUs at node 0 and 4 share the same LMBPR as do CPUs at node 1 and 5, and CPUs at node 2 and 6, and CPUs at node 3 and 7.


I/O Port Chip Node-Specific Error Register

Mnemonic:	IPCNSE
Offset:	BB + 2000
Access:	R/W

Click in a field or on its name for the description.

The IPCNSE register is used to record errors relating to the internal operation of the IOP module and Up Hose transactions.

All Vortex errors put the IOP into an unpredictable state. The IOP should be reset using Node_Reset in the LCNR register after such errors.


I/O Port Chip Vector Register

Mnemonic:	IPCVR
Offset:	BB + 2040
Access:	R/W

Click in a field or on its name for the description.

This register is loaded by software with the vector pointing to the IOP error handler.


I/O Port Chip Mode Selection Register

Mnemonic:	IPCMSR
Offset:	BB + 2080
Access:	R/W

Click in a field or on its name for the description.

The IPCMSR register is used to select the "back-off" mode arbitration algorithm for the IOP module. The two-bit arbitration control field controls the number of requests the IOP makes on the LSB at high priority before switching to low priority. Memory bank lockout is prevented by the "back-off" algorithm.


I/O Port Chip Hose Status Register

Mnemonic:	IPCHST
Offset:	BB + 20C0
Access:	R/W

Click in a field or on its name for the description.

The IPCHST register contains status information for each hose.


I/O Port Chip Diagnostic Register

Mnemonic:	IPCDR
Offset:	BB + 2100
Access:	R/W

Click in a field or on its name for the description.

The IPCDR register is used to force errors: errors on the LSB bus, errors on the Vortex buses, and errors on the hoses using the loopback function. LSB bus errors generated by use of this register are detected by the IOP when the signals are received and are also detected by all other nodes monitoring the LSB.


DWLMA Registers

The DWLMA is the interface from the LSB to the XMI. The module designation is T2028-AA; it is in slot 8 of the XMI card cage.

How to examine these registers

Mnemonic	Register Name	Offset	Access

XMI Required Registers

XDEV	Device	BB + 00	R/W
XBER	Bus Error	BB + 04	R/W
XFADR	Failing Address	BB + 08	RO
XFAER	Failing Address Extension	BB + 0C	RO
IBR	Information Base Repair	BB + 10	R/W

Node-Specific Registers

LDIAG	Diagnostic	BB + 40	R/W
IMSK	Interrupt Mask	BB + 44	R/W
LEVR	Error Vector	BB + 48	R/W
LERR	Error	BB + 4C	R/W
LGPR	General Purpose	BB + 50	R/W
IPR1	Interrupt Pending 1	BB + 54	RO
IPR2	Interrupt Pending 2	BB + 58	RO
IIPR	Interrupt in Progress	BB + 5C	RO


BB

BB is the XMI mailbox base physical address (in hex) of the DWLMA module. The DWLMA module is node 8; BB is 61C0 0000.


DWLMA Device Register

Mnemonic:	XDEV
Offset:	BB + 00
Access:	R/W

Click in a field or on its name for the description.

The XDEV register contains information to identify the node. The DREV and the Device Type fields are coded on the DWLMA. The LGA revision is coded in the LGA.

NOTE: The contents of this register are returned when either an offset of 00 or 20 is added to the bb.


DWLMA Bus Error Register

Mnemonic:	XBER
Offset:	BB + 04
Access:	R/W

Click in a field or on its name for the description.

XBER contains error status on a failed XMI transaction. This status includes the failed commander ID and an error bit that indicates the type of error that occurred. This status remains locked until software clears the error bits.

Bit <1> is used to enable the More protocol.


DWLMA Failing Address Register

Mnemonic:	XFADR
Offset:	BB + 08
Access:	RO

Click in a field or on its name for the description.

This register and XFAER are used to log command, mask, address, and length information associated with a failing transaction. XFADR and XFAER are locked on the first commander error. Commander errors are specified as bits XBER<20,18:13>. The DWLMA latches the address and length upon the first error set in XBER. The registers are free to latch new information once the error bit in XBER is cleared. If there are no errors, they contain the command, mask, address, and length of the last XMI transaction issued.


DWLMA Failing Address Extension Register

Mnemonic:	XFAER
Offset:	BB + 0C
Access:	RO

Click in a field or on its name for the description.

XFAER logs command, address, and write mask information associated with a failing transaction. XFAER is the higher 32 bits of a 64-bit register formed by concatenating XFADR and XFAER, thus logging the XMI D<63:32> during the command cycle. XFADR and XFAER lock when commander error bits set (XBER bits 20, 18:13).


DWLMA Information Base Repair Register

Mnemonic:	IBR
Offset:	BB + 10
Access:	R/W

Click in a field or on its name for the description.

The IBR register is used to access the SEEPROM located on the DWLMA module. To access SEEPROM, sequential reads or writes of this register are done by software.


DWLMA Diagnostic Register

Mnemonic:	LDIAG
Offset:	BB + 40
Access:	R/W

Click in a field or on its name for the description.

LDIAG is used to supply the node ID and other XMI status bits and to force certain conditions used for diagnostic purposes.


DWLMA Interrupt Mask Register

Mnemonic:	IMSK
Offset:	BB + 44
Access:	R/W

Click in a field or on its name for the description.

The IMSK register is used to enable the DWLMA to interrupt a CPU on the LSB bus when a corresponding error bit is set in XBER or LERR. Seting a particular bit enables the interrupt.


DWLMA Error Vector Register

Mnemonic:	LEVR
Offset:	BB + 48
Access:	R/W

Click in a field or on its name for the description.

LEVR contains the interrupt vector for DWLMA-generated interrupts. The DWLMA generates error interrupts at IPL 17.


DWLMA Error Register

Mnemonic:	LERR
Offset:	BB + R/W
Access:	R/W

Click in a field or on its name for the description.

LERR contains errors specific to the DWLMA adapter. This register must be cleared before XBER is cleared.


DWLMA General Purpose Register

Mnemonic:	LGPR
Offset:	BB + 50
Access:	R/W

Click in a field or on its name for the description.

This general purpose, read/write register is used during DMA read loopback testing as a temporary storage location. If the LOOP bit is set in the DIAG register, a Mailbox Read command is converted to a DMA Read command and issued on the XMI. When the DMA read data is returned on the Down Hose, the DWLMA places the first longword of the last quadword of the DMA read data in the LGPR. Diagnostics clear this register.


DWLMA Interrupt Pending Register 1

Mnemonic:	IPR1
Offset:	BB + 54
Access:	RO

Click in a field or on its name for the description.

IPR1 provides interrupt-pending information at each IPL for XMI nodes 1 through 8. A pending bit is set in this register for every interrupt that is waiting for an interrupt at the same IPL to finish. The pending bit is cleared when the interrupt is in progress.


DWLMA Interrupt Pending Register 2

Mnemonic:	IPR2
Offset:	BB + 58
Access:	RO

Click in a field or on its name for the description.

IPR2 provides interrupt-pending information at each IPL for XMI nodes 9 through 14 and for the DWLMA error interrupt-pending bit. A pending bit is set in this register for every interrupt that is waiting for an interrupt at the same IPL to finish. The pending bit is cleared when the interrupt is in progress.


DWLMA Interrupt in Progress Register

Mnemonic:	IIPR
Offset:	BB + 5C
Access:	RO

Click in a field or on its name for the description.

IIPR contains the node ID of each interrupt in progress for each IPL. It also contains the command node ID of any IDENT in progress. An XMI interrupt is in progress from the time the DWLMA issues the IDENT to the interrupting node, until the INTR/IDENT Return Status packet is received from the IOP. The current IDENT in progress field contains the node ID of the XMI I/O device to which the DWLMA has issued an IDENT to obtain the IDENT vector.


DWLAA Registers

The DWLAA is the interface from the LSB to the Futurebus+. The module designation is B2003-AA; it is in slot 5 of the Futurebus+ card cage.

How to examine these registers

Mnemonic	Register Name	Offset	Access
FINT	Interrupt	BB + 000	R/W
NID	Node Identification	BB + 004	R/W
STO	Split Timeout	BB + 008	R/W
ERRHI	Error High	BB + 00C	R/W
ERRLO	Error Low	BB + 010	R/W
FADRHI	Failing Address High	BB + 014	RO
FADRLO	Failing Address Low	BB + 018	RO
TTO	Transaction Timeout	BB + 01C	R/W
BZRTRY	Busy Retry	BB + 020	R/W
FCTL	Control	BB + 024	R/W
DIAG	Diagnostic Control	BB + 028	R/W
FGPR	General Purpose	BB + 02C	R/W
FERR	Error	BB + 030	R/W
IBR	Information Base Repair	BB + 034	R/W
DID	Device Identification	None	RO
INT14	IPL14 Vector	BB + 800	RO
INT15	IPL15 Vector	BB + 804	RO
INT16	IPL16 Vector	BB + 808	RO
INT17	IPL17 Vector	BB + 80C	RO


BB

BB is the Futurebus+ node space base address (in hex) of the DWLAA module. The DWLAA module is node 5; BB is FFFC A000.


No Offset

The Device Identification Register does not have an offset. It is read via the WRU mailbox.


DWLAA Interrupt Register

Mnemonic:	FINT
Offset:	BB + 000
Access:	R/W

Click in a field or on its name for the description.

The FINT register contains the vector pointing to the error interrupt service routine. The interrupt is posted at IPL 17.


DWLAA Node Identification Register

Mnemonic:	NID
Offset:	BB + 004
Access:	R/W

Click in a field or on its name for the description.

The NID register contains the address used by the DWLAA when responding to CSR reads and writes and to read responses.


DWLAA Split Timeout Register

Mnemonic:	STO
Offset:	BB + 008
Access:	R/W

Click in a field or on its name for the description.

The STO register contains a value determining the time the DWLAA waits, before timing out, after it receives a command/
address from the selected slave until it receives a read response. The default value is 16.384 ms.


DWLAA Error High Register

Mnemonic:	ERRHI
Offset:	BB + 00C
Access:	R/W

Click in a field or on its name for the description.

The ERRHI register, along with the ERRLO register, is used to log Futurebus+ errors. If ERR_SUM is zero, the register returns zeros when read.


DWLAA Error Low Register

Mnemonic:	ERRLO
Offset:	BB + 010
Access:	R/W

Click in a field or on its name for the description.

The ERRLO register records an unsolicted response error when the DWLAA is selected for a Futurebus+ transaction.


DWLAA Failing Address High Register

Mnemonic:	FADRHI
Offset:	BB + 014
Access:	RO

Click in a field or on its name for the description.

The FADRHI register latches the connect phase address of slave/selected slave transactions if the ERR_SUM bit (ERRHI<31>) is clear. If the ERR_SUM bit is set, FADRHI reflects the state of the connect phase address of the last slave/selected slave transaction if the DWLAA was master when the error occurred, or the connect phase address of the current slave/selected slave transaction if the DWLAA was not master when the error occurred.


DWLAA Failing Address Low Register

Mnemonic:	FADRLO
Offset:	BB + 018
Access:	RO

Click in a field or on its name for the description.

The FADRLO register latches the connect phase address of slave/selected slave transactions if the ERR_SUM bit (ERRHI<31>) is clear. If the ERR_SUM bit is set, FADRLO reflects the state of the connect phase address of the last slave/selected slave transaction if the DWLAA was master when the error occurred, or the connect phase address of the current slave/selected slave transaction if the DWLAA was not master when the error occurred.


DWLAA Transaction Timeout Register

Mnemonic:	TTO
Offset:	BB + 01C
Access:	R/W

Click in a field or on its name for the description.

The TTO register contains the value determining the time the master will wait for a transaction to complete before setting the TTO bit in the FERR CSR. The default is 128 ms.


DWLAA Busy Retry Register

Mnemonic:	BZRTRY
Offset:	BB + 020
Access:	R/W

Click in a field or on its name for the description.

The BZRTRY register controls how the DWLAA handles retries on the Futurebus+.


DWLAA Control Register

Mnemonic:	FCTL
Offset:	BB + 024
Access:	R/W

Click in a field or on its name for the description.

The FCTL register controls how the DWLAA responds to various conditions it detects while in operation.


DWLAA Diagnostic Control Register

Mnemonic:	DIAG
Offset:	BB + 028
Access:	R/W

Click in a field or on its name for the description.

The DIAG register is used by diagnostics to control the diagnostic tests.


DWLAA General Purpose Register

Mnemonic:	FGPR
Offset:	BB + 02C
Access:	R/W

Click in a field or on its name for the description.

This general purpose register is used for diagnostic purposes.


DWLAA Error Register

Mnemonic:	FERR
Offset:	BB + 030
Access:	R/W

Click in a field or on its name for the description.

The FERR register contains information on errors detected by the DWLAA during normal operation.


DWLAA Information Base Repair Register

Mnemonic:	IBR
Offset:	BB + 034
Access:	R/W

Click in a field or on its name for the description.

The IBR register supports access to the serial EEPROM located on the DWLAA adapter.


DWLAA Device Identification Register

Mnemonic:	DID
Offset:	None
Access:	RO

Click in a field or on its name for the description.

The DID CSR is not at an actual location, but is the format returned when the B bit is set in the Mailbox Command packet. A Who Are You (WRU) transaction overrides any other command bit sent in the Down Hose command packet.


DWLAA IPL14-17 Vector Registers
DWLAA IPL14--17 Vector Registers

Mnemonic:	INT14--17
Offset:	BB + 800 -- BB + 80C
Access:	RO

Click in a field or on its name for the description.

INT 14-17 are written with the 16-bit vector that is used in servicing I/O adapter interrupts.

ADDRESS: INT 14-17 CSRs are not actual registers but four sequential 16-bit FIFOs. These FIFOs are not visible by a mailbox transaction. They are visible from the Futurebus+ at the following addresses:

FFFC A800	IPL 14
FFFC A804	IPL 15
FFFC A808	IPL 16
FFFC A80C	IPL 17
The DWLAA does not perform byte swapping for interrupt vectors.


Addressing

These topics provide an overview of the DEC 7000 system and addressing information for the buses used in the system.

DEC 7000 System Block Diagram

LSB Address Space

Virtual Address Space Layout

LSB Node Base Addresses

Device Type Codes

XMI Addresses

XMI Node Addresses

Addresses of XMI Slots

VAXBI Addresses

Examining a VAXBI Register from the Console

Base Addresses of VAXBI Nodes

Address Offsets of VAXBI Registers

Futurebus+ Addresses


DEC 7000 System Block Diagram


Virtual Address Space Layout


LSB Node Base Addresses

Node	Module	Base Physical Address (BB)
0	Processor or memory	3 F800 0000
1	Processor or memory	3 F840 0000
2	Processor or memory	3 F880 0000
3	Processor or memory	3 F8C0 0000
4	Processor or memory	3 F900 0000
5	Processor or memory	3 F940 0000
6	Processor or memory	3 F980 0000
7	Processor or memory	3 F9C0 0000
8	IOP	3 FA00 0000
Broadcast Space Base (BSB)	--	3 FE00 0000


Device Type Codes

Device	Code (hex)

LSB

KN7AA	8001
MS7AA	4000
IOP	2000

XMI

CIXCD	0C05
DEMFA	0823
DEMNA	0C03
DWLMA	102A
DWMBB	2002
DWMVA	2002
KDM70	0C22
KFMSB	0C31
KZMSA	0C36

Futurebus+

DEFAA	2006
DWLAA	2003


DWMBB/A and DWMVA/A are the same module, T2018.


XMI Node Addresses

Node	MailboxBase Physical Address (BB)	XMI Base Physical Address (BB)
1	6188 0000	80 0188 0000
2	6190 0000	80 0190 0000
3	6198 0000	80 0198 0000
4	61A0 0000	80 01A0 0000
5	61A8 0000	80 01A8 0000
6	61B0 0000	80 01B0 0000
7	61B8 0000	80 01B8 0000
8	61C0 0000	80 01C0 0000
9	61C8 0000	80 01C8 0000
10	61D0 0000	80 01D0 0000
11	61D8 0000	80 01D8 0000
12	61E0 0000	80 01E0 0000
13	61E8 0000	80 01E8 0000
14	61F0 0000	80 01F0 0000


Addresses of XMI Slots

XMI Slot	Address
1	2200 0000
2	2400 0000
3	2600 0000
4	2800 0000
5	2A00 0000
6	2C00 0000
7	2E00 0000
8	3000 0000
9	3200 0000
10	3400 0000
11	3600 0000
12	3800 0000
13	3A00 0000
14	3C00 0000


Addresses of XMI Slots

XMI Slot	Address
1	2200 0000
2	2400 0000
3	2600 0000
4	2800 0000
5	2A00 0000
6	2C00 0000
7	2E00 0000
8	3000 0000
9	3200 0000
10	3400 0000
11	3600 0000
12	3800 0000
13	3A00 0000
14	3C00 0000


Examining a VAXBI Register from the Console

To examine a VAXBI register from the DEC 7000 console, you need four pieces of information:

1	The XMI channel number (0-3) to which the VAXBI bus is connected.

2	The address for the XMI slot of the DWMBB module.

3	The base address of the VAXBI node.

4	The offset of the VAXBI register to be examined.

The address of the register to be examined is expressed in this form:

xmin:xxxyyzzz

where:	n = the XMI channel number
xxx = the XMI slot in which the DWMBB is installed
yy = the base address of the VAXBI node
zzz = the address offset of the VAXBI register

To calculate the address of the VAXBI register

1	Find the address of the XMI slot to which the VAXBI bus is connected.

2	Add the base address of the VAXBI node.

3	Add the address offset of the VAXBI register.

Example: Examining a VAXBI Register

>>> e xmi1:2200E000
xmi1: 2200E000 131C010E
>>>

In this example, the address for the examine command was derived in this way:

xmin:xxxyyzzz

n	xmi1	The VAXBI bus is connected to XMI1.

xxx	2200 0000	The DWMBB module is installed in XMI slot 1.

yy	0000 E000	The register to be examined is at VAXBI node 7.

zzz	000	The register to be examined is DTYPE.


Base Addresses of VAXBI Nodes

Node ID	Base Address
0	0000 0000
1	0000 2000
2	0000 4000
3	0000 6000
4	0000 8000
5	0000 A000
6	0000 C000
7	0000 E000
8	0001 0000
9	0001 2000
A	0001 4000
B	0001 6000
C	0001 8000
D	0001 A000
E	0001 C000
F	0001 E000

NOTE: You must look at the node ID plug on the backplane of the VAXBI card cage to determine the node ID of the VAXBI option.


Base Addresses of VAXBI Nodes

Node ID	Base Address
0	0000 0000
1	0000 2000
2	0000 4000
3	0000 6000
4	0000 8000
5	0000 A000
6	0000 C000
7	0000 E000
8	0001 0000
9	0001 2000
A	0001 4000
B	0001 6000
C	0001 8000
D	0001 A000
E	0001 C000
F	0001 E000

NOTE: You must look at the node ID plug on the backplane of the VAXBI card cage to determine the node ID of the VAXBI option.


Address Offsets of VAXBI Registers

Mnemonic	Register Name	Address Offset
DTYPE	Device	000
VAXBICSR	VAXBI Control and Status	004
BER	Bus Error	008
EINTRSCR	Error Interrupt Control	00C
INTRDES	Interrupt Destination	010
IPINTRMSK	IPINTR Mask	014
FIPSDES	Force-Bit IPINTR/STOP Destination	018
IPINTRSRC	IPINTR Source	01C
SADR	Starting Address	020
EADR	Ending Address	024
BCICSR	BCI Control and Status	028
WSTAT	Write Status	02C
FIPSCMD	Force-Bit IPINTR/STOP Command	030
UINTRCSR	User Interface Interrupt Control	040
GPR0	General Purpose Register 0	0F0
GPR1	General Purpose Register 1	0F4
GPR2	General Purpose Register 2	0F8
GPR3	General Purpose Register 3	0FC
SOSR	Slave-Only Status	100
RXCD	Receive Console Data	200


Address Offsets of VAXBI Registers

Mnemonic	Register Name	Address Offset
DTYPE	Device	000
VAXBICSR	VAXBI Control and Status	004
BER	Bus Error	008
EINTRSCR	Error Interrupt Control	00C
INTRDES	Interrupt Destination	010
IPINTRMSK	IPINTR Mask	014
FIPSDES	Force-Bit IPINTR/STOP Destination	018
IPINTRSRC	IPINTR Source	01C
SADR	Starting Address	020
EADR	Ending Address	024
BCICSR	BCI Control and Status	028
WSTAT	Write Status	02C
FIPSCMD	Force-Bit IPINTR/STOP Command	030
UINTRCSR	User Interface Interrupt Control	040
GPR0	General Purpose Register 0	0F0
GPR1	General Purpose Register 1	0F4
GPR2	General Purpose Register 2	0F8
GPR3	General Purpose Register 3	0FC
SOSR	Slave-Only Status	100
RXCD	Receive Console Data	200


Futurebus+ Addresses

Node	Address
1	FFFC 2000
2	FFFC 4000
3	FFFC 6000
4	FFFC 8000
5	FFFC A000
6	FFFC C000
7	FFFC E000
8	FFFD 0000
9	FFFD 2000
10	FFFD 4000


The DWLAA module (B2003-AA) is always in slot 5.


Console

These topics provide an overview of the console command set and command syntax.

Console Commands

Environment Variables

Device Name Fields

Console Special Characters


Console Commands

boot

build eeprom

cdp

clear

continue

crash

create

deposit

examine

help

initialize

mchk

repeat

set

show

start

stop

test

update

To introduce a comment


boot

Boot the operating system

Syntax

b[oot] [-fl[ags] <parameters>] [-fi[le] <filename>] <device_name>

Options

Option	Meaning
-file <file>	Boot from the file <file>
-flags <val>	Boot flags that qualify the bootstrap. If omitted, the value of the environment variable boot_osflags is used.

Examples

Booting OpenVMS AXP from a CD-ROM

Booting DEC OSF/1 AXP from a CD-ROM

Booting OpenVMS AXP from a Cluster

Booting DEC OSF/1 AXP from a CI Device

Booting LFU from an InfoServer

Booting LFU from an RRD42


build eeprom

Create a new or restore a corrupted EEPROM image

Syntax

bu[ild] ee[prom]


cdp

Perform basic configuration management of DSSI devices

Syntax

cdp [-{a,i,n,o,u}] [-sn] [-sa <val>] [<dssi_device>]

Options

Option	Meaning
-a	Set device allocation class, allclass
-i	Select interactive mode; set all parameters
-n	Set device node name, nodename (up to 16 characters)
-o	Override warning messages
-u	Set device unit number, unitnum
-sa allclass	Set allclass for all DSSI devices in the system to the specified value
-sn	Set nodename to either RFhscn or TFhscn
	h is the device hose number (0-3)
	s is the device slot number (1-14)
	c is the device channel number (0, 1)
	n is the device node ID number (0-6)
-su unitnum	Set the starting unitnum for the first DSSI device in the system to the specified value. Subsequent DSSI unit numbers are incremented from this base.

Example

Cdp Command


clear

Clear the specified EEPROM option, remove an environment variable, or clear the terminal screen

Syntax

cl[ear] ee[prom] <option>

cl[ear] <envar>

cl[ear] sc[reen]

Options

Option	Meaning
diag_sdd	Remove from EEPROM failure information logged by symptom-directed diagnosis
diag_tdd	Remove from EEPROM failure information logged by test-directed diagnosis
log	Remove from EEPROM all failure information (symptom-directed diagnosis, test-directed diagnosis, and operating system)
symptom	Remove from EEPROM all failure information on operating system


continue

Resume processing at the point it was interrupted by Ctrl/P

Syntax

c[ontinue]


crash

Restart the operating system; generate a memory dump

Syntax

cra[sh]


create

Create an environment variable

Syntax

cr[eate] [-nv] <envar> [<value>]

Option

Option	Meaning
-nv	Store the nonvolatile environment variable in EEPROM


deposit

Store data in a specified location

Syntax

d[eposit] [-{b,w,l,q,o,h,u}] [-{n val, s val}] [<space>:]<adrs> <data>

Options

Deposit Command Options

Device Name and Address Space Options

Location Symbols


Deposit Command Options

Option	Meaning
-b	Define data size as a byte
-h	Define data size as a hexword
-l	Define data size as a longword; initial default
-o	Define data size as an octaword
-q	Define data size as a quadword
-w	Define data size as a word
-n val	Number of consecutive locations to modify
-s val	Address increment size. Default is data size.
-u	Allow access to console private memory, while disabling virtual address protection checks


Deposit Command Options

Option	Meaning
-b	Define data size as a byte
-h	Define data size as a hexword
-l	Define data size as a longword; initial default
-o	Define data size as an octaword
-q	Define data size as a quadword
-w	Define data size as a word
-n val	Number of consecutive locations to modify
-s val	Address increment size. Default is data size.
-u	Allow access to console private memory, while disabling virtual address protection checks


Device Name and Address Space Options

Option	Meaning
<dev_name>	Device name; for example, xmi0, kn7aa0, or demna0
fpr	Define the address space as the floating-point register set, F0 through F31
gpr	Define the address space as the general register set, R0 through R31. The data size is always a longword.
ipr	Define the address space as the internal processor registers (IPRs). The data size is always a longword.
pt	Define the address space as the PAL temp register set, PT0 through PT31
pmem	Define the address space as physical memory
vmem	Define the address space as virtual memory. All access and protection checking occur.


Device Name and Address Space Options

Option	Meaning
<dev_name>	Device name; for example, xmi0, kn7aa0, or demna0
fpr	Define the address space as the floating-point register set, F0 through F31
gpr	Define the address space as the general register set, R0 through R31. The data size is always a longword.
ipr	Define the address space as the internal processor registers (IPRs). The data size is always a longword.
pt	Define the address space as the PAL temp register set, PT0 through PT31
pmem	Define the address space as physical memory
vmem	Define the address space as virtual memory. All access and protection checking occur.


Location Symbols

Symbol	Meaning
+	The location immediately following the last location referenced in a deposit or examine command. For physical and virtual memory, the referenced location is the last location plus the size of the reference (1 for byte, 2 for word, 4 for longword). For other address spaces, the address is the last referenced address plus one.
-	The location immediately preceding the last location referenced in a deposit or examine command. For physical and virtual memory, the referenced location is the last location minus the size of the reference (1 for byte, 2 for word, 4 for longword). For other address spaces, the address is the last referenced address minus one.
*	The last location referenced in a deposit or examine command.
@	The location addressed by the last location referenced in a deposit or examine command.


Location Symbols

Symbol	Meaning
+	The location immediately following the last location referenced in a deposit or examine command. For physical and virtual memory, the referenced location is the last location plus the size of the reference (1 for byte, 2 for word, 4 for longword). For other address spaces, the address is the last referenced address plus one.
-	The location immediately preceding the last location referenced in a deposit or examine command. For physical and virtual memory, the referenced location is the last location minus the size of the reference (1 for byte, 2 for word, 4 for longword). For other address spaces, the address is the last referenced address minus one.
*	The last location referenced in a deposit or examine command.
@	The location addressed by the last location referenced in a deposit or examine command.


examine

Display contents of a memory location, a register, or a device

Syntax

e[xamine] [-{b,w,l,q,o,h,d,u}] [-{n val, s val}] [<space>:]<adrs>

Options

Examine Command Options

Device Name and Address Space Options

Location Symbols

Examples

Examine KN7AA Registers

Examine AXP Internal Processor Registers

Examine Console Registers

Examine MS7AA Registers

Examine IOP Registers

Examine DWLMA Registers

Examine DWLAA Registers


Examine Command Options

Option	Meaning
-b	Define data size as a byte
-d	Disassemble instruction at current address
-h	Define data size as a hexword
-l	Define data size as a longword; initial default
-o	Define data size as an octaword
-q	Define data size as a quadword
-w	Define data size as a word
-n val	Number of consecutive locations to modify
-s val	Address increment size. Default is data size.
-u	Allow access to console private memory, while disabling virtual address protection checks


Examine Command Options

Option	Meaning
-b	Define data size as a byte
-d	Disassemble instruction at current address
-h	Define data size as a hexword
-l	Define data size as a longword; initial default
-o	Define data size as an octaword
-q	Define data size as a quadword
-w	Define data size as a word
-n val	Number of consecutive locations to modify
-s val	Address increment size. Default is data size.
-u	Allow access to console private memory, while disabling virtual address protection checks


help

Provide basic information on the console commands when the system is in console mode

Syntax

h[elp] [<option>]


initialize

Initialize the entire system or a specified device or subsystem

Syntax

i[nitialize] [<device_name>]


mchk

Dump internal state information for diagnosis of hardware failure

Syntax

mchk [<node_id>]

Example

Mchk Command


repeat

Repeat a command; stop by entering Ctrl/C

Syntax

r[epeat] [<command>]


set

Record the current system configuration in the EEPROM, set the selected EEPROM option, modify an environment variable, connect to another console or service, or configure the system power regulators for battery backup

Syntax

se[t] c[onfiguration]

se[t] ee[prom] <option>

se[t] <envar> [<value>]

se[t] h[ost] {[-dup] [-bus <b>] node [<task>] or <device_adapter>}

se[t] p[ower] -b {4, 8} {main, left, right}

Options

Set EEPROM Command Options

Set Host Command Options

Examples

Set Host Command -- Running DUP-Based Diagnostics and Utilities

Set Host Command -- Running Diagnostics on a Remote XMI Adapter

Running DEMNA Self-Test (Failing Case)

Running DEMNA Self-Test (Passing Case)


Set EEPROM Command Options

Option	Meaning
field	Record the LARS report number and comment
manufacturing	Record manufacturing information: module serial number and module part number
serial	Record system serial number


Set EEPROM Command Options

Option	Meaning
field	Record the LARS report number and comment
manufacturing	Record manufacturing information: module serial number and module part number
serial	Record system serial number


Set Host Command Options

Option	Meaning
-bus b	DSSI bus on which the node resides
-dup	Remote node is a DUP server


Set Host Command Options

Option	Meaning
-bus b	DSSI bus on which the node resides
-dup	Remote node is a DUP server


show

Display the last saved configuration, device information for a disk or tape adapter, selected EEPROM information, current state of an environment variable, memory module information, information about network devices, or system power status

Syntax

sh[ow] c[onfiguration] [-s]

sh[ow] dev[ice] [<dev_name>]

sh[ow] ee[prom] <option>

sh[ow] {<envar>, *}

sh[ow] m[emory]

sh[ow] ne[twork]

sh[ow] p[ower] [{-h, -s}] [{main, right, left}]

Options

Show EEPROM Command Options

Show Power Command Options

Examples

Show Configuration Command

Show Device Command

Show Network Command

Show Power Command


Show EEPROM Command Options

Option	Meaning
diag_sdd	Display failure information logged by symptom-directed diagnosis
diag_tdd	Display failure information logged by test-directed diagnosis
field	Display LARS number and comment
manufacturing	Display manufacturing information: module serial number and module part number
serial	Display system serial number
symptom	Display failure information logged on operating system


Show EEPROM Command Options

Option	Meaning
diag_sdd	Display failure information logged by symptom-directed diagnosis
diag_tdd	Display failure information logged by test-directed diagnosis
field	Display LARS number and comment
manufacturing	Display manufacturing information: module serial number and module part number
serial	Display system serial number
symptom	Display failure information logged on operating system


Show Power Command Options

Option	Meaning
-h	History status -- the value of each parameter at the last system shutdown
-s	Current status (default)
main	Power status of the main cabinet (default)
right	Power status of the expander cabinet to the right of the main cabinet
left	Power status of the expander cabinet to the left of the main cabinet


Show Power Command Options

Option	Meaning
-h	History status -- the value of each parameter at the last system shutdown
-s	Current status (default)
main	Power status of the main cabinet (default)
right	Power status of the expander cabinet to the right of the main cabinet
left	Power status of the expander cabinet to the left of the main cabinet


Abbreviations Used in Show Power Command Output

Abbreviation	Meaning

Power Supply State

NORMAL	Normal AC operation
BBU MODE	UPS mode
BRKR OPEN	Breaker open
NO AC IN	No AC voltage
KEYSW OFF	Keyswitch off
NON FATAL	Nonfatal fault
FATAL	Fatal fault
SPARE

Heatsink Status

BROKEN	Broken
FAULT	Fault (red zone)
WARNING	Warning
NORMAL	Normal operation

Battery Pack Status

NO BATTERY	Battery pack not installed
BATT FLT	Battery pack failure
BBU INH	UPS inhibit
CHG INH	Charger inhibit
BATT EOL	Battery at end of life
DISCHARG	Battery discharged
DISCHG'G	Discharging
CHARGING	Charging
OVER 24HRS	Charge mode longer than 24 hours
FULL CHG'D	Fully charged

Last UPS Test Status

NO BATTER	Battery pack not installed
NOT READY	Battery pack not ready (only if test requested)
ABORTED	Test aborted
TESTING	Test in progress
FAILED	Test failed
PASSED	Test passed


Abbreviations Used in Show Power Command Output

Abbreviation	Meaning

Power Supply State

NORMAL	Normal AC operation
BBU MODE	UPS mode
BRKR OPEN	Breaker open
NO AC IN	No AC voltage
KEYSW OFF	Keyswitch off
NON FATAL	Nonfatal fault
FATAL	Fatal fault
SPARE

Heatsink Status

BROKEN	Broken
FAULT	Fault (red zone)
WARNING	Warning
NORMAL	Normal operation

Battery Pack Status

NO BATTERY	Battery pack not installed
BATT FLT	Battery pack failure
BBU INH	UPS inhibit
CHG INH	Charger inhibit
BATT EOL	Battery at end of life
DISCHARG	Battery discharged
DISCHG'G	Discharging
CHARGING	Charging
OVER 24HRS	Charge mode longer than 24 hours
FULL CHG'D	Fully charged

Last UPS Test Status

NO BATTER	Battery pack not installed
NOT READY	Battery pack not ready (only if test requested)
ABORTED	Test aborted
TESTING	Test in progress
FAILED	Test failed
PASSED	Test passed


start

Begin execution of an instruction at specified address; does not initialize the system

Syntax

s[tart] <address>


stop

Halt a specified processor

Syntax

sto[p] <cpu_device_name>


test

Test the entire system (default), a subsystem, or a specified device

Syntax

t[est] [-write] [-nowrite <list>] [-omit <list>] [-t <time>] [-q] [<dev_arg>]

Options

Option	Meaning
-write	Select writes to media as well as reads (read-only is the default). Applicable only to disk testing (ignored otherwise).
-nowrite <list>	Used with -write to prevent selected devices or groups of devices from being written to
-omit <list>	Specify device not to test; takes a single device or device list as a qualifier
-t <time>	Run time in seconds for the test command; default for system is 600 seconds (10 minutes).
-q	"Quiet" option prevents informational messages about testing start and stop from being displayed on the console terminal. Error messages are always reported.

Examples

Test System

Write/Read/Compare Test of All Disks Not Associated with Controller "a"

Destructive Exercising Selected, Then Aborted

Test Command - Quiet Qualifier Set

Detection of Memory Data Compare Error

Test Using Wildcard

Test All Devices Associated with XMI0


update

Copy the contents of the EEPROM or FEPROMs on the boot processor to the EEPROM or FEPROMs on the specified secondary processor(s)

Syntax

upd[ate] -{e[eprom], f[lash]} <device_name>

Options

Option	Meaning
-flash	Update the FEPROMs on the specified secondary processor
-eeprom	Update the EEPROM on the specified secondary


To introduce a comment

#

Introduce a comment

Syntax

# <comment>


Environment Variables

An environment variable is a name and a value association maintained by the console program. The value associated with an environment variable is an ASCII string (up to 127 characters) or an integer. Volatile environment variables are initialized by a system reset; others are nonvolatile across system failures.

Environment variables are created by the console create command, modified by the set command, displayed by the show command, and deleted by the clear command.

Variable	Attribute	Function
auto_action	Non-volatile	The action the console will take following an error halt. Values are:
		restart -- Automatically restart. If restart fails, boot the operating system.
		boot -- Automatically boot the operating system.
		halt -- Enter console mode (default).
baud	Non-volatile	Sets the baud rate of the console terminal port to 300, 600, 1200, 2400, 4800, or 9600 (default).
bootdef_dev	Non-volatile	The default device or device list from which booting is attempted when the boot command does not specify a device name.
boot_file	Non-volatile	The default file name used for the primary bootstrap when the boot command does not specify a file name.
boot_osflags	Non-volatile	Additional parameters passed to the system during booting if none are specified by the  -flags qualifier to the boot command.
boot_reset	Non-volatile	Resets system and displays self-test results during booting. Default value is on.
cpu	Volatile	Selects the current boot processor.
cpu_enabled	Non-volatile	A bitmask indicating which processors are enabled to run (leave console mode). Default is 0xFF.
cpu_primary	Non-volatile	A bitmask indicating which processors are enabled to become the next boot processor after the next reset. Default is 0xFF.
d_harderr	Volatile	Determines action taken following a hard error. Values are halt (default) and continue. Applies only when using the test command.
d_report	Volatile	Determines level of information provided by the diagnostic reports. Values are summary (default) and full. Applies only when using the test command.
d_softerr	Volatile	Determines action taken following a soft error. Values are continue (default) and full. Applies only when using the test command.
dump_dev	Non-volatile	Complete device specification of the device to which operating system dumps are written. Default value is null. (Not supported by all operating systems.)
enable_audit	Non-volatile	When set to on, allows audit trail messages to be displayed during booting.
interleave	Non-volatile	The memory interleave specification. Values must be default, none, or an explicit interleave list. Default value is default.
language	Non-volatile	Determines whether system displays message numbers or message text in English (default).


Device Name Fields

Device names are used in several console commands. A device name is expressed in the form ddccuuuu.node.channel.slot.hose. Fields are separated by periods. The table below lists the field definitions.

Field	Size	Definition
dd	2	Protocol used to access the device:
		du -- MSCP disk (CI, SI, DSSI)
		mu -- MSCP tape (CI, SI, DSSI)
		ex -- XMI Ethernet
		fx -- XMI FDDI
		dk -- SCSI disk
		mk -- SCSI tape
cc	2 (max)	Controller letter (a--zz) assigned by console, based on the system configuration
uuuu	4 (max)	Unit number of the device (0--9999)
node	3 (max)	Node number (0--255) of the device on a remote (CI or DSSI) bus. If the remote bus is a CI, this is the CI node number of the HSC; if it is a DSSI, this is the node number of the disk.
channel	1	Channel number (0--1); used only if the adapter has multiple channels
slot	2 (max)	XMI slot number (1--14) of the adapter
hose	1	Hose number (0--3) that connects to the I/O bus


Console Special Characters

Character	Function
Return	Carriage return; ends a command line
Backslash	Line continuation
Backspace	Deletes previously typed character
Help	By itself, displays first-level help. When pressed after part of a command, displays options available.
Ctrl/A, F14	Toggles between insertion and overstrike modes
Ctrl/B, ↑	Recall previous command
Ctrl/C	Terminate running process
Ctrl/D, ←	Move cursor left one position
Ctrl/E	Move cursor to end of line
Ctrl/F, →	Move cursor right one position
Ctrl/H, BS, F12	Move cursor to beginning of line
Ctrl/J	Delete word
Ctrl/O	Stop output to console terminal for current command. Toggles between enable and disable.
Ctrl/P	In console mode, acts like Ctrl/C. In program mode, causes the boot processor to halt and begin running the console program.
Ctrl/Q	Resume output to console terminal
Ctrl/R	Redisplay the current line
Ctrl/S	Stop output to console terminal
Ctrl/U	Delete entire line
*	Wildcarding for some commands
" "	Quotes for set environment variable name
#	Comment specifier


Example: Booting OpenVMS AXP from a CD-ROM

>>> show device

polling for units on kzmsa0, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>> boot -flags 0,0 dka100.1.0.1.0

Booting...

Connecting to boot device dka100

initializing HWRPB at 2000

initializing page table at 1ee000

initializing machine state

jumping to bootstrap at 1fa000

OpenVMS AXP (TM) Operating System, Version V1.0


Example: Booting OpenVMS AXP from a CD-ROM

>>> show device

polling for units on kzmsa0, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>> boot -flags 0,0 dka100.1.0.1.0

Booting...

Connecting to boot device dka100

initializing HWRPB at 2000

initializing page table at 1ee000

initializing machine state

jumping to bootstrap at 1fa000

OpenVMS AXP (TM) Operating System, Version V1.0


Example: Booting DEC OSF/1 AXP from a CD-ROM

>>> show device

polling for units on kzmsa0, slot 2, xmi0...

dka100.1.0.2.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>> boot dka100.1.0.2.0

Booting...

Connecting to boot device dka100.1.0.2.0

Created boot device: dka100.1.0.2.0

block 0 of dka100.1.0.2.0 is a valid boot block

reading 16 blocks from dka100.1.0.2.0

bootstrap code read in

base = 1fe000, start = 0

initializing HWRPB at 2000

initializing page table at 1f2000

initializing machine state

jumping to bootstrap at 1fe000

Resetting IO subsystem...

[I/O subsystem reset information, memory information displayed, I/O bus adapters displayed, configured devices displayed, network configuration information displayed]

The system is ready.

DEC OSF/1 Version 1.2 console


Example: Booting DEC OSF/1 AXP from a CD-ROM

>>> show device

polling for units on kzmsa0, slot 2, xmi0...

dka100.1.0.2.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>> boot dka100.1.0.2.0

Booting...

Connecting to boot device dka100.1.0.2.0

Created boot device: dka100.1.0.2.0

block 0 of dka100.1.0.2.0 is a valid boot block

reading 16 blocks from dka100.1.0.2.0

bootstrap code read in

base = 1fe000, start = 0

initializing HWRPB at 2000

initializing page table at 1f2000

initializing machine state

jumping to bootstrap at 1fe000

Resetting IO subsystem...

[I/O subsystem reset information, memory information displayed, I/O bus adapters displayed, configured devices displayed, network configuration information displayed]

The system is ready.

DEC OSF/1 Version 1.2 console


Example: Booting OpenVMS AXP from a Cluster

>>> show device

polling for units on cixcd0, slot 2, xmi0...

dua20.14.0.2.0     $100$DUA20    RA82

dua31.14.0.2.0     $100$DUA31    RA82

dua80.15.0.2.0     $100$DUA80    RA90

>>> boot -fl 4,0 dua20.14.0.2.0

Booting...

Connecting to boot device dua20

initializing HWRPB at 2000

initializing page table at 1ee000

initializing machine state

jumping to bootstrap at 1fa000

OpenVMS AXP (TM) Operating System, Version V1.0


Example: Booting OpenVMS AXP from a Cluster

>>> show device

polling for units on cixcd0, slot 2, xmi0...

dua20.14.0.2.0     $100$DUA20    RA82

dua31.14.0.2.0     $100$DUA31    RA82

dua80.15.0.2.0     $100$DUA80    RA90

>>> boot -fl 4,0 dua20.14.0.2.0

Booting...

Connecting to boot device dua20

initializing HWRPB at 2000

initializing page table at 1ee000

initializing machine state

jumping to bootstrap at 1fa000

OpenVMS AXP (TM) Operating System, Version V1.0


Example: Booting DEC OSF/1 AXP from a CI Device

>>> show device

polling for units on cixcd0, slot 2, xmi0...

dua20.14.0.2.0     $100$DUA20    RA82

dua31.14.0.2.0     $100$DUA31    RA82

dua80.15.0.2.0     $100$DUA80    RA90

>>> boot dua31.14.0.2.0

Booting...

Connecting to boot device dua31.14.0.2.0

Connecting to boot device dua31.14.0.2.0

Created boot device: dua31.14.0.2.0

block 0 of dua31.14.0.2.0 is a valid boot block

reading 16 blocks from dua31.14.0.2.0

bootstrap code read in

base = 1fe000, start = 0

initializing HWRPB at 2000

initializing page table at 1f2000

initializing machine state

jumping to bootstrap at 1fe000

Resetting IO subsystem...

[I/O subsystem reset information, memory information displayed, I/O bus adapters displayed, configured devices displayed, network configuration information displayed]

The system is ready.

DEC OSF/1 Version 1.2 console


Example: Booting DEC OSF/1 AXP from a CI Device

>>> show device

polling for units on cixcd0, slot 2, xmi0...

dua20.14.0.2.0     $100$DUA20    RA82

dua31.14.0.2.0     $100$DUA31    RA82

dua80.15.0.2.0     $100$DUA80    RA90

>>> boot dua31.14.0.2.0

Booting...

Connecting to boot device dua31.14.0.2.0

Connecting to boot device dua31.14.0.2.0

Created boot device: dua31.14.0.2.0

block 0 of dua31.14.0.2.0 is a valid boot block

reading 16 blocks from dua31.14.0.2.0

bootstrap code read in

base = 1fe000, start = 0

initializing HWRPB at 2000

initializing page table at 1f2000

initializing machine state

jumping to bootstrap at 1fe000

Resetting IO subsystem...

[I/O subsystem reset information, memory information displayed, I/O bus adapters displayed, configured devices displayed, network configuration information displayed]

The system is ready.

DEC OSF/1 Version 1.2 console


Example: Booting LFU from an InfoServer

>>> boot exa0 -file APB_015 -flag 0,80

Booting...
Connecting to boot device exa0

Requesting MOP Assistance Volunteer.....
MOP Assistance Volunteer found.

Loading...
.................................
Load complete!
Image size: 2144256
Host name: GALL
Host address: aa-00-04-00-0c-74

bootstrap code read in
base = 127e00, start = 0
boot device name = exa0.0.0.14.2
boot flags  0,0,0
boot device type = 69
controller ID = a
unit number = 0
node ID = 0
channel = 0
slot = 14

hose = 2
jumping to bootstrap at 127e00

Bootfile: [DEC7000]AXP7000_Vnn.APB
Network Initial System Load Function
Version 1.1

FUNCTION	    FUNCTION
ID
1     -         Display Menu
2     -         Help
3     -         Choose Service
4     -         Select Options
5     -         Stop

Enter a function ID value: 3

OPTION	OPTION
ID
1     -         Find Services
2     -         Enter known Service Name

Enter an Option ID value: 1

Working

Servers found: 3

Service Name Format:
Service Number
Service Name
Server Name
Ethernet ID

#1
INFO4$RZ57
INFO4
08-00-2B-26-A6-98

#2
6000_DIAG_H
INFO3
08-00-2B-16-04-D4

#3
UPDATE
OPUS_ESS
08-00-2B-18-A9-75

Enter a Service Number or <CR> for more: 3

           Copyright Digital Equipment Corporation

                            1992

                    All Rights Reserved.

Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

        ***** Loadable Firmware Update Utility *****

          Version 2.1                  16-jun-1992


Example: Booting LFU from an InfoServer

>>> boot exa0 -file APB_015 -flag 0,80

Booting...
Connecting to boot device exa0

Requesting MOP Assistance Volunteer.....
MOP Assistance Volunteer found.

Loading...
.................................
Load complete!
Image size: 2144256
Host name: GALL
Host address: aa-00-04-00-0c-74

bootstrap code read in
base = 127e00, start = 0
boot device name = exa0.0.0.14.2
boot flags  0,0,0
boot device type = 69
controller ID = a
unit number = 0
node ID = 0
channel = 0
slot = 14

hose = 2
jumping to bootstrap at 127e00

Bootfile: [DEC7000]AXP7000_Vnn.APB
Network Initial System Load Function
Version 1.1

FUNCTION	    FUNCTION
ID
1     -         Display Menu
2     -         Help
3     -         Choose Service
4     -         Select Options
5     -         Stop

Enter a function ID value: 3

OPTION	OPTION
ID
1     -         Find Services
2     -         Enter known Service Name

Enter an Option ID value: 1

Working

Servers found: 3

Service Name Format:
Service Number
Service Name
Server Name
Ethernet ID

#1
INFO4$RZ57
INFO4
08-00-2B-26-A6-98

#2
6000_DIAG_H
INFO3
08-00-2B-16-04-D4

#3
UPDATE
OPUS_ESS
08-00-2B-18-A9-75

Enter a Service Number or <CR> for more: 3

           Copyright Digital Equipment Corporation

                            1992

                    All Rights Reserved.

Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

        ***** Loadable Firmware Update Utility *****

          Version 2.1                  16-jun-1992


Example: Booting LFU from an RRD42

>>>show device

polling for units on kzmsa, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

>>>boot dka100.1.0.1.0 -flag 0,80

Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  P  .  .  P  TYP
                     o  +  .  .  .  +  .  .  +  ST1
                     .  .  .  .  .  D  .  .  B  BPD
                     o  +  .  .  .  +  .  .  +  ST2
                     .  .  .  .  .  D  .  .  B  BPD
                     +  +  .  .  .  +  .  .  +  ST3
                     .  .  .  .  .  D  .  .  B  BPD

   +  +  +  .  .  .  +  .  .  .  .  +  +  +     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     . 128 .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

>>>

Booting...

Connecting to boot device dka100.1.0.1.0
block 0 of dka100 is a valid boot block
reading 7561 blocks from dka100.1.0.1.0
bootstrap code read in
base = lfe000, start = 0
initializing HWRPB at 2000

initializing page table at lf2000
initializing machine state
jumping to bootstarp at lfe000

Bootfile: [DEC7000]AXP7000_V04.APB

          Copyright Digital Equipment Corporation

                           1992

                   All Rights Reserved.

Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

        ***** Loadable Firmware Update Utility *****

          Version 2.1                  16-jun-1992


Example: Booting LFU from an RRD42

>>>show device

polling for units on kzmsa, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

>>>boot dka100.1.0.1.0 -flag 0,80

Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  P  .  .  P  TYP
                     o  +  .  .  .  +  .  .  +  ST1
                     .  .  .  .  .  D  .  .  B  BPD
                     o  +  .  .  .  +  .  .  +  ST2
                     .  .  .  .  .  D  .  .  B  BPD
                     +  +  .  .  .  +  .  .  +  ST3
                     .  .  .  .  .  D  .  .  B  BPD

   +  +  +  .  .  .  +  .  .  .  .  +  +  +     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     . 128 .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

>>>

Booting...

Connecting to boot device dka100.1.0.1.0
block 0 of dka100 is a valid boot block
reading 7561 blocks from dka100.1.0.1.0
bootstrap code read in
base = lfe000, start = 0
initializing HWRPB at 2000

initializing page table at lf2000
initializing machine state
jumping to bootstarp at lfe000

Bootfile: [DEC7000]AXP7000_V04.APB

          Copyright Digital Equipment Corporation

                           1992

                   All Rights Reserved.

Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

        ***** Loadable Firmware Update Utility *****

          Version 2.1                  16-jun-1992


Example: Cdp Command

>>> show device

polling for units on kfmsb0, slot 0, xmi0...

dua5.0.0.13.0    BASHFL$DIA5       RF71

polling for units on cixcd0, slot 14, xmi1...

dub44.1.0.13.0   $1$DIA44 (BLANK4) RF71

>>> cdp -i                # Interactive mode

dua5.0.0.13.0:

Node Name [BASHFL]?       # Press Return to go to next

Allocation Class [0]?     # field without making a

Unit Number [5]?          # change.

dub44.1.0.13.0:

Node Name [BLANK4]?

Allocation Class [1]?

Unit Number [44]?         # Press Return to exit.

>>> cdp -n dua5           # Set device node name of dua5.

dua5.0.0.13.0:

Node Name [BASHFL]?       # Exit, no changes made.

>>> cdp -a                # Set device allocation class.

dua5.0.0.13.0:

Allocation Class [0]?

dub44.1.0.13.0:

Allocation Class [1]?     # Exit, no changes made.


Example: Cdp Command

>>> show device

polling for units on kfmsb0, slot 0, xmi0...

dua5.0.0.13.0    BASHFL$DIA5       RF71

polling for units on cixcd0, slot 14, xmi1...

dub44.1.0.13.0   $1$DIA44 (BLANK4) RF71

>>> cdp -i                # Interactive mode

dua5.0.0.13.0:

Node Name [BASHFL]?       # Press Return to go to next

Allocation Class [0]?     # field without making a

Unit Number [5]?          # change.

dub44.1.0.13.0:

Node Name [BLANK4]?

Allocation Class [1]?

Unit Number [44]?         # Press Return to exit.

>>> cdp -n dua5           # Set device node name of dua5.

dua5.0.0.13.0:

Node Name [BASHFL]?       # Exit, no changes made.

>>> cdp -a                # Set device allocation class.

dua5.0.0.13.0:

Allocation Class [0]?

dub44.1.0.13.0:

Allocation Class [1]?     # Exit, no changes made.


Example: Examine KN7AA Registers

P00>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  0000  kn7aa0

  3+    KN7AA    (8001)  0000  kn7aa1

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0003  iop0

  C0 XMI                       xmi0

  1+    DEMNA    (0C03)  0802  demna0

  8+    DWLMA    (102A)  0003  dwlma0

  B+    KZMSA    (0C36)  013F  kzmsa0

  D+    KDM70    (0C22)  2911  kdm700

P00>>> examine kn7aa0:80	  # Examine Configuration
kn7aa0: 00000080 00000001	  # Register of KN7AA0
  # (Offset= 80)

P00>>> examine pmem:3f8000080	  # Same as above;
pmem: 00000003F8000080 00000001	  # examine physical
  # memory address
  # (PA + offset)

P00>>> examine kn7aa1:fc0	  # Examine Last Miss Address
kn7aa1: 00000FC0 000084FD	  # Register of KN7AA1
  # (Offset = FC0)

P00>>> examine pmem:3f8c00fc0	  # Same as above;
pmem: 00000003F8C00FC0 000084FD	  # examine physical
  # memory address
  # (PA + offset)


Example: Examine KN7AA Registers

P00>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  0000  kn7aa0

  3+    KN7AA    (8001)  0000  kn7aa1

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0003  iop0

  C0 XMI                       xmi0

  1+    DEMNA    (0C03)  0802  demna0

  8+    DWLMA    (102A)  0003  dwlma0

  B+    KZMSA    (0C36)  013F  kzmsa0

  D+    KDM70    (0C22)  2911  kdm700

P00>>> examine kn7aa0:80	  # Examine Configuration
kn7aa0: 00000080 00000001	  # Register of KN7AA0
  # (Offset= 80)

P00>>> examine pmem:3f8000080	  # Same as above;
pmem: 00000003F8000080 00000001	  # examine physical
  # memory address
  # (PA + offset)

P00>>> examine kn7aa1:fc0	  # Examine Last Miss Address
kn7aa1: 00000FC0 000084FD	  # Register of KN7AA1
  # (Offset = FC0)

P00>>> examine pmem:3f8c00fc0	  # Same as above;
pmem: 00000003F8C00FC0 000084FD	  # examine physical
  # memory address
  # (PA + offset)


Register	Offset	Register	Offset
LDEV	0	LMMR6	380
LBER	40	LMMR7	3C0
LCNR	80	LBESR0	600
LMMR0	200	LBESR1	640
LMMR1	240	LBESR2	680
LMMR2	280	LBESR3	6C0
LMMR3	2C0	LBECR0	700
LMMR4	300	LBECR1	740
LMMR5	340


Register	Offset	Register	Offset
LMODE	C00	LTAGW	D80
LMERR	C40	LCON	E00, E40
LLOCK	C80	LPERF	F00
LDIAG	D00	LCNTR	F40, F80
LTAGA	D40	LMISSADDR	FC0


Node	Physical Address
0	3 F800 0000
1	3 F840 0000
2	3 F880 0000
3	3 F8C0 0000
4	3 F900 0000
5	3 F940 0000
6	3 F980 0000
7	3 F9C0 0000


Example: Examine AXP Internal Processor Registers

>>> examine ipl	# Examine IPL

ipr: 00000006 (   IPL) 000000000000001F


Example: Examine AXP Internal Processor Registers

>>> examine ipl	# Examine IPL

ipr: 00000006 (   IPL) 000000000000001F


Example: Examine Console Registers

>>> examine pmem:3f7000000	# Examine Gbus$LEDs
pmem: 00000003F7000000 00000020	# register
# physical address


Example: Examine Console Registers

>>> examine pmem:3f7000000	# Examine Gbus$LEDs
pmem: 00000003F7000000 00000020	# register
# physical address


Register	Physical Address
Gbus$WHAMI	3 F700 0000
Gbus$LEDs	3 F700 0040
Gbus$PMask	3 F700 0080
Gbus$Intr	3 F700 00C0
Gbus$Halt	3 F700 0100
Gbus$LSBRST	3 F700 0140
Gbus$Misc	3 F700 0180
Gbus$RMode	3 F780 0000
Gbus$LTagRW	3 F780 0100


Example: Examine MS7AA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine ms7aa0:21c0	# Examine Memory
ms7aa0: 000021C0 10000000	# Diagnostic
# Register A
# (Offset = 21C0)

>>> examine pmem:3f98021c0	# Same as above;
pmem: 00000003F98021C0 10000000	# examine physical
# memory address
# (PA + offset)


Example: Examine MS7AA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine ms7aa0:21c0	# Examine Memory
ms7aa0: 000021C0 10000000	# Diagnostic
# Register A
# (Offset = 21C0)

>>> examine pmem:3f98021c0	# Same as above;
pmem: 00000003F98021C0 10000000	# examine physical
# memory address
# (PA + offset)


Register	Offset	Register	Offset
LDEV	0	MSTR0	2080
LBER	40	MSTR1	20C0
LCNR	80	FADR	2100
IBR	C0	MERA	2140
LBESR0	600	MSYNDA	2180
LBESR1	640	MDRA	21C0
LBESR2	680	MCBSA	2200
LBESR3	6C0	MERB	4140
LBECR0	700	MSYNDB	4180
LBECR1	740	MDRB	41C0
MCR	2000	MCBSB	4200
AMR	2040


Example: Examine IOP Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine iop0:0	# Examine Device
iop0: 00000000 00062000	# Register
# (Offset = 0)

>>> examine -l pmem:3fa000000	# Same as above;
pmem: 00000003FA000000 00062000	# examine physical
# memory address
# (3FA00000 + offset)


Example: Examine IOP Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine iop0:0	# Examine Device
iop0: 00000000 00062000	# Register
# (Offset = 0)

>>> examine -l pmem:3fa000000	# Same as above;
pmem: 00000003FA000000 00062000	# examine physical
# memory address
# (3FA00000 + offset)


Register	Offset	Register	Offset
LDEV	0	LBECR0	700
LBER	40	LBECR1	740
LCNR	80	LILID0	A00
IBR	C0	LILID1	A40
LMMR0	200	LILID2	A80
LMMR1	240	LILID3	AC0
LMMR2	280	LCPUMASK	B00
LMMR3	2C0	LMBPR0	C00
LMMR4	300	LMBPR1	C00
LMMR5	340	LMBPR2	C00
LMMR6	380	LMBPR3	C00
LMMR7	3C0	IPCNSE	2000
LBESR0	600	IPCVR	2040
LBESR1	640	IPCMSR	2080
LBESR2	680	IPCHST	20C0
LBESR3	6C0	IPCDR	2100


Example: Examine DWLMA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine dwlma0:0	# Examine DWLMA Device
dwlma0: 00000000 0104102A	# Register
# (Offset = 0)

>>> examine xmi0:61c00000	# Same as above; examine
xmi0: 61C00000 0104102A	# address on XMI
# (PA + offset)

>>> examine -n 4 dwlma0:0	# Examine all DWLMA
dwlma0: 00000000 0104102A 	# XMI required registers.
dwlma0: 00000004 00000202
dwlma0: 00000008 61902470
dwlma0: 0000000C 7000000F
dwlma0: 00000010 00000003


Example: Examine DWLMA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine dwlma0:0	# Examine DWLMA Device
dwlma0: 00000000 0104102A	# Register
# (Offset = 0)

>>> examine xmi0:61c00000	# Same as above; examine
xmi0: 61C00000 0104102A	# address on XMI
# (PA + offset)

>>> examine -n 4 dwlma0:0	# Examine all DWLMA
dwlma0: 00000000 0104102A 	# XMI required registers.
dwlma0: 00000004 00000202
dwlma0: 00000008 61902470
dwlma0: 0000000C 7000000F
dwlma0: 00000010 00000003


Register	Offset	Register	Offset
XDEV	0	LEVR	48
XBER	4	LERR	4C
XFADR	8	LGPR	50
XFAER	C	IPR1	54
IBR	10	IPR2	58
LDIAG	40	IIPR	5C
IMSK	44


Node	Physical Address
1	6188 0000
2	6190 0000
3	6198 0000
4	61A0 0000
5	61A8 0000
6	61B0 0000
7	61B8 0000
8	61C0 0000
9	61C8 0000
10	61D0 0000
11	61D8 0000
12	61E0 0000
13	61E8 0000
14	61F0 0000


Example: Examine DWLAA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine dwlaa0:04	# Examine DWLAA Node
dwlaa0: 00000004 0000FFCA	# Identification
# Register (Offset = 04)

>>> examine fbus0:fffca004	# Same as above; examine
fbus0: FFFCA004 0000FFCA	# address on FBUS
# (FFFC A000 + offset)

>>> examine -n d dwlaa0:0	# Examine all DWLAA
dwlaa0: 00000000 00000000	# registers
dwlaa0: 00000004 0000FFCA
dwlaa0: 00000008 04000000
dwlaa0: 0000000C E4020000
dwlaa0: 00000010 00000000
dwlaa0: 00000014 00000000
dwlaa0: 00000018 00000000
dwlaa0: 0000001C 00080000
dwlaa0: 00000020 00800040
dwlaa0: 00000024 000F000E
dwlaa0: 00000028 EE010000
dwlaa0: 0000002C 00000001
dwlaa0: 00000030 00000000
dwlaa0: 00000034 00000007


Example: Examine DWLAA Registers

>>> show config

        Name     Type    Rev   Mnemonic

  LSB

  0+    KN7AA    (8001)  4000  kn7aa0

  7+    MS7AA    (4000)  0000  ms7aa0

  8+    IOP      (2000)  0006  iop0

  C0 XMI                       xmi0

  5+    DEMFA    (0823)  2513  demfa0

  8+    DWLMA    (102A)  0104  dwlma0

  C+    KDM70    (0C22)  2911  kdm700

  E+    DEMNA    (0C03)  0802  demna0

  C1 FBUS                      fbus0

  5+    DWLAA    (2003)  0000  dwlaa0

  6+    DEFAA    (2006)  0000  defaa0

>>> examine dwlaa0:04	# Examine DWLAA Node
dwlaa0: 00000004 0000FFCA	# Identification
# Register (Offset = 04)

>>> examine fbus0:fffca004	# Same as above; examine
fbus0: FFFCA004 0000FFCA	# address on FBUS
# (FFFC A000 + offset)

>>> examine -n d dwlaa0:0	# Examine all DWLAA
dwlaa0: 00000000 00000000	# registers
dwlaa0: 00000004 0000FFCA
dwlaa0: 00000008 04000000
dwlaa0: 0000000C E4020000
dwlaa0: 00000010 00000000
dwlaa0: 00000014 00000000
dwlaa0: 00000018 00000000
dwlaa0: 0000001C 00080000
dwlaa0: 00000020 00800040
dwlaa0: 00000024 000F000E
dwlaa0: 00000028 EE010000
dwlaa0: 0000002C 00000001
dwlaa0: 00000030 00000000
dwlaa0: 00000034 00000007


Register	Offset	Register	Offset
FINT	000	DIAG	028
NID	004	FGPR	02C
STO	008	FERR	030
ERRHI	00C	IBR	034
ERRLO	010	DID	None
FADRHI	014	INT14	800
FADRLO	018	INT15	804
TTO	01C	INT16	808
BZRTRY	020	INT17	80C
FCTL	024


Example: Mchk Command

>>> mchk

pal                 	V5.37-2/O1.28-2

pal_flags           	0450010860000005

PTBR ipr: 0000000A (  PTBR) 0000000000000000

SCBB ipr: 0000000B (  SCBB) 0000000000000000

PCBB ipr: 00000008 (  PCBB) 0000000000001000

exc_addr pmem: 00006130 000000000003D258

iccsr pmem: 00006148 00000000009F0000

hirr pmem: 00006160 0000000000000342

mm_csr pmem: 00006168 0000000000005080

dc_stat pmem: 00006170 00000000000002E8

dc_addr pmem: 00006178 00000007FFFFFFFF

biu_stat pmem: 00006188 0000000000001850

biu_addr pmem: 00006190 0000000000006120

biu_ctl pmem: 00006198 0000000850006447

fill_syndrome pmem: 000061A0 0000000000000000

fill_addr pmem: 000061A8 000000000000DD10

va pmem: 000061B0 0000000000006190

lep_gbus pmem: 000061C0 0020000000000030

lber pmem: 000061CC 00000021

lmerr pmem: 000061D4 00000000

lbesr0 pmem: 000061D8 0000000C

lbesr1 pmem: 000061DC 0000000C

lbesr2 pmem: 000061E0 0000000C

lbesr3 pmem: 000061E4 0000000C

lbecr0 pmem: 000061E8 0000E064

lbecr1 pmem: 000061EC 00004000

vhit pmem: F8000F80 00000000

tag pmem: 00006008 00E005550000000F

dwlma0 XBE xmi0: 60000004 0000000100000202

dwlma0 LERR xmi0: 6000004C 0000000100000000

>>>


Example: Mchk Command

>>> mchk

pal                 	V5.37-2/O1.28-2

pal_flags           	0450010860000005

PTBR ipr: 0000000A (  PTBR) 0000000000000000

SCBB ipr: 0000000B (  SCBB) 0000000000000000

PCBB ipr: 00000008 (  PCBB) 0000000000001000

exc_addr pmem: 00006130 000000000003D258

iccsr pmem: 00006148 00000000009F0000

hirr pmem: 00006160 0000000000000342

mm_csr pmem: 00006168 0000000000005080

dc_stat pmem: 00006170 00000000000002E8

dc_addr pmem: 00006178 00000007FFFFFFFF

biu_stat pmem: 00006188 0000000000001850

biu_addr pmem: 00006190 0000000000006120

biu_ctl pmem: 00006198 0000000850006447

fill_syndrome pmem: 000061A0 0000000000000000

fill_addr pmem: 000061A8 000000000000DD10

va pmem: 000061B0 0000000000006190

lep_gbus pmem: 000061C0 0020000000000030

lber pmem: 000061CC 00000021

lmerr pmem: 000061D4 00000000

lbesr0 pmem: 000061D8 0000000C

lbesr1 pmem: 000061DC 0000000C

lbesr2 pmem: 000061E0 0000000C

lbesr3 pmem: 000061E4 0000000C

lbecr0 pmem: 000061E8 0000E064

lbecr1 pmem: 000061EC 00004000

vhit pmem: F8000F80 00000000

tag pmem: 00006008 00E005550000000F

dwlma0 XBE xmi0: 60000004 0000000100000202

dwlma0 LERR xmi0: 6000004C 0000000100000000

>>>


Example: Show Configuration Command

>>> show config

      Name     Type      Rev       Mnemonic

LSB

0+    KN7AA    (8001)    0000      kn7aa0

6+    MS7AA    (4000)    0000      ms7aa0

7+    MS7AA    (4000)    0000      ms7aa1

8+    IOP      (2000)    0006      iop0

C0 XMI                             xmi0

1+    DEMNA    (0C03)    0802      demna0

4+    KDM70    (0C22)    1E11      kdm700

8+    DWLMA    (102A)    0104      dwlma0

C1 XMI                             xmi1

6+    DEMNA    (0C03)    0802      demna1

8+    DWLMA    (102A)    0104      dwlma1

D+    KDM70    (0C22)    1E11      kdm701

E+    KZMSA    (0C36)    413F      kzmsa0


Example: Show Configuration Command

>>> show config

      Name     Type      Rev       Mnemonic

LSB

0+    KN7AA    (8001)    0000      kn7aa0

6+    MS7AA    (4000)    0000      ms7aa0

7+    MS7AA    (4000)    0000      ms7aa1

8+    IOP      (2000)    0006      iop0

C0 XMI                             xmi0

1+    DEMNA    (0C03)    0802      demna0

4+    KDM70    (0C22)    1E11      kdm700

8+    DWLMA    (102A)    0104      dwlma0

C1 XMI                             xmi1

6+    DEMNA    (0C03)    0802      demna1

8+    DWLMA    (102A)    0104      dwlma1

D+    KDM70    (0C22)    1E11      kdm701

E+    KZMSA    (0C36)    413F      kzmsa0


Example: Show Device Command

>>> show device

polling for units on kzmsa0, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>>


Example: Show Device Command

>>> show device

polling for units on kzmsa0, slot 1, xmi0...

dka100.1.0.1.0      dka100          RRD42

polling for units on kdm700, slot 6, xmi0...

dub1.1.0.6.0      DUB1       RA82

dub2.2.0.6.0      DUB2       RA90

>>>


Example: Show Network Command

>>> show network

polling for units on demna0, slot 14, xmi0...

exa0.0.0.14.0: 08-00-2B-24-3F-E1

polling for units on demfa0, slot 1, xmi1...

fxa0.0.0.1.1: 08-00-2B-29-E0-FF

>>>


Example: Show Network Command

>>> show network

polling for units on demna0, slot 14, xmi0...

exa0.0.0.14.0: 08-00-2B-24-3F-E1

polling for units on demfa0, slot 1, xmi1...

fxa0.0.0.1.1: 08-00-2B-29-E0-FF

>>>


Example: Show Power Command

P00>>> show power

Cabinet: Main	Regulator :	   A	   B	   C

-------------------------------------------------------------------------------

          Primary Micro Firmware Rev :	  2.2	  2.2	  2.2

        Secondary Micro Firmware Rev :	  2.2	  2.2	  2.2

                  Power Supply State : 	NORMAL 	NORMAL 	NORMAL

             AC Line Voltage (V RMS) : 	111.65 	111.49 	104.34

               DC Bulk Voltage (VDC) : 	227.02 	227.02 	227.02

            48V DC Bus Voltage (VDC) : 	 48.69 	 48.75 	 48.75

            48V DC Bus Current (ADC) : 	 30.17 	 29.68 	 29.58

      48V Battery Pack Voltage (VDC) : 	 50.85 	 50.72 	 47.91

      24V Battery Pack Voltage (VDC) : 	 25.56 	 25.56 	 23.95

   Battery Pack Charge Current (IDC) :	  2.91	  2.90	  2.91

      Ambient Temperature (Degree C) : 	 26.22 	 24.80 	 24.75

                Elapsed Time (Hours) : 	290.00 	290.00 	290.00

Remaining Battery Capacity (Minutes) :	  8.00	  8.00	  8.00

     Battery Cutoff Counter (Cycles) :	  1.00	  1.00	  1.00

               Battery Configuration : 4 Batteries  4 Batteries  4 Batteries

                     Heatsink Status : 	NORMAL 	NORMAL 	NORMAL

                 Battery Pack Status : 	CHARGING	CHARGING	CHARGING

                Last UPS Test Status : 	PASSED 	PASSED 	PASSED

LDC POWER Status     : OK
PIU Primary Status   : OK
PIU Secondary Status : OK

The cabinet in the above example has three power regulators. If the cabinet has fewer than three regulators, the appropriate column (A, B, or C) is left blank. The bottom three lines of the output, showing PIU power status, apply only to the main cabinet.

Abbreviations used in output of show power command


Example: Show Power Command

P00>>> show power

Cabinet: Main	Regulator :	   A	   B	   C

-------------------------------------------------------------------------------

          Primary Micro Firmware Rev :	  2.2	  2.2	  2.2

        Secondary Micro Firmware Rev :	  2.2	  2.2	  2.2

                  Power Supply State : 	NORMAL 	NORMAL 	NORMAL

             AC Line Voltage (V RMS) : 	111.65 	111.49 	104.34

               DC Bulk Voltage (VDC) : 	227.02 	227.02 	227.02

            48V DC Bus Voltage (VDC) : 	 48.69 	 48.75 	 48.75

            48V DC Bus Current (ADC) : 	 30.17 	 29.68 	 29.58

      48V Battery Pack Voltage (VDC) : 	 50.85 	 50.72 	 47.91

      24V Battery Pack Voltage (VDC) : 	 25.56 	 25.56 	 23.95

   Battery Pack Charge Current (IDC) :	  2.91	  2.90	  2.91

      Ambient Temperature (Degree C) : 	 26.22 	 24.80 	 24.75

                Elapsed Time (Hours) : 	290.00 	290.00 	290.00

Remaining Battery Capacity (Minutes) :	  8.00	  8.00	  8.00

     Battery Cutoff Counter (Cycles) :	  1.00	  1.00	  1.00

               Battery Configuration : 4 Batteries  4 Batteries  4 Batteries

                     Heatsink Status : 	NORMAL 	NORMAL 	NORMAL

                 Battery Pack Status : 	CHARGING	CHARGING	CHARGING

                Last UPS Test Status : 	PASSED 	PASSED 	PASSED

LDC POWER Status     : OK
PIU Primary Status   : OK
PIU Secondary Status : OK

The cabinet in the above example has three power regulators. If the cabinet has fewer than three regulators, the appropriate column (A, B, or C) is left blank. The bottom three lines of the output, showing PIU power status, apply only to the main cabinet.

Abbreviations used in output of show power command


Self-Test and Diagnostics

Self-test is run when the system is powered up or reset.

Diagnostics are run using the test command or the set host command.

Self-Test

SROM Tests

GROM Tests

CPU/Memory Tests

Multiprocessor Tests

IOP Tests

DWLMA Tests

DWLAA Tests

Test Command

Test System

Write/Read/Compare Test of All Disks Not Associated with Controller "a"

Destructive Exercising Selected, Then Aborted

Test Command - Quiet Qualifier Set

Detection of Memory Data Compare Error

Test Using Wildcard

Test All Devices Associated with XMI0

Set Host Command -- Running DUP-Based Diagnostics and Utilities

Set Host Command -- Running Diagnostics on a Remote XMI Adapter

Running DEMNA Self-Test (Failing Case)

Running DEMNA Self-Test (Passing Case)


SROM Tests

Test Number	Test Name
1	D-cache data RAM march test
2	Backup cache data line test
3	Backup cache data RAM march/address bus test
4	ECC data line test
5	ECC data RAM march test
6	Gbus accessibility test
7	B-tag data line test
8	B-cache tag store RAM march test
9	B-cache stat store RAM march test
10	B-map data line test
11	B-map RAM march test
12	D-map RAM march test
13	Watch chip interval timer test
14	TRANS code w/LEP Gbus ROM checksum test


GROM Tests

Test Number	Test Name
15	Device register test
16	LSB bus error register test
17	CPU module error register test
18	Gbus/LEVI-A CSR read/write test
19	EV4 write buffer test
20	ECC logic test
21	Backup cache data line test
22	Backup tag store RAM march test
23	B-stat RAM march test
24	B-map RAM march test
25	Backup cache data RAM march test
26	ECC data RAM march test
27	Backup cache to LEVI data path test
28	Backup cache to LEVI data line test
29	ECC logic shared test
30	LDxL/STxC test
31	Watch chip TOY registers test
32	LEP EEPROM test
33	DUART0 and DUART1 internal loopback interrupt and baud rate test
34	DUART2A ^P detect internal/external loopback interrupt and baud rate test
35	EV4 single-bit ECC error test
36	EV4 double-bit ECC error test
37	Backup tag store parity error test
38	Backup stat store parity error test
39	B-map parity error test
40	D-map parity error test
41	Invalidate logic test
42	LSB parity error during CSR data cycles test
43	LSB parity error during CSR C/A cycles test
44	Interrupts at IPL 14-17 test
45	Interprocessor interrupt test
46	Nonexistent address error test
47	Device register test
48	Backup cache to LEVI data path test
49	Backup cache to LEVI data line test
50	ECC logic shared test


CPU/Memory Tests

Test Number	Test Name
1	CPU/memory LDEV test
2	Single-bit ECC error test
3	Double-bit ECC error test
4	B-cache read fill test
5	CSR command parity error test
6	Column parity error test
7	Row parity error test
8	DRAM ECC error test
9	Address line walk test
10	Shared write through cache test


Multiprocessor Tests

Test Number	Test Name
1	IP interrupts test
2	Shared updates test
3	LSB and victim writes test
4	LSB writes test
5	LSB writes 2 test
6	Invalidate test
7	Multiple concurrent Add Aligned Word Interlocked instructions test


IOP Tests

Test Number	Test Name
1	Register write/read test
2	Unique register addressing test
3	Nonexistent LSB addressing test
4*	Node reset test
5	Forced CAE error test
6	Forced CNFE error test
7	Forced LSB CSR data parity error test
8	Loopback mailbox test
9*	Nonexistent mailbox address error test
10	Forced LSB command parity error test
11	IOP LSB arbitration test
12	Force Up Vortex parity errors test
13	Force Up Vortex sequence errors test
14*	Force Down Vortex parity errors test
15*	Force Down Vortex sequence errors test
16*	Force Down Vortex illegal command error test
17	Hose parity error test
18	Hose sequence error test
19	Hose illegal command error test
20*	Hose overflow error test
21	IOP internal interrupt test
22	Remote adapter GPR write read test
23*	LSB correctable ECC errors test
24*	EEPROM read 16 bytes test

* These tests are run only in user mode.


DWLMA Tests

Test Number	Test Name
1	Force Down Hose parity test
2	Force Up Hose parity test
3	DWLMA register read/write test
4	Unique register addressing test
5*	Nonexistent internal addressing test
6	Mailbox illegal command test
7*	DWLMA reset test
8	Arb suppress mode test
9	XMI bus GPR write/read test
10	DWLMA XMI node space register read/write test
11	Node space unique register addressing test
12*	XMI node space nonexistent addressing test
13	Disable XMI timeout disable retries on NO ACK test
14	Nonsupported register offset test
15	XFADR and XFAER register test
16	Forced XMI read response test
17*	Force XMI parity error test
18*	DMA read data test
19*	DMA read length test
20*	DMA read tag<7:6> test
21*	More read stream termination test
22*	More read stream discard command queue test
23*	More read stream DHW pre-fetch test
24*	QW-length More stream read test
25*	Contiguous OW DMA read buffer addressing test
26	Contiguous HW DMA read buffer addressing test
27*	Random DMA read buffer addressing test
28	Arb suppress mode test
29*	Quadword-length More bypass test
30*	Masked DMA write test
31*	Unmasked DMA write test
32*	Flushing the More write tag sequential test
33*	Flushing the More write tag nonsequential test
34*	More write stream discard command queue test
35*	Unaligned HW More stream write test
36*	Unaligned OW More stream write test
37*	Contiguous DMA More write buffer addressing test
38	Contiguous non-More DMA write buffer addressing test
39	Random DMA write buffer addressing test
40	Quadword-length More bypass test
41*	Multiple DWLMA interrupt test
42*	DWLMA EEPROM read 16 bytes test

* These tests are run only in user mode.


DWLAA Tests

Test Number	Test Name
1	Register initialize test
2	Register read/write test
3	Unique register addressing test
4*	Serial EEPROM test
5	Illegal CSR access test
6	Illegal MBOX command test
7	Down Hose header cycle parity error test
8	Down Hose data cycle parity error test
9	AD[63:0] transceiver loopback test
10	BP[7:0] transceiver loopback test
11	CM[7:0] transceiver loopback test
12*	Nonexistent address error test
13*	Futurebus transaction timeout test
* These tests are run only in user mode.


Example: Test System

P00>>> test -t 120

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting memory exerciser, running on kn7aa* (id #9c)

Starting memory exerciser, running on kn7aa* (id #c6)

Starting memory exerciser, running on kn7aa* (id #f3)

Starting memory exerciser, running on kn7aa* (id #122)

Starting memory exerciser, running on kn7aa* (id #151)

Starting memory exerciser, running on kn7aa* (id #1d0)

Starting device exerciser on dka1.1.0.1.2 (id #236) in READ-ONLY mode

Stopping device exerciser on dka1.1.0.1.2 (id #236)

Starting device exerciser on dka3.3.0.1.2 (id #28e) in READ-ONLY mode

Stopping device exerciser on dka3.3.0.1.2 (id #28e)

Starting device exerciser on due0.0.0.10.2 (id #2e6) in READ-ONLY mode

Stopping device exerciser on due0.0.0.10.2 (id #2e6)

Starting device exerciser on due1.0.0.10.2 (id #33e) in READ-ONLY mode

Stopping device exerciser on due1.0.0.10.2 (id #33e)

Stopping memory exerciser, running on kn7aa* (id #f3)

Stopping memory exerciser, running on kn7aa* (id #c6)

Stopping memory exerciser, running on kn7aa* (id #1d0)

Stopping memory exerciser, running on kn7aa* (id #122)

Stopping memory exerciser, running on kn7aa* (id #151)

Stopping memory exerciser, running on kn7aa* (id #9c)

Done testing...

P00>>>


Example: Write/Read/Compare Test of All Disks Not Associated with Controller a
Example: Write/Read/Compare Test of All Disks Not Associated with Controller "a"

P00>>> test -nowrite "dka*" -write -t 120

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Are you sure you want to perform writes to the selected disks? [yes/(no)] yes

User data on all selected devices may be lost. Continue? [yes/(no)] yes

Testing...

Starting memory exerciser, running on kn7aa* (id #9c)

Starting memory exerciser, running on kn7aa* (id #c6)

Starting memory exerciser, running on kn7aa* (id #f3)

Starting memory exerciser, running on kn7aa* (id #122)

Starting memory exerciser, running on kn7aa* (id #151)

Starting memory exerciser, running on kn7aa* (id #1d0)

Starting device exerciser on due0.0.0.10.2 (id #2e6) in WRITE/READ mode

Stopping device exerciser on due0.0.0.10.2 (id #2e6)

Starting device exerciser on due1.0.0.10.2 (id #33e) in WRITE/READ mode

Stopping device exerciser on due1.0.0.10.2 (id #33e)

Starting device exerciser on due2.0.0.10.2 (id #379) in WRITE/READ mode

Stopping device exerciser on due2.0.0.10.2 (id #379)

Starting device exerciser on due3.0.0.10.2 (id #3b1) in WRITE/READ mode

Stopping device exerciser on due3.0.0.10.2 (id #3b1)

Stopping memory exerciser, running on kn7aa* (id #f3)

Stopping memory exerciser, running on kn7aa* (id #c6)

Stopping memory exerciser, running on kn7aa* (id #1d0)

Stopping memory exerciser, running on kn7aa* (id #122)

Stopping memory exerciser, running on kn7aa* (id #151)

Stopping memory exerciser, running on kn7aa* (id #9c)

Done testing...

P00>>>


Example: Destructive Exercising Selected, Then Aborted

P00>>> test -w -n "dka*"

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Are you sure you want to perform writes to the selected disks? [yes/(no)] no

Testing aborted...

P00>>>


Example: Test Command - Quiet Qualifier Set

P00>>> test -q -t 300

Configuring system...

Default system exerciser selected for runtime of 300 seconds

Type Ctrl/C to abort...

Done testing...

P00>>>


Example: Detection of Memory Data Compare Error

>>> set d_report full

>>> test ms7aa*

Memory subsystem test selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting memory exerciser, running on kn7aa0 (id #aa)

Still testing...

Still testing...

*** Hard Error - Error #23 on FRU: kn7aa0,ms7aa1

Data compare error

      ID  Program         Device     Pass Hard/Soft Test     Time

-------- -------- -------------- -------- --------- ---- --------

000000aa   mem_ex         memory      433    1    0    4 10:23:51

Expected value: FFFFFFE0

Received value: FFF7FFE0

Failing addr:   047C87C8

*** End of Error ***

Testing aborted - halt-on-error selected...

Stopping memory exerciser on kn7aa0 (id #aa)

Done testing...

>>>


Example: Test Using Wildcard

>>> test dem*a*

Network exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Initializing demfa0

Initializing demna0

Initializing demna1

Self-test passed on device demfa0

Self-test passed on device demna0

Self-test passed on device demna1

Configuring demfa0

polling for units on demfa0, slot 5, xmi0...

fxa0.0.0.5.0: 08-00-2B-29-E0-FF

Configuring demna0

polling for units on demna0, slot 14, xmi0...

exa0.0.0.14.0: 08-00-2B-25-D7-C1

Configuring demna1

polling for units on demna1, slot 13, xmi1...

exb0.0.0.13.1: 08-00-2B-46-E8-84

Starting network exerciser on exa0.0.0.14.0 (id #144) in external loopback mode

Starting network exerciser on exb0.0.0.13.1 (id #187) in external loopback mode

Starting network exerciser on fxa0.0.0.5.0 (id #1b1) in external loopback mode

Stopping network exerciser on exa0.0.0.14.0 (id #144)

Stopping network exerciser on exb0.0.0.13.1 (id #187)

Stopping network exerciser on fxa0.0.0.5.0 (id #1b1)

Done testing...

>>>


Example: Test All Devices Associated with XMI0

>>> test xmi0 -omit demna1

XMI subsystem test selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting DWLMA exerciser on dwlma0

Stopping DWLMA exerciser on dwlma0

Initializing demna0

Initializing demfa0

Initializing kdm700

Self-test passed on device demna0

Self-test passed on device demfa0

Self-test passed on device kdm700

Configuring demna0

exa0.0.0.14.0: 08-00-2B-25-D7-C1

Configuring demfa0

fxa0.0.0.5.0: 08-00-2B-29-E0-FF

Configuring kdm700

polling for units on kdm700, slot 12, xmi0...

due0.0.0.12.0      DUE0                      RA70

due1.0.0.12.0      DUE1                      RA70

due2.0.0.12.0      DUE2                      RA70

due3.0.0.12.0      DUE3                      RA70

Starting network exerciser on exa0.0.0.14.0 (id #181) in external loopback mode

Starting network exerciser on fxa0.0.0.5.0 (id #192) in external loopback mode

Starting device exerciser on due0.0.0.12.0 (id #2e6) in READ-ONLY mode

Starting device exerciser on due1.0.0.12.0 (id #33e) in READ-ONLY mode

Starting device exerciser on due2.0.0.12.0 (id #379) in READ-ONLY mode

Starting device exerciser on due3.0.0.12.0 (id #3b1) in READ-ONLY mode

Stopping device exerciser on due0.0.0.12.0 (id #2e6)

Stopping device exerciser on due1.0.0.12.0 (id #33e)

Stopping device exerciser on due2.0.0.12.0 (id #379)

Stopping device exerciser on due3.0.0.12.0 (id #3b1)

Stopping network exerciser on exa0.0.0.14.0 (id #181)

Stopping network exerciser on fxa0.0.0.5.0 (id #192)

Done testing...

>>>


Example: Set Host Command -- Running DUP-Based Diagnostics and Utilities

>>> show device kdm700

polling for units on kdm700, slot 12, xmi0...

dua32.0.0.12.0     DUA32                     RA70

dua34.0.0.12.0     DUA34                     RA70

dua77.0.0.12.0     DUA77                     RA70

>>> set host -dup dua32.0.0.12.0

dup: starting DIRECT on kdm70_a.0.0.12.0 ()

 DIRECT    1  D Directory Utility

 ILEXER    1  D InLine Exerciser

 Task? ilexer

 dup: starting ILEXER on kdm70_a.0.0.12.0 ()

 ***

 *** ILEXER (InLine Exerciser) V 001  *** 17-NOV-1992 10:21:57 ***

 ***

 Enable Bad Block Replacement (Y/N) [N] ?

 Available Disk Drives: D0032 D0034 D0077

 Available Tape Drives: NONE

 Select next drive to test (Tnnnn/Dnnnn) [] ? d0032

 Write enable drive (Y/N) [N] ?

 *** Available tests are:

 1. Random I/O

 2. Seek Intensive I/O

 3. Data Intensive I/O

 4. Oscillatory Seek

 Select test number (1:4) [1] ?

 Select start block number (0:547040) [0] ?

 Select end block number (0:547040) [547040] ? 500

 Select data pattern number 0=ALL (0:15) [0] ?

 Select another drive (Y/N) [] ?

 *** No default is allowed.

 Select another drive (Y/N) [] ? n

 Select execution time limit, 0=Infinite, minutes (0:65535) [0] ? 1

 Select report interval, minutes (0:65535) [1] ? 1

 Select hard error limit (0:32) [0] ?

 Report soft errors (Y/N) [N] ? y

 Execution Performance Summary at 17-NOV-1992 10:23:57

 D0032    193832346     4315      9713        0      0      0      0

 Execution Performance Summary at 17-NOV-1992 10:23:57

 D0032 *  193832346     4320      9723        0      0      0      0

 ***

 *** ILEXER is exiting.

 ***

 Task?


Example: Running DEMNA Self-Test (Failing Case)

>>> set host demna0

Connecting to remote node, ^Y to disconnect.

t/r

RBDE> ST0/TR

;Selftest     3.00

; T0001 T0002 T0003 T0004 T0005 T0006 T0007 T0008 T0009 T0010

; T0011 T0012 T0013 T0014 T0015 T0016 T0017 T0018

;       F        E     0C03        1

;      HE    XNAGA       XX    T0018

;      03 00000000 0000A000 00000000 20150004 20051D97 08

;       F        E     0C03        1

;      HE    XNAGA       XX    T0018

;      05 00020000 80020000 00000000 20150204 200524A4 01

;       F        E     0C03        1

;00000000 00000002 00000000 00000000 00000000 00000000 00000000

RBDE> ^Y

>>>


Example: Running DEMNA Self-Test (Passing Case)

>>> set h demna0

Connecting to remote node, ^Y to disconnect.

t/r

RBDE> ST0/TR

;Selftest     3.00

; T0001 T0002 T0003 T0004 T0005 T0006 T0007 T0008 T0009 T0010

; T0011 T0012 T0013 T0014 T0015 T0016 T0017 T0018

;       P        E     0C03        1

;00000000 00000000 00000000 00000000 00000000 00000000 00000000

RBDE> ^Y

>>>


Example: Test System

P00>>> test -t 120

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting memory exerciser, running on kn7aa* (id #9c)

Starting memory exerciser, running on kn7aa* (id #c6)

Starting memory exerciser, running on kn7aa* (id #f3)

Starting memory exerciser, running on kn7aa* (id #122)

Starting memory exerciser, running on kn7aa* (id #151)

Starting memory exerciser, running on kn7aa* (id #1d0)

Starting device exerciser on dka1.1.0.1.2 (id #236) in READ-ONLY mode

Stopping device exerciser on dka1.1.0.1.2 (id #236)

Starting device exerciser on dka3.3.0.1.2 (id #28e) in READ-ONLY mode

Stopping device exerciser on dka3.3.0.1.2 (id #28e)

Starting device exerciser on due0.0.0.10.2 (id #2e6) in READ-ONLY mode

Stopping device exerciser on due0.0.0.10.2 (id #2e6)

Starting device exerciser on due1.0.0.10.2 (id #33e) in READ-ONLY mode

Stopping device exerciser on due1.0.0.10.2 (id #33e)

Stopping memory exerciser, running on kn7aa* (id #f3)

Stopping memory exerciser, running on kn7aa* (id #c6)

Stopping memory exerciser, running on kn7aa* (id #1d0)

Stopping memory exerciser, running on kn7aa* (id #122)

Stopping memory exerciser, running on kn7aa* (id #151)

Stopping memory exerciser, running on kn7aa* (id #9c)

Done testing...

P00>>>


Example: Write/Read/Compare Test of All Disks Not Associated with Controller a
Example: Write/Read/Compare Test of All Disks Not Associated with Controller "a"

P00>>> test -nowrite "dka*" -write -t 120

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Are you sure you want to perform writes to the selected disks? [yes/(no)] yes

User data on all selected devices may be lost. Continue? [yes/(no)] yes

Testing...

Starting memory exerciser, running on kn7aa* (id #9c)

Starting memory exerciser, running on kn7aa* (id #c6)

Starting memory exerciser, running on kn7aa* (id #f3)

Starting memory exerciser, running on kn7aa* (id #122)

Starting memory exerciser, running on kn7aa* (id #151)

Starting memory exerciser, running on kn7aa* (id #1d0)

Starting device exerciser on due0.0.0.10.2 (id #2e6) in WRITE/READ mode

Stopping device exerciser on due0.0.0.10.2 (id #2e6)

Starting device exerciser on due1.0.0.10.2 (id #33e) in WRITE/READ mode

Stopping device exerciser on due1.0.0.10.2 (id #33e)

Starting device exerciser on due2.0.0.10.2 (id #379) in WRITE/READ mode

Stopping device exerciser on due2.0.0.10.2 (id #379)

Starting device exerciser on due3.0.0.10.2 (id #3b1) in WRITE/READ mode

Stopping device exerciser on due3.0.0.10.2 (id #3b1)

Stopping memory exerciser, running on kn7aa* (id #f3)

Stopping memory exerciser, running on kn7aa* (id #c6)

Stopping memory exerciser, running on kn7aa* (id #1d0)

Stopping memory exerciser, running on kn7aa* (id #122)

Stopping memory exerciser, running on kn7aa* (id #151)

Stopping memory exerciser, running on kn7aa* (id #9c)

Done testing...

P00>>>


Example: Destructive Exercising Selected, Then Aborted

P00>>> test -w -n "dka*"

Configuring system...

polling for units on kzmsa0, slot 1, xmi0...

dka1.1.0.1.2       DKA300                    RRD42

dka3.3.0.1.2       DKA300                    RZ73

polling for units on kzmsa1, slot 9, xmi0...

polling for units on kdm700, slot 10, xmi0...

due0.0.0.10.2      DUE0                      RA70

due1.0.0.10.2      DUE1                      RA70

due2.0.0.10.2      DUE2                      RA70

due3.0.0.10.2      DUE3                      RA70

polling for units on demna0, slot 12, xmi0...

exa0.0.0.12.2: 08-00-2B-25-D6-4C

Default system exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Are you sure you want to perform writes to the selected disks? [yes/(no)] no

Testing aborted...

P00>>>


Example: Test Command - Quiet Qualifier Set

P00>>> test -q -t 300

Configuring system...

Default system exerciser selected for runtime of 300 seconds

Type Ctrl/C to abort...

Done testing...

P00>>>


Example: Detection of Memory Data Compare Error

>>> set d_report full

>>> test ms7aa*

Memory subsystem test selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting memory exerciser, running on kn7aa0 (id #aa)

Still testing...

Still testing...

*** Hard Error - Error #23 on FRU: kn7aa0,ms7aa1

Data compare error

      ID  Program         Device     Pass Hard/Soft Test     Time

-------- -------- -------------- -------- --------- ---- --------

000000aa   mem_ex         memory      433    1    0    4 10:23:51

Expected value: FFFFFFE0

Received value: FFF7FFE0

Failing addr:   047C87C8

*** End of Error ***

Testing aborted - halt-on-error selected...

Stopping memory exerciser on kn7aa0 (id #aa)

Done testing...

>>>


Example: Test Using Wildcard

>>> test dem*a*

Network exerciser selected for runtime of 120 seconds

Type Ctrl/C to abort...

Initializing demfa0

Initializing demna0

Initializing demna1

Self-test passed on device demfa0

Self-test passed on device demna0

Self-test passed on device demna1

Configuring demfa0

polling for units on demfa0, slot 5, xmi0...

fxa0.0.0.5.0: 08-00-2B-29-E0-FF

Configuring demna0

polling for units on demna0, slot 14, xmi0...

exa0.0.0.14.0: 08-00-2B-25-D7-C1

Configuring demna1

polling for units on demna1, slot 13, xmi1...

exb0.0.0.13.1: 08-00-2B-46-E8-84

Starting network exerciser on exa0.0.0.14.0 (id #144) in external loopback mode

Starting network exerciser on exb0.0.0.13.1 (id #187) in external loopback mode

Starting network exerciser on fxa0.0.0.5.0 (id #1b1) in external loopback mode

Stopping network exerciser on exa0.0.0.14.0 (id #144)

Stopping network exerciser on exb0.0.0.13.1 (id #187)

Stopping network exerciser on fxa0.0.0.5.0 (id #1b1)

Done testing...

>>>


Example: Test All Devices Associated with XMI0

>>> test xmi0 -omit demna1

XMI subsystem test selected for runtime of 120 seconds

Type Ctrl/C to abort...

Starting DWLMA exerciser on dwlma0

Stopping DWLMA exerciser on dwlma0

Initializing demna0

Initializing demfa0

Initializing kdm700

Self-test passed on device demna0

Self-test passed on device demfa0

Self-test passed on device kdm700

Configuring demna0

exa0.0.0.14.0: 08-00-2B-25-D7-C1

Configuring demfa0

fxa0.0.0.5.0: 08-00-2B-29-E0-FF

Configuring kdm700

polling for units on kdm700, slot 12, xmi0...

due0.0.0.12.0      DUE0                      RA70

due1.0.0.12.0      DUE1                      RA70

due2.0.0.12.0      DUE2                      RA70

due3.0.0.12.0      DUE3                      RA70

Starting network exerciser on exa0.0.0.14.0 (id #181) in external loopback mode

Starting network exerciser on fxa0.0.0.5.0 (id #192) in external loopback mode

Starting device exerciser on due0.0.0.12.0 (id #2e6) in READ-ONLY mode

Starting device exerciser on due1.0.0.12.0 (id #33e) in READ-ONLY mode

Starting device exerciser on due2.0.0.12.0 (id #379) in READ-ONLY mode

Starting device exerciser on due3.0.0.12.0 (id #3b1) in READ-ONLY mode

Stopping device exerciser on due0.0.0.12.0 (id #2e6)

Stopping device exerciser on due1.0.0.12.0 (id #33e)

Stopping device exerciser on due2.0.0.12.0 (id #379)

Stopping device exerciser on due3.0.0.12.0 (id #3b1)

Stopping network exerciser on exa0.0.0.14.0 (id #181)

Stopping network exerciser on fxa0.0.0.5.0 (id #192)

Done testing...

>>>


Example: Set Host Command -- Running DUP-Based Diagnostics and Utilities

>>> show device kdm700

polling for units on kdm700, slot 12, xmi0...

dua32.0.0.12.0     DUA32                     RA70

dua34.0.0.12.0     DUA34                     RA70

dua77.0.0.12.0     DUA77                     RA70

>>> set host -dup dua32.0.0.12.0

dup: starting DIRECT on kdm70_a.0.0.12.0 ()

 DIRECT    1  D Directory Utility

 ILEXER    1  D InLine Exerciser

 Task? ilexer

 dup: starting ILEXER on kdm70_a.0.0.12.0 ()

 ***

 *** ILEXER (InLine Exerciser) V 001  *** 17-NOV-1992 10:21:57 ***

 ***

 Enable Bad Block Replacement (Y/N) [N] ?

 Available Disk Drives: D0032 D0034 D0077

 Available Tape Drives: NONE

 Select next drive to test (Tnnnn/Dnnnn) [] ? d0032

 Write enable drive (Y/N) [N] ?

 *** Available tests are:

 1. Random I/O

 2. Seek Intensive I/O

 3. Data Intensive I/O

 4. Oscillatory Seek

 Select test number (1:4) [1] ?

 Select start block number (0:547040) [0] ?

 Select end block number (0:547040) [547040] ? 500

 Select data pattern number 0=ALL (0:15) [0] ?

 Select another drive (Y/N) [] ?

 *** No default is allowed.

 Select another drive (Y/N) [] ? n

 Select execution time limit, 0=Infinite, minutes (0:65535) [0] ? 1

 Select report interval, minutes (0:65535) [1] ? 1

 Select hard error limit (0:32) [0] ?

 Report soft errors (Y/N) [N] ? y

 Execution Performance Summary at 17-NOV-1992 10:23:57

 D0032    193832346     4315      9713        0      0      0      0

 Execution Performance Summary at 17-NOV-1992 10:23:57

 D0032 *  193832346     4320      9723        0      0      0      0

 ***

 *** ILEXER is exiting.

 ***

 Task?


Example: Running DEMNA Self-Test (Failing Case)

>>> set host demna0

Connecting to remote node, ^Y to disconnect.

t/r

RBDE> ST0/TR

;Selftest     3.00

; T0001 T0002 T0003 T0004 T0005 T0006 T0007 T0008 T0009 T0010

; T0011 T0012 T0013 T0014 T0015 T0016 T0017 T0018

;       F        E     0C03        1

;      HE    XNAGA       XX    T0018

;      03 00000000 0000A000 00000000 20150004 20051D97 08

;       F        E     0C03        1

;      HE    XNAGA       XX    T0018

;      05 00020000 80020000 00000000 20150204 200524A4 01

;       F        E     0C03        1

;00000000 00000002 00000000 00000000 00000000 00000000 00000000

RBDE> ^Y

>>>


Example: Running DEMNA Self-Test (Passing Case)

>>> set h demna0

Connecting to remote node, ^Y to disconnect.

t/r

RBDE> ST0/TR

;Selftest     3.00

; T0001 T0002 T0003 T0004 T0005 T0006 T0007 T0008 T0009 T0010

; T0011 T0012 T0013 T0014 T0015 T0016 T0017 T0018

;       P        E     0C03        1

;00000000 00000000 00000000 00000000 00000000 00000000 00000000

RBDE> ^Y

>>>


FRU Locations

These topics show the location of field-replaceable units in the following assemblies:

Cabinet Front

Cabinet Rear

Platform Cables

XMI Plug-In Unit

VAXBI Plug-In Unit

Futurebus+ Plug-In Unit

SCSI Disk and Tape Plug-In Unit

DSSI Disk Plug-In Unit

Battery Plug-In Unit


Cabinet Front

Click on the callout number for a description of the FRU.


Cabinet Front

1	70-28574-02	LSB centerplane and card cage
2	E2040	CPU module
3	E2043-AA or	Memory module 64 Mbytes
	E2043-BA or	Memory module 128 Mbytes
	E2043-CA or	Memory module 256 Mbytes
	E2046-AA	Memory module 512 Mbytes
4	54-20306-01	Control panel
5	30-33796-01 or	Power regulator
	30-33796-02
6	12-35173-01	Blower
7	DWLMA-xx or	XMI plug-in unit
	DWMBB-LA	VAXBI plug-in unit
8	BA655-AA or	SCSI disk plug-in unit
	BA654-AA	DSSI disk plug-in unit
9	H7237-AA	Battery plug-in unit


70-28574-02	LSB centerplane and card cage

Removal and replacement of the LSB centerplane and card cage requires access to both the front and the rear of the cabinet.

The LSB centerplane and card cage is located in the main cabinet only (cannot be located in the expander cabinet).


E2040	CPU module

The CPU module is located in the main cabinet only (cannot be located in the expander cabinet).


E2043-AA or	Memory module 64 Mbytes
E2043-BA or	Memory module 128 Mbytes
E2043-CA or	Memory module 256 Mbytes
E2046-AA	Memory module 512 Mbytes

Memory modules are located in the main cabinet only (cannot be located in the expander cabinet).

Memory modules can be located in either the front or the rear of the cabinet.


54-20306-01	Control panel

The control panel is located in the main cabinet only (cannot be located in the expander cabinet).


30-33796-01 or	Power regulator
30-33796-02

Removal and replacement of a power regulator requires access to both the front and the rear of the cabinet.


12-35173-01	Blower

Removal and replacement of the blower requires access to both the front and the rear of the cabinet.


DWLMA-xx or	XMI plug-in unit
DWMBB-LA	VAXBI plug-in unit

Removal and replacement of the XMI or VAXBI plug-in unit requires access to both the front and the rear of the cabinet.

For the correct part number of the XMI plug-in unit, replace -xx with -AA if it is located in the main cabinet or with -BA if it is located in the expander cabinet.


BA655-AA or	SCSI disk plug-in unit
BA654-AA	DSSI disk plug-in unit

The SCSI or DSSI disk plug-in unit can be located in either the front or the rear of the cabinet. It can be located in the bottom of the main cabinet or in the top or bottom of the expander cabinet.


H7237-AA	Battery plug-in unit

Removal and replacement of the battery plug-in unit requires access to both the front and the rear of the cabinet.


Cabinet Rear

Click on the callout number for a description of the FRU.


Cabinet Rear

1	70-28574-02	LSB centerplane and card cage
2	E2044-AA	IOP module
3	E2043-AA or	Memory module 64 Mbytes
	E2043-BA or	Memory module 128 Mbytes
	E2043-CA or	Memory module 256 Mbytes
	E2046-AA	Memory module 512 Mbytes
4	E2040	CPU module
5	54-20300-01	Cabinet control logic module (CCL)
6	RRD42	Removable media device
7	30-35143-01	DC distribution box
8	30-33798-01 or	AC input box
	30-33798-02 or
	30-33798-03
9	12-35173-01	Blower
10	DWLMA-xx or	XMI plug-in unit
	DWMBB-LA or	VAXBI plug-in unit
	DWLAA-xx	Futurebus+ plug-in unit
11	BA655-AA or	SCSI disk plug-in unit
	BA654-AA	DSSI disk plug-in unit
12	H7237-AA	Battery plug-in unit


70-28574-02	LSB centerplane and card cage

Removal and replacement of the LSB centerplane and card cage requires access to both the front and the rear of the cabinet.

The LSB centerplane and card cage is located in the main cabinet only (cannot be located in the expander cabinet).


E2044-AA	IOP module

The IOP module is located in the main cabinet only (cannot be located in the expander cabinet).


E2043-AA or	Memory module 64 Mbytes
E2043-BA or	Memory module 128 Mbytes
E2043-CA or	Memory module 256 Mbytes
E2046-AA	Memory module 512 Mbytes

Memory modules are located in the main cabinet only (cannot be located in the expander cabinet).

Memory modules can be located in either the front or the rear of the cabinet.


E2040	CPU module

The CPU module is located in the main cabinet only (cannot be located in the expander cabinet).


54-20300-01	Cabinet control logic module (CCL)


RRD42	Removable media device

Removal and replacement of the removable media device requires access to both the front and the rear of the cabinet.


30-35143-01	DC distribution box

Removal and replacement of the DC distribution box requires access to both the front and the rear of the cabinet.


30-33798-01 or	AC input box
30-33798-02 or
30-33798-03


12-35173-01	Blower

Removal and replacement of the blower requires access to both the front and the rear of the cabinet.


DWLMA-xx or	XMI plug-in unit
DWMBB-LA or	VAXBI plug-in unit
DWLAA-xx	Futurebus+ plug-in unit

Removal and replacement of the XMI or VAXBI plug-in unit requires access to both the front and the rear of the cabinet.

For the correct part number of the XMI or Futurebus+ plug-in unit, replace -xx with -AA if it is located in the main cabinet or with -BA if it is located in the expander cabinet.


BA655-AA or	SCSI disk plug-in unit
BA654-AA	DSSI disk plug-in unit

The SCSI or DSSI disk plug-in unit can be located in either the front or the rear of the cabinet. It can be located in the bottom of the main cabinet or in the top or bottom of the expander cabinet.


H7237-AA	Battery plug-in unit

Removal and replacement of the battery plug-in unit requires access to both the front and the rear of the cabinet.


Cables

Click on the callout number for a description of the cable.


Cables

1	17-03118-01	48V LSB power (gray)
2	17-03118-02	48V LSB power (yellow)
3	17-03119-01	48V power/signal to PIU
4	17-03127-01	48V to LDC
5	17-03126-01	48V power/sense to blower
6	17-03124-01	AC box to CCL signal
7	17-03120-01	Control panel to CCL signal
8	17-03123-01	LDC to CCL signal
9	17-03164-01	+5/+12 LDC to tape power
10	17-03121-01	CCL to LSB bulkhead signal
11	17-03122-01	LSB bulkhead to LSB backplane
12	17-03085-01	I/O cable, long (to expander cabinet -- 114 in)
13	17-03085-02	I/O cable, short (53 in)
14	17-03201-01	DEC power bus
15	BC10U-09	SCSI cable to RRD42
16	17-03443-01	LDC bulkhead power
17	17-03444-01	LDC bulkhead signal
18	17-03511-01	Control panel to CCL in expander cabinet


17-03118-01	48V LSB power (gray)


17-03118-02	48V LSB power (yellow)


17-03119-01	48V power/signal to PIU


17-03127-01	48V to LDC


17-03126-01	48V power/sense to blower


17-03124-01	AC box to CCL signal


17-03120-01	Control panel to CCL signal


17-03123-01	LDC to CCL signal


17-03164-01	+5/+12 LDC to tape power


17-03121-01	CCL to LSB bulkhead signal


17-03122-01	LSB bulkhead to LSB backplane


17-03085-01	I/O cable, long (to expander cabinet - 114 in)


17-03085-02	I/O cable, short (53 in)


17-03201-01	DEC power bus


BC10U-09	SCSI cable to RRD42


17-03443-01	LDC bulkhead power


17-03444-01	LDC bulkhead signal


17-03511-01	Control panel to CCL in expander cabinet


XMI Plug-In Unit

Click on the callout number for a description of the FRU.

NOTE: Only the front half of the XMI PIU enclosure is shown.


XMI Plug-In Unit

1	70-30396-01	XMI backplane assembly
2	30-36010-01	Module A (power regulator)
3	30-36009-01	Module B (power regulator)
4	T2028-AA	DWLMA module (LSB to XMI - slot 8)
5	T2030-YA	Clock and arbitration module (slot 7)
6	17-03162-01	Signal cable
7	17-03163-01	48V power cable
8	17-03202-01	Power distribution cable (rear of PIU enclosure, front half)
9	17-03416-01	+5VB jumper (rear of PIU enclosure, front half)
10	17-03533-01	Bulkhead to XMI signal (rear of PIU enclosure, front half)


70-30396-01	XMI backplane assembly

These FRUs can reside in any slot of the XMI backplane assembly except 7 or 8:

T2020-00	DEMNA XMI to NI controller
T2027-00	DEMFA XMI to FDDI controller
T2080-YA	CIXCD XMI to CI controller
T2029-AA	KZMSA XMI to SCSI controller
T2029-AC	KFMSB XMI to DSSI controller
A module with an XMI corner must be in slot 1 or 14. For more information, see the Platform Service Manual.

If a DWMBB-LA is installed, this FRU must be in slot 1:

T2018	DWMBB/A XMI to VAXBI controller

If a DWMBB-LB is installed, this FRU must be in slot 2:

T2018	DWMBB/A XMI to VAXBI controller


30-36010-01	Module A (power regulator)


30-36009-01	Module B (power regulator)


T2028-AA	DWLMA module (LSB to XMI - slot 8)


T2030-YA	Clock and arbitration module (slot 7)


17-03162-01	Signal cable


17-03163-01	48V power cable


17-03202-01	Power distribution cable (rear of PIU enclosure, front half)


17-03416-01	+5VB jumper (rear of PIU enclosure, front half)


17-03533-01	Bulkhead to XMI signal (rear of PIU enclosure, front half)


VAXBI Plug-In Unit

Click on the callout number for a description of the FRU.

NOTE: Only the front half of the VAXBI PIU enclosure is shown


VAXBI Plug-In Unit

1	70-24126-02	VAXBI backplane assembly
2	30-36010-01	Module A (power regulator)
3	30-36009-01	Module B (power regulator)
4	T1043	DWMBB/B module (XMI to VAXBI), slot 7
5	17-03162-01	Signal cable
6	17-03163-01	48V power cable
7	17-03202-01	Power distribution cable (rear of PIU enclosure, front half)


70-24126-02	VAXBI backplane assembly


30-36010-01	Module A (power regulator)


30-36009-01	Module B (power regulator)


T1043	DWMBB/B module (XMI to VAXBI), slot 7
If the PIU has an optional second VAXBI (DWMBB-LB), the second T1043 is in slot 1.


17-03162-01	Signal cable


17-03163-01	48V power cable


17-03202-01	Power distribution cable (rear of PIU enclosure, front half)


Futurebus+ Plug-In Unit

Click on the callout number for a description of the FRU.


Futurebus+ Plug-In Unit

1	54-21662-01	Futurebus+ backplane assembly
2	30-36011-01	Module A2 (power regulator)
3	30-36009-01	Module B (power regulator)
4	B2003-AA	DWLAA module (LSB to Futurebus+ -- slot 5)


54-21662-01	Futurebus+ backplane assembly


30-36011-01	Module A2 (power regulator)


30-36009-01	Module B (power regulator)


B2003-AA	DWLAA module (LSB to Futurebus+ -- slot 5)


SCSI Disk and Tape Plug-In Unit

Click on the callout number for a description of the FRU.


SCSI Disk and Tape Plug-In Unit

1	RZ73-VA or	Disk drive 5.25-inch (3 slots)
	RZ26-VA or	Disk drive 3.5-inch (1 slot)
	TLZ06-VA	Tape drive 3.5-inch (1 slot)
2	BA350-LA	Shelf
3	H7430-AA	Shelf power supply
4	17-03532-01	Power control/status signal cable


RZ73-VA or	Disk drive 5.25-inch (3 slots)
RZ26-VA or	Disk drive 3.5-inch (1 slot)
TLZ06-VA	Tape drive 3.5-inch (1 slot)


BA350-LA	Shelf


H7430-AA	Shelf power supply


17-03532-01	Power control/status signal cable


DSSI Disk Plug-In Unit

Click on the callout number for a description of the FRU.


DSSI Disk Plug-In Unit

1	SF73-LA	Disk brick
2	RF73-EA	Disk drive
	Includes these FRUs:
	54-19119-01	RF73-EA ECM module
	70-28814-01	RF73 HDA
3	54-20868-01	Local disk converter (LDC)
4	54-21664-01	Disk control panel
5	17-03417-01	RF73 signal cable
6	17-03418-01	LDC power cable
7	17-03419-01	LDC signal cable
8	17-03420-01	RF73 power cable
9	17-03423-01	Disk control panel to bulkhead cable
10	17-03424-01	DSSI bus cable
11	17-02382-0x	DSSI brick jumper cable (BC21Q-xx)
12	17-03422-01	Signal and power cable


SF73-LA	Disk brick


RF73-EA	Disk drive

Includes these FRUs:

54-19119-01	RF73-EA ECM module
70-28814-01	RF73 HDA

Each brick contains two disk drives.


54-20868-01	Local disk converter (LDC)

Each brick has one LDC.


54-21664-01	Disk control panel

Each brick has one disk control panel.


17-03417-01	RF73 signal cable

Each brick has one RF73 signal cable.


17-03418-01	LDC power cable

Each brick has one LDC power cable.


17-03419-01	LDC signal cable

Each brick has one LDC signal cable.


17-03420-01	RF73 power cable

Each brick has one RF73 power cable.


17-03423-01	Disk control panel to bulkhead cable

Each brick has one disk control panel to bulkhead cable.


17-03424-01	DSSI bus cable

Each brick has one DSSI bus cable.


17-02382-0x	DSSI brick jumper cable (BC21Q-xx)

This cable connects the bricks to each other.


17-03422-01	Signal and power cable

This cable runs up the center rear of the PIU enclosure.


Battery Plug-In Unit

Click on the callout number for a description of the FRU.

NOTE: The battery plug-in unit is shown without its enclosure.


Battery Plug-In Unit

1	H7238-AA	Battery block (contains four 12-36168-02 batteries)
2	12-39982-01	Fuse (LPN-RK-90)
3	17-03421-01	Battery sensor cable
4	17-03492-01	Intermediate cable, battery block A
5	17-03493-01	Intermediate cable, battery block B or C
6	17-03494-01	Power regulator A to battery block A
7	17-03494-02	Power regulator B to battery block B
8	17-03494-03	Power regulator C to battery block C


H7238-AA	Battery block (contains four 12-36168-02 batteries)


12-39982-01	Fuse (LPN-RK-90)


17-03421-01	Battery sensor cable


17-03492-01	Intermediate cable, battery block A


17-03493-01	Intermediate cable, battery block B or C


17-03494-01	Power regulator A to battery block A


17-03494-02	Power regulator B to battery block B


17-03494-03	Power regulator C to battery block C


Controls and Indicators

The topics in this section describe controls and indicators on these system components:

AC Input Box

Cabinet Control Logic Module

Control Panel

DSSI Disk PIU

DWLAA Module

DWLMA Module and Clock Card

IOP Module

KN7AA Processor Module

RRD42 Removable Media Device

SCSI Disk and Tape PIU

System Power Regulator

XMI, VAXBI, or Futurebus+ PIU Power Regulators


Control Panel


Control Panel Indicator Lights

Light	Color	State	Meaning
Key On	Green	On	Power supplied to entire system; blower running.
		Off	Power supplied only to CCL module.
Run	Green	On	Primary processor is running the operating system or user programs.
		Off	Primary processor is in console mode.
Fault	Yellow	On	Fault on LSB, XMI, or an I/O bus.
		Slow flash	Power sequencing in progress or airflow error.
		Fast flash	Power system error, airflow error, or detected transition to keyswitch in Disable position.
		Off	The system passed self-test.


RRD42 Removable Media Device


RRD42 CD Drive Control Panel

LED	State	Condition
Green	Off	No activity
(Activity)	On	Data is being transferred


KN7AA Processor Module

Self-test LEDs indicating defective DC-to-DC converter


Processor (E2040) LEDs After Self-Test

Test Result	Processor	LEDs
Self-test passed	Boot	STP, 0, and 1 are on. All others are off.
Self-test passed	Secondary	STP and 0 are on. All others are off.
Self-test failed	All	STP, 0, and 1 are off. Failing test number is in the top seven LEDs.

The failing test number is in binary-coded decimal. SROM CLK, 7, and 6 are the most significant digit of the test number; LEDs 5 through 2 are the least significant digit.

Number in LEDs	Test
1 -- 14	SROM self-tests 1-14
15 -- 50	GROM self-tests 15-50
51 -- 60	CPU/memory interaction tests 1-10
61 -- 67	Multiprocessor tests 1-7


Self-Test LEDs Indicating Defective DC-to-DC Converter

Processor Modules	Memory Modules	IOP Module	Defective Converter on This Module
One module's STP LED is off; all others are on.	All STP LEDs are on.	STP LED is off.	Processor module with STP LED off.
All STP LEDs are on.	One module's STP LED is off; all others are on.	STP LED is off.	Memory module with STP LED off.
All STP LEDs are on.	All STP LEDs are on.	STP LED is off.	IOP module.
Defective DC-to-DC Converter

Each module on the LSB has an on-board DC-to-DC converter. If the converter on any module is unable to supply +5V, the 2V reference voltage is disabled for all nodes, preventing any node from using the LSB. The table above indicates which module has the defective converter based on the state of the STP LEDs of all modules in the LSB.

Use this table when the Fault light on the control panel is on and the console prompt is displayed but the self-test map is not. This indicates that the LSB is good, but access to the bus is not possible.


IOP Module


IOP (E2044-AA) Module LED

Condition	Meaning
On	One of the following:
	• All IOP-specific and I/O adapter tests passed.
	• An I/O adapter test failed, and the error was isolated to the adapter.
Off	One of the following:
	• An IOP-specific test failed.
	• An I/O adapter test failed, and the error could not be isolated to the adapter.
	• The processor module failed.


Cabinet Control Logic Module


CCL Module LEDs

LED	Meaning
Power LED	Power is present on the CCL module.
PIU 1 -- 4	PIU is present and power is enabled to the regulators in the PIU quadrant indicated. (Q1 is to the left when viewing the cabinet from the front, Q2 is behind Q1, Q3 is in the front right, and Q4 is behind Q3.)

NOTE: Cabinet control logic modules prior to revision K04 included a pressure switch. Revisions K04 and after do not include that switch.


System Power Regulator


System Power Regulator Lights

Run Light (Green)	Fault Light (Yellow)	Meaning
Off	Off	No AC power
Off	On	Fatal fault
Fast flash	Off	AC power present and keyswitch in Disable position
On	Fast flash	Nonfatal fault or battery at end of life
On	Slow flash	Battery discharge mode
On	Off	Normal operation


AC Input Box


AC Input Box -- Indicators on Circuit Breaker

Color	Meaning
Red	Pole is in on position; not tripped.
Green	Pole is in off position or tripped due to an overload.

NOTE: In the 202V version (30-33798-03), all poles trip if one does, causing all indicators to turn green.


XMI, VAXBI, or Futurebus+ PIU Power Regulators


XMI, VAXBI, or Futurebus+ PIU Power Regulator Lights (Regulators A and B)

Light	Color	State	Meaning	Does light latch?
MOD OK	Green	On	Regulator is working.	No
		Off	Regulator is not working.
OC	Yellow	On	Overcurrent condition	Yes
OT	Yellow	On	Overtemperature condition	Yes
OV	Yellow	On	Overvoltage condition	Yes
48V	Green	On	48V is present.	No
XMI, VAXBI, or Futurebus+ PIU Power Switches (Regulator B)

Switch	Function
Reset	Momentary switch resets all lights on regulators A and B.
Enable/Disable	When this switch is in the Disable position, the output of both PIU power supplies is inhibited.


DWLMA Module and Clock Card


DWLMA (T2028-AA) Module LEDs

LED	Color	Desired Condition
STP -- Self-Test Passed	Yellow	On
DBGDIS -- Debug Disable	Green	On
POK -- Power OK	Green	On
FTLERR -- Fatal Error	Red	Off
ES -- Error Summary	Red	Off

The clock card, XMI node 7, has a yellow LED that lights to indicate that power is enabled in the XMI card cage. The POWER ENABLE H signal is looped through the clock card so that the XMI power system cannot be enabled unless the clock card is properly installed.


DWLAA Module


DWLAA Module LEDs

Fault LED (Yellow)	Run LED (Green)	Meaning
Off	Off	No power to module.
Off	On	Module has passed self-test and is operational on bus.
On	Off	Module is operational on bus but has detected a fatal error.
On	On	Self-test is in progress or has failed.


SCSI Disk and Tape PIU


SCSI Indicator LEDs

Indicator LED	LED State	Meaning

Disk Drive LEDs

Green	Off	No activity
	Flashing	Activity
	On	Activity
Yellow	Off	Normal
	Flashing	Spin up/spin down

Tape Drive LEDs

Green	Off	No tape
	Flashing	Self-test in progress or failed
	On	Normal
Yellow	Off	Write enable
	Flashing	Self-test in progress or failed
	On	Write protect

Power Supply LEDs

Green (left)	Off	Shelf fault
	On	Shelf OK
Green (right)	Off	Power fault
	On	Power OK


DSSI Disk PIU


Disk Brick Controls and Indicators

Control	Pushbutton Position	Light	Function
Power	In	On	DC power present
(Green)	Out	Off	DC power not present
Ready	In	On	ISE is on-line
(Green)	Out	Off	ISE is off-line
Wrt Prot	In	On	Write-protect enabled
(Yellow)	Out	Off	Write-protect disabled
Fault	Momentary	On	Fault condition
(Red)	switch	Off	Normal operation
		Slow flash	ISE calibrations in progress
		Fast flash	Disk control panel failure


Restoring Corrupted ROMs

The following descriptions tell you how to determine when to use each of these topics.

Restoring a Corrupted EEPROM

Use this section when the message "EEPROM image failed to verify" is displayed on the console terminal.

Restoring Corrupted Firmware on an Adapter

Use this section when an adapter fails self-test and the problem is corrupted firmware.

Restoring Corrupted Firmware on a CPU with the Update Command

Use this section when the message "Firmware image checksum error on CPU node n" is displayed after the console display.

Restoring Corrupted Frimware on a CPU with Flash ROM Recovery Code

Use this section when you power up the system and the prompt AXP-7000/10000-FRRC> is displayed on the console terminal.


Restoring a Corrupted EEPROM

Using the Build EEPROM Command to Restore a Corrupted EEPROM

EEPROM image failed to verify
EEPROM environment parameters not set up
Fail to update EEPROM envar on CPU 1

P00>>> build eeprom
Creating new EEPROM image
System Serial Number>               # Enter system serial number
Module Serial Number>               # Enter module serial number
Module Unified 2-5-2.4 Part Number> # Enter part number

P00>>> set cpu kn7aa1               # Move to next CPU (if corrupt)

P01>>> build eeprom
Creating new EEPROM image
System Serial Number>               # Enter system serial number

Module Serial Number>               # Enter module serial number
Module Unified 2-5-2.4 Part Number> # Enter part number

P01>>> initialize

NOTE: See Console Commands for more information on the console commands for the EEPROM.


Restoring Corrupted Firmware on an Adapter

If an adapter fails self-test, use this procedure to determine if the firmware is corrupted, and if it is, to update the firmware:

1	Boot LFU.

2	Use the LFU display or show command to indicate (by returning the mnemonic "unknown") if firmware has been corrupted.

3	Use the LFU update command to write the new firmware.

4	Exit.


Booting LFU

P00>>> show device

polling for units on kzmsa, slot 1, xmi0...
dka100.1.0.1.0      dka100          RRD42

P00>>> boot dka100.1.0.1.0
Booting...

            Copyright Digital Equipment Corporation

                             1992

                     All Rights Reserved.

  Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

          ***** Loadable Firmware Update Utility *****

            Version 2.1                  16-jun-1992

----------------------------------------------------------------
  Function      Description
----------------------------------------------------------------
  Display      Displays the system's configuration table.
  Exit         Return to loadable offline operating environment.
  List         Lists the device types and firmware revisions
               supported by this revision of LFU.
  Modify       Modifies port parameters and device attributes.
  Show         Displays device mnemonic, hardware and firmware
               revisions.
  Update       Replaces current firmware with loadable data
               image.
  Verify       Compares loadable and device images.
  ? or Help    Scrolls the function table.
----------------------------------------------------------------

Function?


Booting LFU

P00>>> show device

polling for units on kzmsa, slot 1, xmi0...
dka100.1.0.1.0      dka100          RRD42

P00>>> boot dka100.1.0.1.0
Booting...

            Copyright Digital Equipment Corporation

                             1992

                     All Rights Reserved.

  Loadable Environment Rev: V1.0-1625    Jul 12 1992  10:50:56

          ***** Loadable Firmware Update Utility *****

            Version 2.1                  16-jun-1992

----------------------------------------------------------------
  Function      Description
----------------------------------------------------------------
  Display      Displays the system's configuration table.
  Exit         Return to loadable offline operating environment.
  List         Lists the device types and firmware revisions
               supported by this revision of LFU.
  Modify       Modifies port parameters and device attributes.
  Show         Displays device mnemonic, hardware and firmware
               revisions.
  Update       Replaces current firmware with loadable data
               image.
  Verify       Compares loadable and device images.
  ? or Help    Scrolls the function table.
----------------------------------------------------------------

Function?


LFU Display and Show Commands

Function? disp

      Name   Type    Rev   Mnemonic  FW Rev   HW Rev

LSB

0+    KN7AA  (8001)  0000  kn7aa0                M

7+    MS7AA  (4000)  0000  ms7aa1

8+    IOP    (2000)  0001  iop0

C0 XMI                     xmi0

8+    DWLMA  (102A)  A5A6  dwlma0

C+    KDM70  (0C22)  1E11  kdm700     3.0

E+    DEMNA  (0C03)  0802  demna0     8.2

C1 XMI                     xmi1

1+    ?????  (0000)  0000  unknown0

8+    DWLMA  (102A)  A5A6  dwlma1

A+    CIXCD  (0C2F)  0111  cixcd0     1.0      A01

Function? sho *

               Firmware        Hardware

               Revision        Revision

kn7aa0  +      1.0                M

ms7aa0          --               --

iop0            --               --

dwlma0          --               --

kdm700         3.0         Cannot be read

demna0         8.2         Cannot be read

unknown0        --               --          Updates only.

cixcd0         1.0              A01

           '+' indicates the update firmware revision

               is greater than the adapter's firmware revision.

Function?


LFU Display and Show Commands

Function? disp

      Name   Type    Rev   Mnemonic  FW Rev   HW Rev

LSB

0+    KN7AA  (8001)  0000  kn7aa0                M

7+    MS7AA  (4000)  0000  ms7aa1

8+    IOP    (2000)  0001  iop0

C0 XMI                     xmi0

8+    DWLMA  (102A)  A5A6  dwlma0

C+    KDM70  (0C22)  1E11  kdm700     3.0

E+    DEMNA  (0C03)  0802  demna0     8.2

C1 XMI                     xmi1

1+    ?????  (0000)  0000  unknown0

8+    DWLMA  (102A)  A5A6  dwlma1

A+    CIXCD  (0C2F)  0111  cixcd0     1.0      A01

Function? sho *

               Firmware        Hardware

               Revision        Revision

kn7aa0  +      1.0                M

ms7aa0          --               --

iop0            --               --

dwlma0          --               --

kdm700         3.0         Cannot be read

demna0         8.2         Cannot be read

unknown0        --               --          Updates only.

cixcd0         1.0              A01

           '+' indicates the update firmware revision

               is greater than the adapter's firmware revision.

Function?


LFU Update Command

Function? update unknown0

Enter device name or 'exit' to skip this device.

Device name? cixcd

WARNING: updates may take several minutes to complete for each device

DO NOT ABORT!

unknown0 Updating to 1.0...Reading Device...Verifying 1.0...PASSED.

Function?


LFU Update Command

Function? update unknown0

Enter device name or 'exit' to skip this device.

Device name? cixcd

WARNING: updates may take several minutes to complete for each device

DO NOT ABORT!

unknown0 Updating to 1.0...Reading Device...Verifying 1.0...PASSED.

Function?


LFU Exit Command

Function? exit

Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  .  .  P  P  TYP
                     o  +  .  .  .  .  .  +  +  ST1
                     .  .  .  .  .  .  .  E  B  BPD
                     o  +  .  .  .  .  .  +  +  ST2
                     .  .  .  .  .  .  .  E  B  BPD
                     +  +  .  .  .  .  .  +  +  ST3
                     .  .  .  .  .  .  .  E  B  BPD

   .  .  .  .  +  .  +  .  +  .  .  .  +  .     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     .128  .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

P00>>>


LFU Exit Command

Function? exit

Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  .  .  P  P  TYP
                     o  +  .  .  .  .  .  +  +  ST1
                     .  .  .  .  .  .  .  E  B  BPD
                     o  +  .  .  .  .  .  +  +  ST2
                     .  .  .  .  .  .  .  E  B  BPD
                     +  +  .  .  .  .  .  +  +  ST3
                     .  .  .  .  .  .  .  E  B  BPD

   .  .  .  .  +  .  +  .  +  .  .  .  +  .     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     .128  .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

P00>>>


Restoring Corrupted Firmware on a CPU with the Update Command

The processor module in slot 3 in the following example has a corrupted GROM image. This is indicated by the D in the BDP lines and the message "Firmware image checksum error on CPU node 3." Use the console update command to update the firmware on the processor in node 3 from the boot processor's firmware.

Restoring Corrupted Firmware on a CPU with the Update Command

P00>>> init
Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  P  .  .  P  TYP
                     o  +  .  .  .  +  .  .  +  ST1
                     .  .  .  .  .  D  .  .  B  BPD
                     o  +  .  .  .  +  .  .  +  ST2

                     .  .  .  .  .  D  .  .  B  BPD
                     +  +  .  .  .  +  .  .  +  ST3
                     .  .  .  .  .  D  .  .  B  BPD

   +  +  +  .  .  .  +  .  .  .  .  +  +  +     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     . 128 .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567
Firmware image checksum error on CPU node 3
P00>>> update kn7aa1 -f
Update kn7aa1's FLASH ROMs [Y/(N)]? y
Updating kn7aa1's FLASH ROMs ............done
P00>>> update kn7aa1 -e
Update kn7aa1's EEPROM [Y/(N)]? y
Updating kn7aa1's EEPROM .........done
P00>>> init
Initializing...

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  P  .  .  P  TYP
                     o  +  .  .  .  +  .  .  +  ST1
                     .  .  .  .  .  E  .  .  B  BPD
                     o  +  .  .  .  +  .  .  +  ST2
                     .  .  .  .  .  E  .  .  B  BPD
                     +  +  .  .  .  +  .  .  +  ST3
                     .  .  .  .  .  E  .  .  B  BPD

   +  +  +  .  .  .  +  .  .  .  .  +  +  +     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     . 128 .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

P00>>>


Restoring Corrupted Firmware on a CPU with Flash ROM Recovery Code

Use this procedure if you see the prompt AXP-7000/10000-FRRC> at the console terminal after power-up. (This prompt appears only if the console terminal is set at 9600 baud.) This prompt indicates that the firmware in the FEPROMs on the processor module has been corrupted.

The following must be available before you can use this procedure:

•	A source system that can logically connect, through the console port, to the system that has the corrupted firmware.

•	The source system can be on site or remote.

•	The source system must have access to an RRD42 or an InfoServer.

•	The program Kermit must reside on the source system.

•	The AXP 7000 console CD-ROM. This CD-ROM includes the file AXP7000_10000_CONSOLE_IMAGE.GROM.

Do the following to restore the corrupted firmware. All work is done at the source system, and the procedure takes approximately 20-30 minutes.

1	Prepare the source system:

a	Set the speed of the terminal at which you are working to 9600 baud.

b	Bind the CD-ROM volume name to a virtual disk container.

c	Mount the InfoServer.

2	Make a physical connection from the source system to the system with the corrupted firmware. For example, use an RS232 cable to connect from a DMB32 on the source system to the console port on the system with the corrupted firmware.

3	Run Kermit and set the parameters as shown in the response to the show all command in the example.

4	Connect to the system with the corrupted firmware and downline load the correct code.


Preparing the Source System to Restore Corrupted Firmware on a CPU

$ set term/speed=9600/perm txa3:
$ mcr ess$ladcp
LADCP> bind AXP7000_V01
AXP7000_V01 is bound to DAD104
LADCP> exit
$ mount/ov=id dad104
$ dir dad104:[sys0.sysexe]

Directory DAD104:[SYS0.SYSEXE]

AXP7000_10000_CONSOLE_IMAGE.GROM


Running Kermit and Setting Parameters

$ kermit
Kermit-32> set file type binary
Kermit-32> set retry packet 5
Kermit-32> set send time 5
Kermit-32> show all
VMS Kermit-32 version 3.3.111

  Block check type	One character checksum
  Debugging	OFF
  Delay	5 (sec)
  Server sends NAKs every 75 seconds while waiting for a command
  Escape character	035 (octal)
  File type	BINARY
  File naming	Normal form
  Handshaking character	None
  Incomplete file disposition	Discard
  Line used	(Optional)
  Local echo	OFF
  Parity type	None

Retry maximums

  Initial connection	5 (dec)
  Sending a packet	5 (dec)

Send parameters

  Packet length	80 (dec)
  Padding length	0 (dec)
  Padding character	000 (octal)
  Time out	5 (sec)
  End of line character	015 (octal)
  Quoting character	043 (octal)
  Start of packet	001 (octal)

Receive parameters

  Packet length	80 (dec)
  Padding length	0 (dec)
  Padding character	000 (octal)
  Time out	5 (sec)
  End of line character	015 (octal)

  Quoting character	043 (octal)
  8-bit quoting character	046 (octal)
  Start of packet	001 (octal)

Transmit parameters

  Delay	0.0 (sec)
  Echo	OFF
  Repeat quoting character	176 (octal)


Downline Loading Code to Corrupted FEPROMs

Kermit-32> connect txa5:
AXP-7000/10000-FRRC> r	!Prepare system to receive
AXP-7000/10000-FRRC> Ctrl/] C	!Return to Kermit
Kermit-32> send dad104:[SYS0.SYSEXE]AXP7000_10000_console_image.grom
!Transmit code
Kermit-32> connect	!Reconnect to target system
AXP-7000/10000-FRRC> c	!Verify checksum of image
AXP-7000/10000-FRRC> p	!Copy program image to
!FEPROMs
AXP-7000/10000-FRRC> i	!Reset node
>>> Ctrl/] C	!Return to Kermit
Kermit-32> exit	!Return to DCL
$


System Errors

These topics include information on tools available for diagnosing system errors.

EEPROM Error Logs

System Error Logs


EEPROM Error Logs

The console command show eeprom diag_tdd can be used to identify the failing test when a processor fails during power-up.

Sample Show EEPROM Diag_TDD Output shows a failing processor in a multiprocessor system (the passing CPUs have been removed from the system) and how to identify the failed test by using this command.

Sample Multiple EEPROM Error Log Entries shows how to obtain multiple error log entries for a specific module.


Sample Show EEPROM Diag_TDD Output

>>> init
CPU00: Test Failure - Select primary CPU

F  E  D  C  B  A  9  8  7  6  5  4  3  2  1  0  NODE #
                     A  M  .  .  .  .  .  .  P  TYP
                     o  +  .  .  .  .  .  .  -  ST1
                     .  .  .  .  .  .  .  .  B  BPD
CPU00: Test Failure - Select primary CPU
                     o  +  .  .  .  .  .  .  -  ST2
                     .  .  .  .  .  .  .  .  B  BPD
CPU00: Test Failure - Select primary CPU
                     +  +  .  .  .  .  .  .  -  ST3
                     .  .  .  .  .  .  .  .  B  BPD

   .  .  .  .  +  .  +  .  +  .  .  .  +  .     C0 XMI +
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C1
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C2
   .  .  .  .  .  .  .  .  .  .  .  .  .  .     C3

                     . A0  .  .  .  .  .  .  .  ILV
                     .128  .  .  .  .  .  .  .  128MB

Firmware Rev = V1.0-1625 SROM Rev = V1.0-0 SYS SN = GAO1234567

>>>show eeprom diag_tdd

Diagnostic TDD Logging is enabled
Logging Control Field value = 0000
Actions logged = 1

Diagnostic TDD Log number 1
Diag = cpu_tst, SSN = GAO1234567,Detecting CPU Node = 1,Failing FRU Node = 1, Firmware Rev = V1.0-1625, Time = 01/20/93 23:28:04,
Test = 15,Mode = 1,Error Number = 1,Error Type  = 1,Error Count = 1
Data1/00000000FFFFFFFF,Data2/00000000FFFFFFFE,Data3/0000000000300000
>>>


Init

After removing the passing processors from the system, the user types the init command to power up the system.


Node ID

The message CPU00: Test Failure -- Select primary CPU prompts the user to enter the node ID of the failing processor. Note that the CPU node ID appears in the error message (CPU00). Type 0 to obtain the full console display. If you do not type the node ID when prompted, the processor continues to hang.

NOTE: The user input in response to the message is not echoed at the console terminal.


show eeprom diag_tdd

Type the command show eeprom diag_tdd to enable the diagnostic TDD error log. The error log header is displayed.


Test

The failing test number


Mode

The operating mode (0=user mode, 1=power-up mode)


Error Number

The failing error number


Error Type

The type of error that occurred (0=fatal, 1=hard, 2=soft)


Error Count

The number of errors that occurred


Data Fields

The fields show, in quadwords, the following:

Data1 -- the expected data

Data2 -- the received data

Data3 -- the failing address

These fields are used primarily for expected, received, and failing address information. However, data in these fields may vary according to various diagnostic reports.


Sample Multiple EEPROM Error Log Entries

P01>>> show seeprom diag_tdd ms7aa0
please wait ~1 min, reading ms7aa0

Diagnostic TDD Logging is enabled
OTF set
Logging Control Field value = 0000
Actions logged = 5

Diagnostic TDD Log number 1
Diag = cpumem, SSN = KS, Detecting CPU Node = 1, Failing FRU Node = 5,
Firmware Rev = X2.0-3290, Time = 01/24/82 21:05:11,
Test = 72, Mode = 1, Error Number = 28, Error Type = 1, Error Count = 1
Data1/0000000000000002, Data2/0000000000000000, Data3/0000000000000000

Diagnostic TDD Log number 2
Multiple FRU's identified for this error
Diag = mem_ex, SSN = KS, Detecting CPU Node = 1, Failing FRU Node = 5,
Firmware Rev = X2.0-3290, Time = 01/24/82 23:28:04,
Test = 2, Mode = 0, Error Number = 6, Error Type = 1, Error Count = 1
Data1/00000000AAAAAAAA, Data2/0000000055555555, Data3/0000000000A01E54

Diagnostic TDD Log number 3
Diag = cpumem, SSN = KS, Detecting CPU Node = 1, Failing FRU Node = 5,
Firmware Rev = X2.0-3290, Time = 01/24/82 21:04:12,
Test = 72, Mode = 1, Error Number = 28, Error Type = 1, Error Count = 1
Data1/0000000000000002, Data2/0000000000000000, Data3/0000000000000000

Diagnostic TDD Log number 4
Diag = cpumem, SSN = KS, Detecting CPU Node = 1, Failing FRU Node = 5,
Firmware Rev = X2.0-3290, Time = 01/24/82 21:05:02,
Test = 4, Mode = 1, Error Number = 1, Error Type = 1, Error Count = 1
Data1/AAAAAAAAAAAAAAAA, Data2/0000000000000000, Data3/000000000012BA80

Diagnostic TDD Log number 5
Diag = cpumem, SSN = KS, Detecting CPU Node = 2, Failing FRU Node = 5,
Firmware Rev = X2.0-3273, Time = 01/22/82 19:14:10,
Test = 4, Mode = 1, Error Number = 1, Error Type = 1, Error Count = 1
Data1/AAAAAAAAAAAAAAAA, Data2/0000000000000000, Data3/0000000000129100
P01>>>


show seeprom diag_tdd ms7aa0

The user types the command show seeprom diag_tdd ms7aa0.


Actions Logged

Five EEPROM error log actions are recorded for memory module ms7aa0, LSB node 5.


EEPROM Error Log Entries

Each EEPROM error log entry is displayed.


Console Prompt

The console prompt returns.


System Error Logs

Create an error log report with the command:

$ analyze/error_log

Error Log Entries

670 Machine Check Entry Packet

KN7AA Machine Check Frame

630 Machine Check Entry Packet

630 Machine Check Frame for OpenVMS AXP

630 Machine Check Frame for DEC OSF/1 AXP


Error Log Entries

Entry	Description
Mchk 670	Processor machine check -- This hard error is detected by the processor. Entries include backup cache probes, CPU fill ECC errors, and external LSB control-related errors.
Mchk 660	System machine check -- This hard error is detected by a component other than the processor. Entries include error conditions related to the operation of the backup cache (LSB side), the Gbus, or the LSB.
Mchk 660	IOP -- IPL 17 error. The IOP module detects errors on the LSB, vortex, and hoses. The IPCs (LSB interface chips) detect Up Vortex errors and LSB errors. The Up HIC (vortex-to-hose chips) detect Up Hose errors, and the Down HIC chips detect Down Hose errors.
Mchk 660	DWLMA -- IPL 17 error. The DWLMA module detects errors in the XMI, the Down Hose, and the Up Hose. The DWLMA detects two types of errors: those that are fatal to the system and those that can be reset.
Mchk 660	DWLAA -- IPL 17 error. The DWLAA module detects errors in the Futurebus+ and the Down Hose.
Mchk 660	Lastfail -- Last error(s) detected before the system terminates the session.
Mchk 660	Memscan -- Operating system poll of memory error registers shows an error.
Mchk 630	Processor correctable machine check -- This single-bit ECC (soft) error occurs when a primary cache fill is in progress. Entries include errors in data sourced from the backup cache and errors caused by the EDAL.


670 Machine Check Entry Packet


KN7AA Machine Check Frame


630 Machine Check Entry Packet


630 Machine Check Frame for OpenVMS AXP


630 Machine Check Frame for DEC OSF/1 AXP


Copyright

First Printing, March 1993

The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation.

Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies.

Copyright © 1993, 1994 by Digital Equipment Corporation.

All Rights Reserved.
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:

Alpha AXP	DECUS	VAXBI
AXP	DWMVA	VAXELN
DEC	OpenVMS	VMScluster
DECchip	ULTRIX	XMI
DEC LANcontroller	UNIBUS	The AXP logo
DECnet	VAX

OSF/1 is a registered trademark of the Open Software Foundation, Inc.

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to correct the interference.


Preface

Intended Audience

This manual is written for the Digital service engineer.

Conventions Used in This Document

Terminology. The DEC 7000 AXP systems use the Alpha AXP architecture. References in text use DEC 7000 to refer to DEC 7000 AXP systems.

Book titles. In text, if a book is cited without a product name, that book is part of the hardware documentation.

Command syntax. The text shown in command syntax uses these conventions:

•	Bold text indicates elements to be typed at the terminal.

•	Brackets ([]) indicate that an element is optional.

•	Braces ({}) indicate a choice from the enclosed list.

•	Angle brackets (<>) indicate that the enclosed text is not a literal depiction of the element but instead a reference to the kind of item that can appear in that position.

Icons. The icons shown below are used in illustrations for designating part placement in the system described. A shaded area in the icon shows the location of the component or part being discussed.

Document Titles

DEC 7000 Documentation lists the books in the DEC 7000 documentation set. Related Documents lists other documents that you may find useful.


DEC 7000 Documentation

Title	Order Number
Installation Kit	EK-7000B-DK
Site Preparation Guide	EK-7000B-SP
Installation Guide	EK-700EB-IN
Hardware User Information Kit	EK-7001B-DK
Operations Manual	EK-7000B-OP
Basic Troubleshooting	EK-7000B-TS
Service Information Kit-DEC 7000	EK-7002B-DK
Platform Service Manual	EK-7000A-SV
System Service Manual	EK-7002B-SV
Pocket Service Guide	EK-7700A-PG
Advanced Troubleshooting	EK-7701A-TS
Reference Manuals
Console Reference Manual	EK-70C0B-TM
KN7AA CPU Technical Manual	EK-KN7AA-TM
MS7AA Memory Technical Manual	EK-MS7AA-TM
I/O System Technical Manual	EK-70I0A-TM
Platform Technical Manual	EK-7000A-TM
Upgrade Manuals
KN7AA CPU Installation Card	EK-KN7AA-IN
MS7AA Memory Installation Card	EK-MS7AA-IN
KZMSA Adapter Installation Guide	EK-KXMSX-IN
DWLMA XMI PIU Installation Guide	EK-DWLMA-IN
DWMBB VAXBI PIU Installation Guide	EK-DWMBB-IN
H7237 Battery PIU Installation Guide	EK-H7237-IN
H7263 Power Regulator Installation Card	EK-H7263-IN
BA654 DSSI Disk PIU Installation Guide	EK-BA654-IN
BA655 SCSI Disk and Tape PIU Installation Guide	EK-BA655-IN
Removable Media Installation Guide	EK-TFRRD-IN


Related Documents

Title	Order Number
General Site Preparation
Site Environmental Preparation Guide	EK-CSEPG-MA
System I/O Options
BA350 Modular Storage Shelf Subsystem Configuration Guide	EK-BA350-CG
BA350 Modular Storage Shelf Subsystem User's Guide	EK-BA350-UG
BA350-LA Modular Storage Shelf User's Guide	EK-350LA-UG
CIXCD Interface User Guide	EK-CIXCD-UG
DEC FDDIcontroller 400 Installation/Problem Solving	EK-DEMFA-IP
DEC LANcontroller 400 Installation Guide	EK-DEMNA-IN
DEC LANcontroller 400 Technical Manual	EK-DEMNA-TM
DSSI VAXcluster Installation and Troubleshooting Manual	EK-410AA-MG
InfoServer 150 Installation and Owner's Guide	EK-INFSV-OM
KDM70 Controller User Guide	EK-KDM70-UG
RRD42 Disc Drive Owner's Manual	EK-RRD42-OM
RF Series Integrated Storage Element User Guide	EK-RF72D-UG
TLZ06 Cassette Tape Drive Owner's Manual	EK-TLZ06-OM
Operating System Manuals
Alpha Architecture Reference Manual	EY-L520E-DP
DEC OSF/1 Guide to System Administration	AA-PJU7A-TE
DECnet for OpenVMS Network Management Utilities	AA-PQYAA-TK
Guide to Installing DEC OSF/1	AA-PS2DA-TE
OpenVMS Alpha Version 1.0 Upgrade and Installation Manual	AA-PQYSA-TE
VMS Upgrade and Installation Supplement: VAX 7000-600 and VAX 10000-600 Series	AA-PRAHA-TE
VMS Network Control Program Manual	AA-LA50A-TE
VMSclusters and Networking
HSC Installation Manual	EK-HSCMN-IN
HSC Installation Manual	EK-SC008-UG
SC008 Star Coupler User's Guide
VAX Volume Shadowing Manual	AA-PBTVA-TE
Peripherals
Installing and Using the VT420 Video Terminal	EK-VT420-UG
LA75 Companion Printer Installation and User Guide	EK-LA75X-UG


Gbus$WHAMI<7>
Gbus$WHAMI<7>; REQ_MODE

Request Mode. (RO) Indicates the maximum number of CPU modules that this CPU module supports in a system:

Gbus$WHAMI <7>	CPUs Allowed in LSB Slots
0	0-3
1	0-7


Gbus$WHAMI<5>
Gbus$WHAMI<5>; LSB_CONWIN

LSB CONWIN. (RO) Reflects the inverted state of the LSB_CONWIN L backplane signal. When set, indicates that Gbus$LEDs<1> is clear (asserted) in one or more CPU modules.


Gbus$WHAMI<4>
Gbus$WHAMI<4>; LSB_BAD

LSB Bad. (RO) Reflects the inverted state of the LSB_BAD L backplane signal. When set, indicates that LSB_BAD L is driven by one or more CPU modules.


Gbus$WHAMI<3>
Gbus$WHAMI<3>; MFG

Manufacturing Status. (RO) Used by manufacturing.


Gbus$WHAMI<2:0>
Gbus$WHAMI<2:0>; NID

Node ID. (RO) Identifies the CPU module by the slot (0-7) where it resides.


Gbus$LEDs<7:3>
Gbus$LEDs<7:3>; LEDs_L

LEDs Low. (R/W) When a bit in this field is set, the associated LED signal is asserted low.


Gbus$LEDs<2>
Gbus$LEDs<2>; RUN_L

RUN Low. (R/W) When set, the associated LED signal is asserted low. The state of this bit also indicates whether the currently running software is the operating system (and not the diagnostic/console program).


Gbus$LEDs<1>
Gbus$LEDs<1>; CONWIN_L

CONWIN Low. (R/W) When set, the associated LED signal is asserted low. Also drives the backplane signal LSB_CONWIN L. The state of this signal can be read through the Gbus$WHAMI register.


Gbus$LEDs<0>
Gbus$LEDs<0>; STP_L

Self-Test Passed Low. (R/W) When set, the associated LED signal is asserted low.


Gbus$PMask<7:4>
Gbus$PMask<7:4>; RSVD

Reserved. (R/W, 1) Initialized to ones


Gbus$PMask<3>
Gbus$PMask<3>; PHALT_EN

Ctrl/P Halt Enable. (R/W, 1) When set, enables Ctrl/P characters received by the UART selected in the Select Console Terminal field of this register to halt the processor. The Halt Enable bit of this register must also be set for a Ctrl/P character to generate a halt.


Gbus$PMask<2:1>
Gbus$PMask<2:1>; SEL_CONS_TERM

Select Console Terminal. (R/W, 1) Selects one of three console terminals for Ctrl/P character detection:

Gbus$PMask <2:1>	Console Terminal Selected
00	UART0A (local terminal)
01	UART0B (Reserved)
10	UART1A (remote diagnostic control)
11	UART2A placed into module-level loopback mode. In this mode, the UART2A receive line is driven by the UART2A transmit line. PHALT_EN (bit <3> of this register) must be zero (Ctrl/P halts disabled) while modifying SEL_CONS_TERM to avoid erroneous halts.


Gbus$PMask<0>
Gbus$PMask<0>; HALT_EN

Halt Enable. (R/W, 1) When set, enables halts to the processor, including halts generated by LCNR<NHALT> or by detection of a Ctrl/P character received by a UART selected in the Select Console Terminal field of this register. When clear, all halts to the processor are disabled. PHALT_EN must also be set for Ctrl/P characters to generate a halt.


Gbus$Intr<7>
Gbus$Intr<7>; INTIM

Interval Timer. (RO, 0) When set, indicates that the watch chip is asserting its interval timer output.


Gbus$Intr<6>
Gbus$Intr<6>; IP

Interprocessor. (W1C, 0) When set, indicates that the LEVI-A chip has detected a write to the LIPINTR register with data selecting this node.


Gbus$Intr<5>
Gbus$Intr<5>; LSB2

LSB 2. (RO, 0) When set, indicates that the LEVI-A chip has an LSB level 2 interrupt pending.


Gbus$Intr<4>
Gbus$Intr<4>; RSVD

Reserved. (R0) Read as zero.


Gbus$Intr<3>
Gbus$Intr<3>; LSB1

LSB 1. (RO, 0) When set, indicates that the LEVI-A chip has an LSB level 1 interrupt pending.


Gbus$Intr<2>
Gbus$Intr<2>; LSB0

LSB 0. (RO, 0) When set, indicates that the LEVI-A chip has an LSB level 0 interrupt pending.


Gbus$Intr<1>
Gbus$Intr<1>; DUART1_INT

DUART1 Interrupt. (RO, 0) When set, indicates that either UART1A or UART1B is requesting an interrupt for the processor. This bit is cleared when all possible DUART1 interrupt sources are cleared.


Gbus$Intr<0>
Gbus$Intr<0>; DUART0_INT

DUART0 Interrupt. (RO, 0) When set, indicates that either UART0A or UART0B is requesting an interrupt for the processor. This bit is cleared when all possible DUART0 interrupt sources are cleared.


Gbus$Halt<7>
Gbus$Halt<7>; RSVD

Reserved. (R0) Read as zero.


Gbus$Halt<6>
Gbus$Halt<6>; Ctrl/P_HALT

Ctrl/P Halt. (W1C, 0) Set when a Ctrl/P character is received by the UART selected in the Gbus$PMask register.


Gbus$Halt<5>
Gbus$Halt<5>; PWR_MODB_OK

Power Module B Okay. (RO) Set when Power Module B of the I/O PIUs (plug-in unit) is working properly. Cleared when Module B fails.


Gbus$Halt<4>
Gbus$Halt<4>; PWR_MODA_OK

Power Module A Okay. (RO) Set when Power Module A of the I/O PIUs (plug-in unit) is working properly. Cleared when Module A fails.


Gbus$Halt<3>
Gbus$Halt<3>; LDC_PWR_OK

LDC Power Okay. (RO) Is set when all local disk converters (LDC) in the platform are working properly. Cleared when no LDCs are installed or when one or more of the LDCs fails.


Gbus$Halt<2>
Gbus$Halt<2>; LSB_SEC

LSB Secure. (RO) Reflects the inverted state of the backplane signal LSB_SECURE L. When set, indicates that the control panel keyswitch is in the Secure position and that Ctrl/P halts to the processor are disabled by hardware.


Gbus$Halt<1>
Gbus$Halt<1>; NHALT

Node Halt. (RO) Reflects the state of LCNR<NHALT>.


Gbus$Halt<0>
Gbus$Halt<0>; RSVD

Reserved. (R0) Read as zero.


Gbus$Misc<7:3>
Gbus$Misc<7:3>; RSVD

Reserved. (RO, 1) Initialized to ones.


Gbus$Misc<2>
Gbus$Misc<2>; BAD

Bad. (R/W, 1) When set, causes the module to drive LSB BAD which, in turn, lights the control panel fault LED. The state of this bit does not affect the Self-Test-Passed LED on the module or the STP bits in the Gbus$LEDs and LCNR registers. This bit allows software to assert LSB BAD on behalf of another system component. To determine if any module is driving LSB BAD, software should read Gbus$WHAMI<LSB_BAD>, not Gbus$Misc<BAD>.


Gbus$Misc<1:0>
Gbus$Misc<1:0>; EXPSEL

Expander Select. (R/W, 1) Selects which cabinet the power supply UART lines are logically connected to, and therefore, which of three 48V regulators are connected to the power supply lines:

Gbus$Misc <1:0>	Power Supply Connection
00	PS lines logically connected to main CPU cabinet.
01	PS lines logically connected to right expander cabinet.
10	PS lines logically connected to left expander cabinet.
11	PS transmit line is looped back to PS receive line.


LDEV<31:16>
LDEV<31:16>; DREV

Device Revision. (R/W, 0) Identifies the revision level of an LSB node. For the KN7AA CPU module, the value of this field is zero.


LDEV<15:0>
LDEV<15:0>; DTYPE

Device Type. (R/W, 0) Identifies the type of node. For the KN7AA CPU module, the value of this field is set to 8001 (hex).


LBER<31:19>
LBER<31:19>; RSVD

Reserved. (R0) Read as zero.


LBER<18>
LBER<18>; NSES

Node-Specific Error Summary. (R, 0) Set when an error condition is reported in the LMERR register.


LBER<17>
LBER<17>; CTCE

Control Transmit Check Error. (W1C, 0) Set when an LSB control line is driven incorrectly by the CPU module. When CTCE is set, ERR is asserted by the CPU module for one cycle.


LBER<16>
LBER<16>; DTCE

Data Transmit Check Error. (W1C, 0) Set when the CPU module detects an error while driving the D<127:0> and ECC<27:0> lines during a data or command cycle. When DTCE is set, ERR is asserted by the CPU module for one cycle.


LBER<15>
LBER<15>; DIE

Dirty Error. (W1C, 0) Set if the CPU module receives an asserted DIRTY signal during a cycle when DIRTY signals are not allowed. When DIE is set, ERR is asserted by the CPU module for one cycle.


LBER<14>
LBER<14>; SHE

Shared Error. (W1C, 0) Set if the CPU module receives an asserted SHARED signal during a cycle when SHARED signals are not allowed. When SHE is set, ERR is asserted by the CPU module for one cycle.


LBER<13>
LBER<13>; CAE

Command/Address Error. (W1C, 0) Set if the CPU module receives an asserted CA signal during a cycle when CA signals are not allowed. When CAE is set, ERR is asserted by the CPU module and error registers are locked.


LBER<12>
LBER<12>; NXAE

Nonexistent Address Error. (W1C, 0) Set when the CPU module does not receive confirmation for a command it sent on the LSB. When NXAE is set, ERR is asserted by the CPU module for one cycle.


LBER<11>
LBER<11>; CNFE

CNF Error. (W1C, 0) Set if the CPU module receives a confirmation signal during a cycle that does not permit confirmation. When CNFE is set, ERR is asserted by the CPU module for one cycle.


LBER<10>
LBER<10>; STE

STALL Error. (W1C, 0) Set when the CPU module receives a STALL signal during a cycle that does not permit stalls. When STE is set, ERR is asserted by the CPU module for one cycle.


LBER<9>
LBER<9>; TDE

Transmitter During Error. (W1C, 0) Set if a CE, UCE, CPE, or CDPE error occurs during a cycle when the CPU module was driving D<127:0>. When TDE is set, ERR is asserted by the CPU module for one cycle.


LBER<8>
LBER<8>; CDPE2

Second CSR Data Parity Error. (W1C, 0) Set when a second parity error occurs while CDPE is set on a CSR data cycle.


LBER<7>
LBER<7>; CDPE

CSR Data Parity Error. (W1C, 0) If a parity error occurs during a CSR data cycle, the CPU module sets CDPE, asserts ERR for one cycle, and locks the error registers.


LBER<6>
LBER<6>; CPE2

Second Command Parity Error. (W1C, 0) Set when a second parity error occurs on a command cycle while CPE is set.


LBER<5>
LBER<5>; CPE

Command Parity Error. (W1C, 0) If a parity error occurs on a command cycle, the CPU module sets CPE, asserts ERR for one cycle, and locks the error registers.


LBER<4>
LBER<4>; CE2

Second Correctable Data Error. (W1C, 0) Set when a second correctable ECC error occurs on a data cycle while CE is set.


LBER<3>
LBER<3>; CE

Correctable Data Error. (W1C, 0) If the CPU module detects an ECC error on the LSB, it sets CE, asserts ERR for one cycle, and locks the error registers.


LBER<2>
LBER<2>; UCE2

Second Uncorrectable Data Error. (W1C, 0) Set when the CPU module detects a second uncorrectable data error while UCE is set.


LBER<1>
LBER<1>; UCE

Uncorrectable Data Error. (W1C, 0) If the CPU module detects an uncorrectable ECC error on the LSB during a data cycle, it sets UCE, asserts ERR for one cycle, and locks the error registers.


LBER<0>
LBER<0>; E

Error. (W1C, 0) Set whenever the CPU module detects assertion of ERR on the LSB.


LCNR<31>
LCNR<31>; STF

Self-Test Fail. (W1C, 1) When set, indicates that this node has not yet completed self-test.


LCNR<30>
LCNR<30>; NRST

Node Reset. (W, 0) When set, the node enters console mode and undergoes a reset sequence.


LCNR<29>
LCNR<29>; NHALT

Node Halt. (R/W, 0) When set, a CPU node enters console mode.


LCNR<28>
LCNR<28>; RSTSTAT

Reset Status. (W1C, 0) When set, provides an indication to console software that a given CPU node should not attempt to become the boot processor, but should rather join an already running system. This bit is set when NRST (LCNR<30>) is set. It is cleared with a write of one, at system power-up, or with an LSB RESET command. This bit is not cleared in a reset sequence caused by setting NRST.


LCNR<27:1>
LCNR<27:1>; RSVD

Reserved. (R0) Read as zero.


LCNR<0>
LCNR<0>; CEEN

Correctable Error Detection Enable. (R/W, 0) When set, enables detection of correctable errors.


LMMR<31:17>
LMMR<31:17>; MODULE_ADDR

Module Address. (R/W) Specifies the most significant bits of the base address of the memory region spanned by the memory module associated with this register (LMMR0-LMMR7). These bits correspond to bits <39:25> of the byte address or D<34:20> of the command cycle.


LMMR<16:11>
LMMR<16:11>; RSVD

Reserved. (R0) Read as zero.


LMMR<10:9>
LMMR<10:9>; NBANKS

Number of Banks. (R/W) Specifies the number of individual memory banks (1, 2, 4, or 8) contained on the memory module associated with this register (LMMR0-7). The value of this field determines how many bits of the memory address (0, 1, 2, or 3) are inserted into the bank number.

LMMR <10:9>	Banks per Module	Bits in Bank Number
00	1	0
01	2	1
10	4	2
11	8	3


LMMR<8:5>
LMMR<8:5>; AW

Address Width. (R/W) Specifies the number of valid bits in MODULE_ADDR (LMMR<31:17>), starting from the MSB. The remaining bits of MODULE_ADDR are ignored.


LMMR<4:3>
LMMR<4:3>; IA

Interleave Address. (R/W) Specifies which interleave, within a group of interleaved modules, is served by the module associated with this register (LMMR0-7).


LMMR<2:1>
LMMR<2:1>; INT

Interleave. (R/W) Specifies the number of memory modules interleaved with this module (1, 2, or 4). This value determines the number of bits in the INT field (0, 1, or 2, starting from the LSB) that are compared to the LSBs of the memory address.

LMMR <2:1>	Modules Interleaved	Address Bits Compared
00	1	0
01	2	1
10	4	2
11	Reserved	Reserved


LMMR<0>
LMMR<0>; EN

Enable. (R/W) When set, indicates that the module associated with this register (LMMR0-7) is installed, and it is a memory module.


LBESR<31:7>
LBESR<31:7>; RSVD

Reserved. (R0) Read as zero.


LBESR<6:0>
LBESR<6:0>; SYND_0

Syndrome 0. (R) Syndrome computed from D<31:0> and ECC<6:0> during error cycle.


LBESR <6:0>
LBESR <6:0>; SYND_1

Syndrome 1. (R) Syndrome computed from D<63:32> and ECC<13:7> during error cycle.


LBESR <6:0>
LBESR <6:0>; SYND_2

Syndrome 2. (R) Syndrome computed from D<95:33> and ECC<20:14> during error cycle.


LBESR <6:0>
LBESR <6:0>; SYND_3

Syndrome 3. (R) Syndrome computed from D<127:96> and ECC<27:21> during error cycle.


Syndrome Values

A syndrome of zero indicates no ECC error for the given longword. The following table gives the syndromes for all single-bit errors. Any non-zero syndrome not listed in this table indicates a double-bit error.

Bit	Syndrome (Hex)	Bit	Syndrome (Hex)
Data<0>	4F	Data<20>	16
Data<1>	4A	Data<21>	19
Data<2>	52	Data<22>	1A
Data<3>	54	Data<23>	1C
Data<4>	57	Data<24>	62
Data<5>	58	Data<25>	64
Data<6>	5B	Data<26>	67
Data<7>	5D	Data<27>	68
Data<8>	23	Data<28>	6B
Data<9>	25	Data<29>	6D
Data<10>	26	Data<30>	70
Data<11>	29	Data<31>	75
Data<12>	2A	ECC<0>	01
Data<13>	2C	ECC<1>	02
Data<14>	31	ECC<2>	04
Data<15>	34	ECC<3>	08
Data<16>	0E	ECC<4>	10
Data<17>	0B	ECC<5>	20
Data<18>	13	ECC<6>	40
Data<19>	15


LBECR<31:0>
LBECR<31:0>; CA

Command/Address. (R) Contents of D<31:0> during the command cycle.


LBECR<31:20>
LBECR<31:20>; RSVD

Reserved. (R0) Read as zero.


LBECR<19:18>
LBECR<19:18>; DCYCLE

Data Cycle. (R) Indicates which data cycle had data error.

LBECR <19:18>	Data Cycle in Error
00	0
01	1
10	2
11	3


LBECR<17>
LBECR<17>; DIRTY

Dirty. (R) Set when DIRTY is asserted for the current command.


LBECR<16>
LBECR<16>; SHARED

Shared. (R) Set when SHARED is asserted for the current command.


LBECR<15>
LBECR<15>; CNF

Confirmation. (R) Set when CNF is asserted for the current command.


LBECR<14:11>
LBECR<14:11>; CID

Commander ID. (R) Contents of REQ<3:0> during command cycle.


LBECR<10:7>
LBECR<10:7>; CID3

Commander ID 3. (R) This field is the duplicate of CID (bits <14:11>). It reads the same as CID. In some early versions of the KN7AA module, CID3 reads as zero.


LBECR<6>
LBECR<6>; P

Parity. (R) Contents of D<38> during command cycle.


LBECR<5:3>
LBECR<5:3>; CMD

Command. (R) Contents of D<37:35> during command cycle. CMD is decoded as follows:

Command	Function
000	Read
001	Write
010	Reserved
011	Write Victim
100	Read CSR
101	Write CSR
110	Reserved
111	Private


LBECR<2:0>
LBECR<2:0>; CA

Command/Address. (R) Contents of D<34:32> during command cycle.


LIOINTR<31:16>
LIOINTR<31:16>; RSVD

Reserved. (R0) Read as zero.


LIOINTR<15:12>
LIOINTR<15:12>; CPU3

CPU3 I/O Interrupt. (W1S) When a bit is set in this field, an interrupt is posted to CPU3.


LIOINTR<11:8>
LIOINTR<11:8>; CPU2

CPU2 I/O Interrupt. (W1S) When a bit is set in this field, an interrupt is posted to CPU2.


LIOINTR<7:4>
LIOINTR<7:4>; CPU1

CPU1 I/O Interrupt. (W1S) When a bit is set in this field, an interrupt is posted to CPU1.


LIOINTR<3:0>
LIOINTR<3:0>; CPU0

CPU0 I/O Interrupt. (W1S) When a bit is set in this field, an interrupt is posted to CPU0.


LIPINTR<31:16>
LIPINTR<31:16>; RSVD

Reserved. (R0) Read as zero.


LIPINTR<15:0>
LIPINTR<15:0>; MASK

Interprocessor Interrupt Mask. (W1S, 0) When a given bit is set, an interprocessor interrupt is posted to a specific processor. Bits are mapped to specific CPUs within a multiprocessor system as follows:

LIPINTR Bits	DECchip 21064 CPU
<15:6>	Not used.
<5>	CPU5
<4>	CPU4
<3>	CPU3
<2>	CPU2
<1>	CPU1
<0>	CPU0


LMODE<31:17>
LMODE<31:17>; RSVD

Reserved. (R0) Read as zero.


LMODE<16>
LMODE<16>; LEVI_REV

LEVI Revision. (R, X) When clear, indicates pass 1 LEVI-A. When set, indicates pass 2 LEVI-A.


LMODE<15:11>
LMODE<15:11>; RSVD

Reserved. (R0) Read as zero.


LMODE<10>
LMODE<10>; CLR_LOCK

Clear Lock. (W, 0) When set, forces LEVI to deassert LSB_LOCKOUT and clear any relevant saved state irrespective of the state of LOCK_TIME, and so on.


LMODE<9:8>
LMODE<9:8>; STCOND_TO

Store Conditional Timeout. (R/W, 0) Unused on the KN7AA module. Should be written with zeros.


LMODE<7:6>
LMODE<7:6>; LOCK_MODE

Lock Mode. (R/W, 0) Unused on the KN7AA module. Should be written with zeros.


LMODE<5:4>
LMODE<5:4>; PMODE

P-Cache Mode. (R/W, 0) Allows LEVI to work with CPU chips with varying internal cache organizations. The value of this field for the KN7AA module is 01 (bin), which denotes an 8K D-cache and an 8K I-cache.


LMODE<3:2>
LMODE<3:2>; WMODE

Write Mode. (R/W, 0) Selects the behavior of LEVI in response to LSB writes.

LMODE<3:2>	LEVI Behavior
00	Use results of P-map lookup to determine invalidate/update.
01	Invalidate the B-cache.
10	Update the B-cache.
11	LEVI behavior undefined.


LMODE<1:0>
LMODE<1:0>; BSIZE

B-Cache Size. (R/W, 0) Tells LEVI about the size of the B-cache.

LMODE<1:0>	B-Cache Size
00	4 Mbytes
01	LEVI behavior undefined.
10	LEVI behavior undefined
11	LEVI behavior undefined


LMODE<31:20>
LMODE<31:20>; RSVD

Reserved. (R0) Read as zero.


LMODE<19:16>
LMODE<19:16>; LEVI_REV

LEVI Revision. (R, X) Indicate revision of LEVI-A.

LMODE<19:16>	LEVI Revision
0000	Pass 1 LEVI-A
0001	Pass 2 LEVI-A
0011	Pass 3 LEVI-A
All else	Reserved


LMODE<15>
LMODE<15>; RSVD

Reserved. (R0) Reads as zero.


LMODE<14>
LMODE<14>; LOCK_IN

Lock In. (R/W, 0) When set, LEVI-A asserts LSB LOCKOUT if LEVI-A signal R_CRD is asserted. This bit should be set along with LMODE<LOCK_ALL>. The use of LOCK_IN is intended for system debug only and should normally be cleared.


LMODE<13:12>
LMODE<13:12>; REQ_MODE

Request Mode. (R/W, 0) Determine the CPU module configurations by controlling the number of LSB REQ lines used by LEVI-A for arbitration. This field should allow no more than are allowed by Gbus$WHAMI<REQ_MODE>.

LMODE<13:12>	CPUs Allowed in LSB Slots
00	0 to 3
11	0 to 7
All else	Reserved


LMODE<11>
LMODE<11>; RSVD

Reserved. (R0) Read as zero.


LMODE<10>
LMODE<10>; CLR_LOCK

Clear Lock. (W, 0) When set, forces LEVI to deassert LSB_LOCKOUT and clear any relevant saved state irrespective of the state of LOCK_TIME, and so on.


LMODE<9:8>
LMODE<9:8>; STCOND_TO

Store Conditional Timeout. (R/W, 0) Unused on the KN7AA module. Should be written with zeros.


LMODE<7>
LMODE<7>; LOCK_MODE

Lock Mode. (R/W, 0) Unused on the KN7AA module. Should be written with zero.


LMODE<6>
LMODE<6>; LOCK_ALL

Lock All. (R/W, 0) When set, prevents all LSB transactions (except secondary and victim writes) if LSB LOCKOUT is asserted by another node. This bit should be set along with LMODE<LOCK_IN>. The use of LOCK_ALL is intended for debug only. This bit should normally be cleared.


LMODE<5:4>
LMODE<5:4>; PMODE

P-Cache Mode. (R/W, 0) Allows LEVI to work with CPU chips with varying internal cache organizations. The value of this field for the KN7AA module is 01 (bin), which denotes an 8K D-cache and an 8K I-cache.


LMODE<3:2>
LMODE<3:2>; WMODE

Write Mode. (R/W, 0) Selects the behavior of LEVI in response to LSB writes.

LMODE<3:2>	LEVI Behavior
00	Use results of P-map lookup to determine invalidate/update.
01	Invalidate the B-cache.
10	Update the B-cache.
11	LEVI behavior undefined.


LMODE<1:0>
LMODE<1:0>; BSIZE

B-Cache Size. (R/W, 0) Tells LEVI about the size of the B-cache.

LMODE<1:0>	B-Cache Size
00	4 Mbytes
01	1 Mbyte
10	16 Mbytes
11	LEVI behavior undefined.


LMERR<31:11>
LMERR<31:11>; RSVD

Reserved. (R0) Read as zero.


LMERR<10>
LMERR<10>; ARBDROP

Arbitration Drop. (W1C, 0) Set when the LEVI arbitration logic detects an LSB cycle in which a node has failed to assert a command after having gained access to the LSB bus. When ARBDROP is set, the LSB command and address are latched in the LBECR register.


LMERR<9>
LMERR<9>; ARBCOL

Arbitration Collision. (W1C, 0) Set when the LEVI arbitration logic detects an attempt to arbitrate for the LSB bus in an illegal time slot.


LMERR<8>
LMERR<8>; BDATADBE

B-Cache Data Double-Bit Error. (W1C, 0) When set, indicates that the LEVI chips have detected a double-bit ECC error when unloading the B-cache RAMs. This bit is set when data being transmitted on the LSB bus incurs a double-bit error. The address and the associated ECC syndrome are latched in the LBECR and LBESR registers, respectively.


LMERR<7>
LMERR<7>; BDATASBE

B-Cache Data Single-Bit Error. (W1C, 0) When set, indicates that the LEVI chips have detected a single-bit ECC error when unloading the B-data RAMs. This bit is set when data being transmitted on the LSB bus incurs a single-bit error. The address and the associated ECC syndrome are latched in the LBECR and LBESR registers, respectively.


LMERR<6>
LMERR<6>; BMAPPE

B-Map Parity Error. (W1C, 0) When set, indicates that the LEVI-A chip has detected bad parity when reading the B-map RAMs. The associated address is latched in the LBECR register.


LMERR<5>
LMERR<5>; BSTATPE

B-Cache Status Store Parity Error. (W1C, 0) When set, indicates that the LEVI-A chip has detected bad parity when reading the B-stat RAM. The associated address is latched in the LBECR register for LSB probes. For LEVI probes due to processor misses (LDx_L and so on), BIU_STAT<0> is set and the address is latched in the FILL_ADDR register.


LMERR<4>
LMERR<4>; BTAGPE

B-Cache Tag Store Parity Error. (W1C, 0) When set, indicates that the LEVI chips have detected bad parity when reading the B-tag RAMs. The associated address is latched in the LBECR register for LSB probes. For LEVI probes due to processor misses (LDx_L and so on), BIU_STAT<0> is set and the address is latched in the FILL_ADDR register.


LMERR<3:0>
LMERR<3:0>; PMAPPE

P-Map Parity Error. (W1C, 0) A bit is set in this field if the LEVI-A chip detects bad parity when reading one of the four internal P-map RAM structures. The associated address is latched in the LBECR register.


LLOCK<31>
LLOCK<31>; LOCK

Lock. (W1C, 0) When set, indicates that the LLOCK register contains a valid address used in the most recent memory space LDx_L instruction executed by the processor and that no LSB writes that reference the same 64-byte LSB block have occurred. This bit is used to determine the response to a subsequent STx_C instruction. Software can clear this bit explicitly with an LSB write to the 64-byte block referenced in LLOCK<28:1>.


LLOCK<30:29>
LLOCK<30:29>; RSVD

Reserved. (R0) Read as zero.


LLOCK<28:1>
LLOCK<28:1>; LADR

Lock Address. (R, 0) Lock address bits <33:6>.


LLOCK<0>
LLOCK<0>; RSVD

Reserved. (R0) Reads as zero.


LDIAG<31:11>
LDIAG<31:11>; RSVD

Reserved. (R0) Read as zero.


LDIAG<10:8>
LDIAG<10:8>; TAG_SEL

Tag Select. (R/W, 0) Specifies which tag store is to be read/written when Gbus$LtagRW is accessed.

LDIAG<10:8>	Tag Store Selected
100	B-cache
010	B-map
001	P-map
When LDIAG is being used to read a tag, only one bit in TAG_SEL is allowed to be set. If more than one bit is set in TAG_SEL when Gbus$LtagRW is written, all specified tags are written.


LDIAG<7>
LDIAG<7>; FRIGN

Force LSB Ignore. (R/W, 1) When set, forces the LEVI gate arrays to ignore all LSB bus traffic except transactions initiated by this node. When FRIGN transitions from set to clear, the LEVI gate array sets LSB ERR to allow all LSB arbitration to resync.


LDIAG<6>
LDIAG<6>; FBDP

Force Bad Data Parity. (R/W, 0) When set, forces the LEVI-A gate array to assert bad parity on the LSB during CSR data cycles.


LDIAG<5>
LDIAG<5>; FBCP

Force Bad Command Parity. (R/W, 0) When set, forces the LEVI-A gate array to assert bad parity on the LSB during CSR command cycles.


LDIAG<4>
LDIAG<4>; FDBE

Force Double-Bit Error. (R/W, 0) Allows a diagnostic program to force the LEVI gate arrays to load data into the B-cache with double-bit ECC errors. When set, LEVI inverts every ECC bit for each longword loaded into the B-cache from the LSB bus. This bit is only relevant when the LEVI gate arrays are loading the B-cache data store (fills).


LDIAG<3>
LDIAG<3>; FSBE

Force Single-Bit Error. (R/W, 0) Allows a diagnostic program to force the LEVI gate arrays to load data into the B-cache with single-bit ECC errors. When set, LEVI inverts one 	ECC bit for each longword loaded into the B-cache from the LSB bus. This bit is only relevant when the LEVI gate arrays are loading the B-cache data store (fills).


LDIAG<2>
LDIAG<2>; FSHARE

Force Share. (R/W, 0) When set, the LEVI-A chip responds to all LSB memory transactions from other nodes with assertion of SHARED.


LDIAG<1>
LDIAG<1>; FDIRTY

Force Dirty. (R/W, 0) When set, the LEVI-A chip responds to all LSB memory space read transactions that hit in the B-map with assertion of DIRTY and supplies the data from the B-cache to the LSB.


LDIAG<0>
LDIAG<0>; PMAP_DIS

P-Map Disable. (R/W, 0) On LEVI-A pass 3 chips, when set, disables the P-map and causes LEVI-A to behave as if all lockups hit in the P-map. This bit is don't care for earlier revisions of LEVI-A. It should be written with zero.


Diagnostic Notes

The following notes offer additional information for performing diagnostics on the CPU module.

How to Make the B-Cache Emulate Main Memory

The CPU module can be made to present its cache as main memory to the LSB environment by setting BIU_CTL<FHIT>, LDIAG<FDIRTY>, and LMODE<WMODE>=10 (binary). The selection of this mode is possible under the following two conditions: (1) Only a single CPU module is placed in this mode; (2) No memory module is present in the system.

How to Read/Write Tags

The combinations of LDIAG, LTAGA, LTAGW, and Gbus$LtagRW registers allow diagnostic programs or error recovery programs to read or write any tag store on the CPU module. LDIAG<TAG_SEL> selects the tag store of interest; LTAGA selects the location in the tag store; LTAGW supplies the value to be written into the tag; and Gbus$LtagRW provides the mechanism. The use of the Gbus register allows LEVI to perform the tag access without the need for any special setup (that is, FRIGN). Even though the Gbus registers are specified to be a byte in length, reads from Gbus$LtagRW return a full longword of data, since no physical Gbus location is actually being read. Gbus address space is used for convenience only.

Writing Tags

1	Write LDIAG<TAG_SEL> to select the tag store.

2	Write LTAGA to select the location.

3	Write LTAGW to specify the value to be written.

4	Write Gbus$LtagRW with any random data. This action triggers LEVI to perform the tag write as set up.

Reading Tags

1	Write LDIAG<TAG_SEL> to select the tag store.

2	Write LTAGA to select the location.

3	Read Gbus$LtagRW. This action triggers LEVI to perform the tag read as set up. The data returned is the value from the selected tag location in the format specified by the LTAGW register.


LTAGA<31:19>
LTAGA<31:19>; RSVD

Reserved. (R0) Read as zero.


LTAGA<18:0>
LTAGA<18:0>; TAG_ADDR

Tag Address. (R/W, 0) Specifies the location (tag address bits <23:5>) to be accessed in the tag store selected by LDIAG<TAG_SEL>.


LTAGW<31>
LTAGW<31>; RSVD

Reserved. (R0) Read as zero.


LTAGW<30>
LTAGW<30>; DIRTY

Dirty. (R/W, 0) Loaded into the Dirty field (if any) of the B-stat store specified in LDIAG<TAG_SEL> when WTAG (LDIAG<4>) is set.


LTAGW<29>
LTAGW<29>; SHARED

Shared. (R/W, 0) Loaded into the Shared field (if any) of the B-stat store specified in LDIAG<TAG_SEL> when WTAG (LDIAG<4>) is set.


LTAGW<28>
LTAGW<28>; VALID

Valid. (R/W, 0) Loaded into the Valid field (if any) of the B-stat store specified in LDIAG<TAG_SEL> when WTAG (LDIAG<4>) is set.


LTAGW<27>
LTAGW<27>; PMAPP

P-Map Parity. (R/W, 0) Specifies the value to be loaded in the B-map parity location when the Gbus$LtagRW register is written. PMAPP covers tag data bits <23:10> and the valid bit (even parity).


LTAGW<26>
LTAGW<26>; BMAPP

B-Map Parity. (R/W, 0) Specifies the value to be loaded in the B-map parity location when the Gbus$LtagRW register is written. BMAPP covers tag data bits <33:22> and the valid bit (even parity).


LTAGW<25>
LTAGW<25>; BSTATP

B-Stat Parity. (R/W, 0) Specifies the value to be loaded in the B-stat parity location when the Gbus$LtagRW register is written. BSTATP covers the Shared, Dirty, and Valid bits.


LTAGW<24>
LTAGW<24>; BTAGP

B-Tag Parity. (R/W, 0) Specifies the value to be loaded in the B-tag parity location when the Gbus$LtagRW register is written. BTAGP covers tag data bits <33:22> (even parity).


LTAGW<23:0>
LTAGW<23:0>; TAG_DATA

Tag Data. (R/W, 0) Loaded into the tag store specified in LDIAG<TAG_SEL> when the Gbus$LtagRW register is written. Mapping is performed as follows:

LTAGW<23:0>	Tag	RAM Structure
<23:12>	<33:22>	B-cache tag
<23:12>	<33:22>	B-map tag
<13:0>	<23:10>	P-map tag


LCON0<31:0>
LCON0<31:0>; CON_COM_DATA0

Console Communication Data 0. (R/W, 0) Data stored in the LCON0 register.


LCON1<31:0>
LCON1<31:0>; CON_COM_DATA1

Console Communication Data 1. (R/W, 0) Data stored in the LCON1 register.


LPERF<31:24>
LPERF<31:24>; N_MASK

Node Mask. (R/W, 0) When a bit is set in this field, LSB reads, LSB writes, or victim writes are counted for the associated node. The bits are in one-to-one correspondence, so that bit <31> is associated with node 7, bit <30> with node 6, and so on, except for bit <24>, which is associated with node 0 and the IOP. More than one bit may be set, allowing transactions from multiple nodes to be counted. This field applies to both LCNTR registers.


LPERF<23>
LPERF<23>; LC1_HLT

LCNTR1 Halt. (W, 0) Write one to disable LCNTR1 counting.


LPERF<22>
LPERF<22>; LC1_RUN

LCNTR1 Run. (W, 0) Write one to enable LCNTR1 counting.


LPERF<21>
LPERF<21>; RSVD

Reserved. (R0) Read as zero.


LPERF<20:16>
LPERF<20:16>; LC1_SEL

LCNTR1 Select. (R/W, 0) Selects event for the LCNTR1 register.

LPERF<20:16>	Event to Count in LCNTR1
00000	Misses due to reads
00001	Misses due to writes
00010	Misses due to shared blocks
00011	LDL_X instructions
00100	STC_X failures
00101	LSB B-map hits
00110	Bank conflict delays -LSB cycles
00111	Arbitration losses
01000	Victim buffer hits -wrapped only
01001	CSR reads
01010	CSR writes
01011	LMBPR writes
01100	LSB interrupts
01101	Gbus reads
01110	Gbus writes
01111	LSB reads -subject to node mask
10000	LSB writes -subject to node mask
10001	Victim writes -subject to node mask
10010	Stall cycles
10011	Total memory latency
10100	Carry out from LCNTR0
Other	Reserved
NOTE: When counting victim buffer hits, LC1_SEL = 01000 counts only hits for which LEVI has to swap (or wrap) the first and second hexwords to satisfy the read request in the proper order. LC0_SEL = 01000 counts all (wrapped or unwrapped) hits.


LPERF<15>
LPERF<15>; LC0_HLT

LCNTR0 Halt. (W, 0) Writing one disables LCNTR0 counting.


LPERF<14>
LPERF<14>; LC0_RUN

LCNTR0 Run. (W, 0) Writing one enables LCNTR0 counting.


LPERF<13>
LPERF<13>; RSVD

Reserved. (R0) Read as zero.


LPERF<12:8>
LPERF<12:8>; LC0_SEL

LCNTR0 Select. (R/W, 0) Selects event for the LCNTR0 register.

LPERF<12:8>	Event to Count in LCNTR0
00000	Misses due to reads
00001	Misses due to writes
00010	Misses due to shared blocks
00011	LDL_X instructions
00100	STC_X failures
00101	LSB B-map hits
00110	Bank conflict delays - LSB cycles
00111	Arbitration losses
01000	Victim buffer hits - wrapped or unwrapped
01001	CSR reads
01010	CSR writes
01011	LMBPR writes
01100	LSB interrupts
01101	Gbus reads
01110	Gbus writes
01111	LSB reads - subject to node mask
10000	LSB writes - subject to node mask
10001	Victim writes - subject to node mask
10010	Stall cycles
10011	Total memory latency
10100	Carry out from LCNTR1
Other	Reserved
When counting victim buffer hits, LC1_SEL = 01000 counts only hits for which LEVI has to swap (or wrap) the first and second hexwords to satisfy the read request in the proper order. LC0_SEL = 01000 counts all (wrapped or unwrapped) hits.


LPERF<7:4>
LPERF<7:4>; RSVD

Reserved. (R0) Read as zero.


LPERF<3:2>
LPERF<3:2>; MA_FREQ

Miss Address Frequency. (R/W, 0) Determines how often the LMISSADDR register loads the last miss address.

LPERF<3:2>	Miss Frequency
00	Load every 32nd miss address
01	Load every 64th miss address
10	Load every 128th miss address
11	Load every 256th miss address


LPERF<1>
LPERF<1>; LC1_OVFL

LCNTR1 Overflow. (R, 0) Records overflow from the LCNTR1 register. Clears when the LCNTR1 register is reset.


LPERF<0>
LPERF<0>; LC0_OVFL

LCNTR0 Overflow. (R, 0) Records overflow from the LCNTR0 register. Clears when the LCNTR0 register is reset.


LPERF<31:24>
LPERF<31:24>; N_MASK

Node Mask. (R/W, 0) When a bit is set in this field, LSB reads, LSB writes, or victim writes are counted for the associated node. The bits are in one-to-one correspondence, so that bit <31> is associated with node 7, bit <30> with node 6, and bit <24> for node 0. The IOP module (node 8) is associated with LPERF<4>. More than one bit may be set, allowing transactions from multiple nodes to be counted. This field applies to both LCNTR registers.


LPERF<23>
LPERF<23>; LC1_HLT

LCNTR1 Halt. (W, 0) Write one to disable LCNTR1 counting.


LPERF<22>
LPERF<22>; LC1_RUN

LCNTR1 Run. (W, 0) Write one to enable LCNTR1 counting.


LPERF<21>
LPERF<21>; RSVD

Reserved. (R0) Reads as zero.


LPERF<20:16>
LPERF<20:16>; LC1_SEL

LCNTR1 Select. (R/W, 0) Selects event for the LCNTR1 register.

LPERF<20:16>	Event to Count in LCNTR1
00000	Our node LSB read due to RBlock (miss)
00001	Our node LSB R/W due to WBlock (miss/shd)
00010	Our node LSB write due to WBlock (shared)
00011	Our node LDxL requests (hit or miss)
00100	Our node STxC failures (hit, miss, or shared)
00101	Another node write this B-map hit
00110	Bank conflict delays-complex
00111	Arbitration losses-complex
01000	Other node LSB read, this VB hit (wrapped)
01001	Our node LSB READ_CSR
01010	Our node LSB WRT_CSR
01011	Our node LSB WRT_CSR to LMBPR (mailbx)
01100	Any node WRT_CSR to broadcast space
01101	Our node RBlock to Gbus space
01110	Our node WBlock to Gbus space
01111	LSB reads -subject to N_MASK<8:0>
10000	LSB writes -subject to N_MASK<8:0>
10001	Victim writes -subject to N_MASK<8:0>
10010	LSB cycles with STALL asserted
10011	Total memory latency-complex
10100	Carry out from LCNTR0
10101	All LSB cmds (subject to N_MASK<8:0>
10110	LSB cycles without STALL asserted
10111	LSB cycles (all)
11000	Mem-space RBlk assert time (RBlk latency)
11001	Mem-space WBlk assert time (WBlk latency)
11010	Mem-space LDxL assert time (LDxL latency)
11011	Mem-space STxC assert time (STxC latency)
11100	Our node LSB READ due to LDxL (miss)
11101	Our node LSB R/W due to STxC (miss o shrd)
11110	Our node STxC requests (hit, miss, shrd, fail)
11111	Our node MB requests (Barrier)
When counting victim buffer hits, LC1_SEL = 01000 counts only hits for which LEVI has to swap (or wrap) the first and second hexwords to satisfy the read request in the proper order. LC0_SEL = 01000 counts all (wrapped or unwrapped) hits.


LPERF<15>
LPERF<15>; LC0_HLT

LCNTR0 Halt. (W, 0) Writing one disables LCNTR0 counting.


LPERF<14>
LPERF<14>; LC0_RUN

LCNTR0 Run. (W, 0) Writing one enables LCNTR0 counting.


LPERF<13>
LPERF<13>; RSVD

Reserved. (R0) Read as zero.


LPERF<12:8>
LPERF<12:8>; LC0_SEL

LCNTR0 Select. (R/W, 0) Selects event for the LCNTR0 register.

LPERF<12:8>	Event to Count in LCNTR0
00000	Our node LSB read due to RBlock (miss)
00001	Our node LSB R/W due to WBlock (miss/shd)
00010	Our node LSB write due to WBlock (shared)
00011	Our node LDxL requests (hit or miss)
00100	Our node STxC failures (hit, miss, or shared)
00101	Another node write this B-map hit
00110	Bank conflict delays-complex
00111	Arbitration losses-complex
01000	Other node LSB read, this VB hit
01001	Our node LSB READ_CSR
01010	Our node LSB WRT_CSR
01011	Our node LSB WRT_CSR to LMBPR (mailbx)
01100	Any node WRT_CSR to broadcast space
01101	Our node RBlock to Gbus space
01110	Our node WBlock to Gbus space
01111	LSB reads -from any node
10000	LSB writes -from any node
10001	Victim writes -from any node
10010	LSB cycles with STALL asserted
10011	Total memory latency-complex
10100	Carry out from LCNTR1
10101	All LSB cmds (from any node
10110	LSB cycles without STALL asserted
10111	LSB cycles (all)
11000	Mem-space RBlk assert time (RBlk latency)
11001	Mem-space WBlk assert time (WBlk latency)
11010	Mem-space LDxL assert time (LDxL latency)
11011	Mem-space STxC assert time (STxC latency)
11100	Our node LSB READ due to LDxL (miss)
11101	Our node LSB R/W due to STxC (miss or shd)
11110	Our node STxC requests (hit, miss, shrd, fail)
11111	Our node MB requests (Barrier)
When counting victim buffer hits, LC1_SEL = 01000 counts only hits for which LEVI has to swap (or wrap) the first and second hexwords to satisfy the read request in the proper order. LC0_SEL = 01000 counts all (wrapped or unwrapped) hits.


LPERF<7:5>
LPERF<7:5>; RSVD

Reserved. (R0) Read as zero.


LPERF<4>
LPERF<4>; N_MASK<8>

Node Mask<8>. (R/W, 0) When set, LCNTR1 counts node masked events from node 8, the IOP. This bit is an extension of the N_MASK field (LPERF<34:24>).


LPERF<3:2>
LPERF<3:2>; MA_FREQ

Miss Address Frequency. (R/W, 0) Determines how often the LMISSADDR register loads the last miss address.

LPERF<3:2>	Miss Frequency
00	Load every 32nd miss address
01	Load every 64th miss address
10	Load every miss address
11	Load every 256th miss address


LPERF<1>
LPERF<1>; LC1_OVFL

LCNTR1 Overflow. (R, 0) Records overflow from the LCNTR1 register. Clears when the LCNTR1 register is reset.


LPERF<0>
LPERF<0>; LC0_OVFL

LCNTR0 Overflow. (R, 0) Records overflow from the LCNTR0 register. Clears when the LCNTR0 register is reset.


LCNTR0<31:0>
LCNTR0<31:0>; EV_COUNT0

Event Count 0. (R, 0) Number of events (selected through LPERF<LC0_SEL>) that occurred while LCNTR0 was enabled. Writes are ignored.


LCNTR1<31:0>
LCNTR1<31:0>; EV_COUNT1

Event Count 1. (R, 0) Number of events (selected through LPERF<LC1_SEL>) that occurred while LCNTR1 was enabled. Writes are ignored.


LMISSADDR<31:29>
LMISSADDR<31:29>; RSVD

Reserved. (R0) Read as zero.


LMISSADDR<28:0>
LMISSADDR<28:0>; MISS_ADDR

Missed Address. (R/W, 0) Block address of one of the last n B-cache misses. LPERF<MA_FREQ> determines the value of n.


LMISSADDR<31>
LMISSADDR<31>; NEW_SAMPLE

New Sample. (R0) Set every time a new address is loaded into the LMISSADDR register; cleared after the register is read.


LMISSADDR<30:29>
LMISSADDR<30:29>; MISS_CMD

Miss Command. (R) Indicates how the B-cache miss was generated.

LMISSADDR<30:29>	Miss Command
00	I-stream read miss: LSB read due to an I-stream RBlock or LDxL.
01	D-stream read miss: LSB read due to a D-stream RBlock or LDxL.
10	Write miss: LSB read due to WBlock or STxC.
11	Write to shared block: LSB write due to WBlock or STxC.


LMISSADDR<28:0>
LMISSADDR<28:0>; MISS_ADDR

Miss Address. (R) Block address of one of the last n B-cache misses. LPERF<MA_FREQ> determines the value of n.


FINT<31:16>
FINT<31:16>; RSVD

Reserved. (MBZ) Must be zero.


FINT<15:0>
FINT<15:0>; VECTOR

Vector. (R/W) This field is loaded with the vector pointing to the error interrupt service routine. The information is written by the operating system.


NID<31:16>
NID<31:16>; RSVD

Reserved. (MBZ) Must be zero.


NID<15:6>
NID<15:6>; BUS_ADDRESS

Bus Address. (R/W) Contains the Futurebus+ address of the DWLAA used when receiving read responses. The default is 102310.


NID<5:1>
NID<5:1>; GEOGRAPHICAL_ADDRESS

Geographical Address. (RO) Equivalent to the inverse of the GA<4:0> lines from the Futurebus+.


NID<0>
NID<0>; NODE_SIDE

Node Side. (RO) A Futurebus+ slot can contain a module that has two nodes on it. This bit is used to state whether the module has one node on it or two. If the bit is clear, there is one node on the module and if it is set, there are two. For the DWLAA the bit is clear.


STO<31>
STO<31>; RSVD

MBZ	Reserved. Must be zero.


STO<30:24>
STO<30:24>; STOVAL

Split Timeout Value. (R/W) The split timeout value can be set from 4.1 to 520.2 milliseconds. If all bits are clear, the timeout is infinite.


STO<23:0>
STO<23:0>; RSVD

Reserved. (MBZ) Must be zero.


ERRHI<31>
ERRHI<31>; ERR_SUM

Error Summary. (RO) The Error Summary bit sets whenever NXA, CMD_PE, DA_PE, USE, PROTO_ERR, or NXTID is set.


ERRHI<30>
ERRHI<30>; MASTER

Master. (RO) The Master bit is set if the DWLAA was the Futurebus+ master during the transaction that incurred an error. When ERR_SUM is cleared, this bit is cleared.


ERRHI<29>
ERRHI<29>; CON_PHASE

Connect Phase. (RO) If an error is detected during a connect phase, this bit is set. When ERR_SUM is cleared, this bit is cleared. (Applies when DWLAA is master, slave, or selected slave.)


ERRHI<28>
ERRHI<28>; DATA_PHASE

Data Phase. RO If an error is detected during a data phase of a Futurebus+ transaction, this bit is set. When ERR_SUM is cleared this bit is cleared. (Applies when master or selected slave.)


ERRHI<27>
ERRHI<27>; DISCON_PHASE

Disconnect Phase. (RO) If an error is detected during a connect phase of a Futurebus+ transaction, this bit is set. When ERR_SUM is cleared, this bit is cleared. (Applies when master, slave, or selected slave.)


ERRHI<26>
ERRHI<26>; NXA

Nonexistent Address. (W1C) This bit is set indicating that no node responded during the connect phase of a Futurebus+ transaction.


ERRHI<25>
ERRHI<25>; RSVD

Reserved. (RAZ) Must be zero.


ERRHI<24>
ERRHI<24>; CMD_PE

Command Parity Error. (W1C) This bit sets indicating that a parity error has occurred during a Futurebus+ transaction. (Applies when slave or selected slave.)


ERRHI<23>
ERRHI<23>; DA_PE

Data/Address Parity Error. (W1C) DA_PE sets indicating that a parity error has occurred during a Futurebus+ command/address transaction. (Applies when master, slave, or selected slave.)


ERRHI<22>
ERRHI<22>; PROTO_ERR

Protocol Error. (W1C) PROTO_ERR sets if an illegal operation or capability error is detected on a Futurebus+ transaction. (Applies when master, slave, or selected slave.)


ERRHI<21:20>
ERRHI<21:20>; RSVD

Reserved. (RAZ) Must be zero.


ERRHI<19>
ERRHI<19>; USE

Unit Specific Error. (W1C) USE sets if the master or the selected slave detects a unit-specific error during a Futurebus+ transaction.


ERRHI<18:16>
ERRHI<18:16>; CAP_LINES

Capability Lines. (RO) The CAP_LINES bits are loaded with the state of the capability lines by the selected slave or slave when the error occurs or by the master during the connect phase. If the error is logged during the slave connect phase, ERRHI<18> holds the value of the last slave/master transaction. These bits clear when ERR_SUM is cleared.


ERRHI<15:8>
ERRHI<15:8>; STATUS_FIELD

Status Field. (RO) The Status Field bits are loaded from ST<7:0> at the time the error is detected when the DWLAA is master. If the error occurs when the DWLAA is a slave, these bits equal the last master value. These bits clear when ERR_SUM is cleared.


ERRHI<7:0>
ERRHI<7:0>; COMMAND_FIELD

Command Field. (RO) The Command Field bits are loaded from CM<7:0> at the time the error is detected when the DWLAA is the slave. If the error occurs when the DWLAA is master, these bits equal the last slave value. These bits clear when ERR_SUM is cleared.


ERRLO<31:1>
ERRLO<31:1>; RSVD

Reserved. (RAZ) Must be zero.


ERRLO<0>
ERRLO<0>; NXTID

Nonexistent Transaction ID. (W1C) A nonexistent transaction ID error occurs when the DWLAA is selected to respond to some unidentified node on the Futurebus+. NXTID sets when this type of error occurs.


FADRHI<31:0>
FADRHI<31:0>; ADDR

High Address Bits. (RO) This register latches the high address bits of the Futurebus+ during the connect phase of Futurebus+ transactions. Interpretation of the address depends upon the state of the ERR_SUM bit and whether the DWLAA was master when an error occurred.


FADRLO<31:0>
FADRLO<31:0>; ADDR

Low Address Bits. (RO) This register latches the high address bits of the Futurebus+ during the connect phase of Futurebus+ transactions. Interpretation of the address depends upon the state of the ERR_SUM bit and whether the DWLAA was master when an error occurred.


TTO<31:21>
TTO<31:21>; RSVD

Reserved. (RAZ) Must be zero.


TTO<20:17>
TTO<20:17>; TTOVAL

Timeout Value. (R/W) TTO value gives a timeout range from 32.33 ms to 480.48 ms with a 5% maximum tolerance of the value set. If TTOVAL is zero, the timeout is infinite.


TTO16:0>
TTO<16:0>; RSVD

Reserved. (RAZ) Must be zero.


BZRTRY<31:28>
BZRTRY<31:28>; RSVD

Reserved. (RAZ) Must be zero.


BZRTRY<27:15>
BZRTRY<27:15>; RETDLY

Retry Delay. (R/W) The Retry Delay value determines the amount of time the DWLAA waits after busy status is returned before retrying. The range is from 8 ms to 65.53 ms. The default is 2.05 ms. If RETDLY is set to 0, the retry is immediate. The retry value is calculated as the binary value of a 28-bit field that assumes bits <14:0> are set times 233 picoseconds.


BZRTRY<14:10>
BZRTRY<14:10>; RSVD

Reserved. (RAZ) Must be zero.


BZRTRY<9:0>
BZRTRY<9:0>; BRT

Retry Threshold. (R/W) The value of BRT determines the number of retries the DWLAA does before timing out. The range is from 0 to 1,023, and the default is 64. The value is equal to the binary count of the field.


FCTL<31:20>
FCTL<31:20>; RSVD

Reserved. (RAZ) Must be zero.


FCTL<19>
FCTL<19>; ENUPRST

Up Hose Reset Enable. (RO) The ENUPRST bit reflects the status of the DWLAA module stake pin. When the jumper is installed, ENUPRST is disabled. When the jumper is removed, provided the CSRBEN bit is set, a remote boot is allowed.


FCTL<18>
FCTL<18>; CSRRBEN

CSR Remote Boot Enable. (R/W) When set (enabled), allows a remote boot provided the ENUPRST bit is also set. Loaded with its default at power-up (but not system reset). The default is set.


FCTL<17>
FCTL<17>; MEMDECEN

Memory Decode Enable. (R/W) When set (enabled), enables DWLAA to decode an LSB memory address. Loaded with its default value at power-up (but not system reset). The default is set.


FCTL<16:15>
FCTL<16:15>; GF

Glitch Filter. (R/W) GF<1:0> bits are connected directly to the FB_P1 and FB_P0 signals on the DWLAA where they connect to the programmable glitch filter. The default is 102, which is loaded on power-up (but not system reset). The minimum GF delay is 10 ns.


FCTL<14>
FCTL<14>; FINTEREN

DWLAA Interrupt Enable. (R/W) The FINTEREN bit, when cleared, disables all interrupts. Default is zero (disabled).


FCTL<13:10>
FCTL<13:10>; FINTEN<17:14>

DWLAA Interrupt <17:14> Enable. (R/W) The FINTEN<17:14> bits allow software to enable the interrupt levels the DWLAA responds to. Writing a zero to these four bits disables interrupts for diagnostic purposes. Default is zero (disabled).


FCTL<9>
FCTL<9>; FBR

Futurebus+ Reset. (RO) FBR reflects the state of the RE* signal from the Futurebus+. The bit can only be read if RE* was asserted for reasons other than a BUS INIT or system reset.


FCTL<8>
FCTL<8>; FERSTEN

Fatal Error State Enable. (R/W) When set, a fatal error state is saved in the FERR. The error state is not cleared by a system reset; it is cleared by a power-up. The default on power-up is disabled.


FCTL<7>
FCTL<7>; HSEINTEN

Hose Error Interrupt Enable. (R/W) When set this bit enables error interrupts on hose errors. This bit is clear by default on power-up and system reset.


FCTL<6>
FCTL<6>; FSEIEN

Futurebus+ Slave Error Interrupt Enable. (R/W) When set, enables the DWLAA, when it is a slave on the Futurebus+, to send an error interrupt to the CPU for Futurebus+ errors that cause an error interrupt. Defaults to disabled on power-up and system reset.


FCTL<5>
FCTL<5>; FSELSIEN

Futurebus+ Selected Slave Error Interrupt Enable. (R/W) When set, enables the DWLAA, when it is a selected slave on the Futurebus+, to send an error interrupt to the CPU for Futurebus+ errors that cause an error interrupt. Defaults to disabled on power-up and system reset.


FCTL<4>
FCTL<4>; FMEIEN

Futurebus+ Master Error Interrupt Enable. (R/W) When set, enables the DWLAA, when it is a master on the Futurebus+, to send an error interrupt to the CPU for Futurebus+ errors that cause an error interrupt. Defaults to disabled on power-up and system reset.


FCTL<3>
FCTL<3>; STF

Self-Test Failed. (R/W) When clear, the DWLAA Fault LED lights. Defaults to clear on power-up.


FCTL<2>
FCTL<2>; PRE

Parity Report Enable. (R/W) When set, parity error reporting is enabled. The default is enabled.


FCTL<1>
FCTL<1>; SI

Split Initiator. (R/W) When set, the bit enables the module to initiate split transactions. The default is enabled.


FCTL<0>
FCTL<0>; SM

Slug Mode. (R/W) When the bit is clear, the Down Hose cycle time is 34 ns. When set, the bit enables the DWLAA to communicate with the IOP at a Down Hose cycle time greater than a 40 ns cycle time. The default is set. The bit controls the pipeline feature of the DWLAA.


DIAG<31:24>
DIAG<31:24>; BP<7:0>

BP<7:0> Transceiver Loopback Return Read Data. (RO) These bits contain the data returned from the BP[7:0]* transceivers following a loopback transaction. Power-up to zero.


DIAG<23:16>
DIAG<23:16>; CM<7:0>

CM<7:0> Return. (RO) These bits contain the data returned from the CM[7:0] transceivers following a loopback transaction. Power-up to zero.


DIAG<15>
DIAG<15>; CP<0>

CP<0> Return. (RO) This bit contains the data returned from the CP[0] transceiver following a loopback transaction. Power-up to zero.


DIAG<14:9>
DIAG<14:9>; RSVD

Reserved. (RAZ) Must be zero.


DIAG<8>
DIAG<8>; LBRDY

Loopback Ready. (RO) This bit is set by the Futurebus+ interface to indicate that the DWLAA owns the bus.


DIAG<7>
DIAG<7>; LBEN

Loopback Enable. (R/W) When set, the DWLAA arbitrates for the bus. The default is zero.


DIAG<6>
DIAG<6>; LPBKDN

Loopback Done. (RO) This bit is set by the loopback state machine upon completion of a loopback transaction. The bit is cleared on RESET or when SDL is written with a zero.


DIAG<5>
DIAG<5>; SDL

Start Diagnostic Loopback. (R/W) This bit is used to start/stop the loopback state machine. Writing a one to the bit causes the state machine to initiate a loopback transaction. Writing a zero to the bit stops the state machine and forces it to enter an idle state. Defaults to zero.


DIAG<4>
DIAG<4>; RSVD

Reserved. (RAZ) Must be zero.


DIAG<3>
DIAG<3>; FTTO

Force TTO. (R/W) When FTTO is set, the next master Futurebus+ transaction will cause the TTO bit to set in FERR CSR resulting in a BUS INIT on the Futurebus+. Defaults to zero. A Down Hose reset must be done to clear the error.


DIAG<2>
DIAG<2>; DRE

Diagnostic Reset Enable. (R/W) When set, will reset the DNHSE FIFOs following the assertion of ERROR_L. Defaults to zero.


DIAG<1>
DIAG<1>; DNP<0>_HDRERR

Force PE on Down Hose Packet Header Cycle. (R/W) DNP<0>_HDRERR forces a parity error to occur on DNP<0> during the header cycles of an Mbox transaction. The bit automatically clears after the error is detected. Defaults to zero.


DIAG<0>
DIAG<0>; DNP<0>_DERR

Force PE on Down Hose Packet Data Cycle. (R/W) DNP<0>_DERR forces a parity error to occur on DNP<0> during the data cycles of an Mbox transaction. The bit automatically clears after the error is detected. Defaults to zero.


FGPR<31:0>
FGPR<31:0>; FGPR

General Purpose Register. (R/W) This general purpose register is used for diagnostics.


FERR<31:25>
FERR<31:25>; RSVD

Reserved. (RAZ) Must be zero.


FERR<24>
FERR<24>; BINT

Bus Init. (W1C) Sets if the DWLAA detects a BUS INIT. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<23>
FERR<23>; UNBCMD

Unexpected Mailbox CMD Packet. (W1C) The UNEXP MBX CMD packet bit is set when the DWLAA receives a mailbox packet before finishing the previous packet. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<22>
FERR<22>; DNHSE_SEQ_ERR

Down Hose Sequence Error. (W1C) DNHSE_SEQ_ERR is set when the tag does not match the requested value. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<21>
FERR<21>; DHSE_HDR_CYCLE_PE

Down Hose Header Cycle Parity Error. (W1C) When set, indicates a parity error occurred during a Down Hose header cycle. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<20>
FERR<20>; DNHSE_CMD_LE

Down Hose Command Length Error. (W1C) When set, indicates an incorrect length code was received in response to the length requested. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<19>
FERR<19>; DNHSE_ILLEGAL_DMA_LE

Down Hose Illegal DMA Length Error. (W1C) When set, indicates an invalid length code was received. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<18>
FERR<18>; DNHSE_PACKET_LE

Down Hose Packet Length Error. (W1C) When set, indicates too few or too many hose cycles occurred for a particular transaction. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<17>
FERR<17>; DNHSE_ILLEGAL_CMD_ERR

Down Hose Illegal Command Error. (W1C) When set, indicates a reserved command was received. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<16>
FERR<16>; FIFOFULL

FIFO Full. (W1C) Sets when the module FIFO signal asserts. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<15>
FERR<15>; DPCU

DPC Underflow. (W1C) Sets when the DWLAA receives a Decrement Packet Counter and there are no outstanding packets in the IOP (unexpected DPC). If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<14:6>
FERR<14:6>; RSVD

Reserved. (RAZ) Must be zero.


FERR<5>
FERR<5>; BRTO

Busy Retry Threshold Exceeded. (W1C) BRTO is set when the master detects a busy timeout for Futurebus+ transactions.


FERR<4>
FERR<4>; STO

Split Timeout. (W1C) STO sets when the STO timer expires before receiving a pending split response for Futurebus+ transactions.


FERR<3>
FERR<3>; TTO

Transaction Timeout. (W1C) TTO is set if the master detects a transaction timeout. If the FERSTEN bit is set in the FCTL register, this bit does not clear on system reset.


FERR<2>
FERR<2>; DHDPE

Down Hose Data Parity Error. (W1C) DHDPE is set when there is a Down Hose parity error on data cycles. This error can also set the Error bit in the Mailbox Status Return packet, and an error interrupt will be sent up the hose.


FERR<1>
FERR<1>; DHURR

Down Hose Unsolicited Read Response. (W1C) DHURR is set when a DMA Read Return packet is received by the DWLAA and one is not expected. This is a fatal error if the FERSTEN bit is set.


FERR<0>
FERR<0>; FINTERR

DWLAA Internal CSR Error. (W1C) The FINTERR bit sets if an error occurs while accessing a DWLAA CSR from the mailbox. This error includes invalid data width or an invalid command. The default is zero.


IBR<31:3>
IBR<31:3>; RSVD

Reserved. (RAZ) Must be zero.


IBR<2>
IBR<2>; SCLK

Serial Clock. (R/W) This bit triggers the EEPROM's serial clock interface. When written with a one, the EEPROM's serial clock is forced to a logic high and when written with a zero, the serial clock is forced to a logic low.


IBR<1>
IBR<1>; XMT_SDAT

Transmit Serial Data. (R/W) This bit asserts the EEPROM's serial data line and is used with SCLK to transfer command, address, and data to the EEPROM.


IBR<0>
IBR<0>; RCV_SDAT

Receive Serial Data. (R/W) This bit reflects the read data of the EEPROM's serial data line when XMT_SDAT is a one. The received data is the inverted version of the written data.


DID<31:26>
DID<31:26>; RSVD

Reserved. (RAZ) Must be zero.


DID<25:21>
DID<25:21>; GEO_ADDR

Geographical Address. (RO) These bits are the inverse of the GA<5:0> Futurebus+ lines.


DID<20>
DID<20>; NODE_SIDE

Node Side. (RO, 0) A Futurebus+ slot can contain a module that has two nodes on it. This bit is used to state whether the module has one node on it or two. If the bit is clear, one node is on the module and if it is set, there are two. For the DWLAA the bit is clear.


DID<19:16>
DID<19:16>; DREV

CLIF Revision. (RO) This field contains the revision of the DC7309A (CLIF) chip.


DID<15:0>
DID<15:0>; DEVID

Device ID. (RO) This field contains the device type of the DWLAA. The device type is 2F0016.


INT 14-17 CSRs
INT 14-17 CSRs <15:0>; VECTOR

Vector. (R/W) Pointers to the interrupt service routines for IPLs 14 through 17.


LDEV<31:16>
LDEV<31:16>; DREV

Device Revision. (RO, 0) Identifies the revision level of an LSB node.


LDEV<15:0>
LDEV<15:0>; DTYPE

Device Type. (RO) Identifies the type of node. The IOP is 2000 (hex).


LBER<31:19>
LBER<31:19>; RSVD

Reserved. (RO, 0) Read as zero.


LBER<18>
LBER<18>; NSES

Node-Specific Error Summary. (RO, 0) Sets when any IOP-specific error condition is reported in the IPCNSE register or the IPCHST register.


LBER<17>
LBER<17>; CTCE

Control Transmit Check Error. (W1C, 0) When the IOP drives an LSB control line, it checks to verify that the line was driven correctly. If it was not, CTCE is set and ERR is asserted.


LBER<16>
LBER<16>; DTCE

Data Transmit Check Error. (W1C, 0) When the IOP drives a data or command cycle, it verifies that the D<127:0> and ECC<27:0> lines were driven correctly. If there is a mismatch, DTCE is set and ERR is asserted.


LBER<15>
LBER<15>; DIE

Dirty Error. (NI, 0) Not implemented on the IOP.


LBER<14>
LBER<14>; SHE

Shared Error. (NI, 0) Not implemented on the IOP.


LBER<13>
LBER<13>; CAE

Command/Address Error. (W1C, 0) If the IOP receives an asserted CA signal during a cycle when CA signals are not allowed, CAE is set and ERR is asserted.


LBER<12>
LBER<12>; NXAE

Nonexistent Address Error. (W1C, 0) If the IOP does not receive confirmation for a command it sent on the LSB, NXAE is set and ERR is asserted.


LBER<11>
LBER<11>; CNFE

Confirmation Error. (W1C, 0) If the IOP receives a confirmation signal during a cycle that does not permit confirmation, it sets CNFE and asserts ERR.


LBER<10>
LBER<10>; STE

STALL Error. (W1C, 0) If the IOP receives a STALL during a cycle that does not permit stalls, it sets STE and asserts ERR.


LBER<9>
LBER<9>; TDE

Transmitter During Error. (W1C, 0) If the IOP was driving D<127:0> during a cycle when a CE, UCE, CPE, or CDPE error occurred, it sets TDE. Command information is locked into the LBECR registers.


LBER<8>
LBER<8>; CDPE2

Second CSR Data Parity Error. (W1C, 0) If CDPE is set and a second parity error occurs on a CSR data cycle, CDPE2 is set.


LBER<7>
LBER<7>; CDPE

CSR Data Parity Error. (W1C, 0) If a parity error occurs during a CSR data cycle, the IOP sets CDPE, asserts ERR, and locks D<38:0> in the LBECR registers.


LBER<6>
LBER<6>; CPE2

Second Command Parity Error. (W1C, 0) If CPE is set and a second parity error occurs on a command cycle, the IOP sets CPE2.


LBER<5>
LBER<5>; CPE

Command Parity Error. (W1C, 0) If a parity error occurs on a command cycle, the IOP sets CPE, asserts ERR, and locks D<38:0> in the LBECR registers.


LBER<4>
LBER<4>; CE2

Second Correctable Data Error. (W1C, 0) If CE is set and a second correctable ECC error occurs on a data cycle, the IOP sets CE2.


LBER<3>
LBER<3>; CE

Correctable Data Error. (W1C, 0) If the IOP detects an ECC error on the LSB, it sets CE, asserts ERR, and locks D<38:0> of the command cycle in the LBECR registers.


LBER<2>
LBER<2>; UCE2

Second Uncorrectable Data Error. (W1C, 0) If UCE is set and the IOP detects a second uncorrectable data error, UCE2 is set.


LBER<1>
LBER<1>; UCE

Uncorrectable Data Error. (W1C, 0) If the IOP detects an uncorrectable ECC error on the LSB during a data cycle, it sets UCE, asserts ERR, and locks D<38:0> of the command cycle in LBECR registers.


LBER<0>
LBER<0>; E

Error. (W1C, 0) The IOP sets E whenever it detects the assertion of ERR on the LSB.


LCNR<31>
LCNR<31>; STF

Self-Test Fail. (R/W, 0) When set, indicates that this node has not yet completed self-test.


LCNR<30>
LCNR<30>; NRST

Node Reset. (WO, 0) When set, the node enters console mode and undergoes a reset sequence.


LCNR<29>
LCNR<29>; NHALT

Node Halt. (NI, 0) Not implemented.


LCNR<28>
LCNR<28>; RSTSTAT

Reset Status. (NI, 0) Not Implemented.


LCNR<27:1>
LCNR<27:1>; MBZ

Must Be Zero. (RO, 0) Must always be written as zero.


LCNR<0>
LCNR<0>; CEEN

Correctable Error Detection Enable. (R/W, 0) When set, enables detection of correctable errors.


IBR<31:3>
IBR<31:3>; RSVD

Reserved. (MBZ) Must be zero.


IBR<2>
IBR<2>; SCLK

Serial Clock. (R/W, 0) Used to implement the SEEPROM serial clock. When the bit is written with a one, the SEEPROM serial clock input is forced high. When this bit is cleared, the serial clock input is forced low.


IBR<1>
IBR<1>; XMT_SDAT

Transmit Serial Data. (R/W, 1) Used by software to assert or deassert the serial data line to the SEEPROM.


IBR<0>
IBR<0>; RCV_SDAT

Receive Serial Data. (RO, 1) The bit reflects the state of the SEEPROM serial data line. It is used by software to receive SEEPROM serial read data and responses. To receive data from the SEEPROM, XMT_SDAT must be set.


LMMR<31:17>
LMMR<31:17>; MODULE_ADDR

Module Address. (R/W, 0) Specifies the most significant bits of the base address of the memory region spanned by the memory module associated with this register (LMMR0 - LMMR7). These bits correspond to bits <39:25> of the byte address or D<34:20> of the command cycle.


LMMR<16:11>
LMMR<16:11>; RSVD

Reserved. (MBZ, 0) Read as zero.


LMMR<10:9>
LMMR<10:9>; NBANKS

Number of Banks. (R/W, 0) Specifies the number of memory banks (1, 2, 4, or 8) contained on the memory module associated with this register (LMMR0 - LMMR7). The value of this field determines how many bits of the memory address (0, 1, 2, or 3) are inserted into the bank number.

LMMR<10:9>	Banks per Module	Bits in Bank Number
00	1	0
01	2	1
10	4	2
11	8	3


LMMR<8:5>
LMMR<8:5>; AW

Address Width. (R/W, 0) Specifies the number of valid bits in MODULE_ADDR (LMMR<31:17>), starting from the MSB. The remaining bits of MODULE_ADDR are ignored.


LMMR<4:3>
LMMR<4:3>; IA

Interleave Address. (R/W, 0) Specifies which interleave, within a group of interleaved modules, is served by the module associated with this register (LMMR0 - LMMR7).


LMMR<2:1>
LMMR<2:1>; INT

Interleave. (R/W, 0) Specifies the number of memory modules interleaved with this module (1, 2, or 4). This value determines the number of bits in the INT field (0, 1, or 2, starting from the LSB) that are compared to the LSBs of the memory address.

LMMR<2:1>	Modules Interleaved	Address Bits Compared
00	1	0
01	2	1
10	4	2
11	Reserved	Reserved


LMMR<0>
LMMR<0>; EN

Enable. (R/W, 0) When set, indicates that the module associated with this register (LMMR0 - LMMR7) is installed, and it is a memory module or a CPU module with globally visible memory.


LBESR<31:7>
LBESR<31:7>; RSVD

Reserved. (RO, 0) Read as zero.


LBESR<6:0>
LBESR<6:0>; SYND_0

Syndrome 0. (RO, 0) Syndrome computed from D<31:0> and ECC<6:0> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_1

Syndrome 1. (RO, 0) Syndrome computed from D<63:32> and ECC<13:7> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_2

Syndrome 2. (RO, 0) Syndrome computed from D<95:33> and ECC<20:14> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_3

Syndrome 3. (RO, 0) Syndrome computed from D<127:96> and ECC<27:21> during error cycle.

A syndrome of zero indicates no ECC error for the given longword. Syndromes for Single-Bit Errors gives the syndromes for all single-bit errors. Any non-zero syndrome not listed in Syndromes for Single-Bit Errors indicates a double-bit error.


Syndromes for Single-Bit Errors

Bit	Syndrome (Hex)	Bit	Syndrome (Hex)
Data<0>	4F	Data<20>	16
Data<1>	4A	Data<21>	19
Data<2>	52	Data<22>	1A
Data<3>	54	Data<23>	1C
Data<4>	57	Data<24>	62
Data<5>	58	Data<25>	64
Data<6>	5B	Data<26>	67
Data<7>	5D	Data<27>	68
Data<8>	23	Data<28>	6B
Data<9>	25	Data<29>	6D
Data<10>	26	Data<30>	70
Data<11>	29	Data<31>	75
Data<12>	2A	ECC<0>	01
Data<13>	2C	ECC<1>	02
Data<14>	31	ECC<2>	04
Data<15>	34	ECC<3>	08
Data<16>	0E	ECC<4>	10
Data<17>	0B	ECC<5>	20
Data<18>	13	ECC<6>	40
Data<19>	15


LBECR0<31:0>
LBECR0<31:0>; CA

Command/ Address. (RO) Contents of D<31:0> during command cycle.


LBECR1<31:20>
LBECR1<31:20>; RSVD

Reserved. (R0) Read as zero.


LBECR1<19:18>
LBECR1<19:18>; DCYCLE

Data Cycle. (RO) Indicates which data cycle had the data error.

LBECR <19:18>	Data Cycle in Error
00	0
01	1
10	2
11	3


LBECR1<17>
LBECR1<17>; DIRTY

Dirty. (NI, 0) Not implemented.


LBECR1<16>
LBECR1<16>; SHARED

Shared. (NI, 0) Not implemented.


LBECR1<15>
LBECR1<15>; CNF

Confirmation. (RO) Set when CNF is asserted for the current command.


LBECR1<14:11>
LBECR1<14:11>; RSVD

Reserved. (R0) Read as zero.


LBECR1<10:7>
LBECR1<10:7>; CID

Commander ID. (RO) Contents of REQ<3:0> during command cycle.


LBECR1<6>
LBECR1<6>; P

Parity. (RO) Contents of D<38> during command cycle.


LBECR1<5:3>
LBECR1<5:3>; CMD

Command. (RO) Contents of D<37:35> during command cycle. CMD is decoded as follows:

Command	Function	DAS Value
000	Read	00
001	Write	08
010	Reserved
011	Write Victim	18
100	Read CSR	20
101	Write CSR	28
110	Reserved
111	Private	38
DAS Value is the hex value commonly found in the low byte of this register when less than 8 Gbytes of memory is present in the system.


LBECR1<2:0>
LBECR1<2:0>; CA

Command/ Address. (RO) Contents of D<34:32> during command cycle.


LILID<31:16>
LILID<31:16>; RSVD

Reserved. (MBZ) Must be zero.


LILID<15:0>
LILID<15:0>; IDENT

IDENT. (RTC) This field is loaded with the vector information supplied by the I/O adapter in the INTR/IDENT command packet. If the interrupt was for an IOP error, the vector is loaded from the IPC Vector Register.


LCPUMASK<31:16>
LCPUMASK<31:16>; RSVD

Reserved. (MBZ) Must be zero.


LCPUMASK<15:12>
LCPUMASK<15:12>; CPU 3

IPL for CPU 3. (R/W, 0) Bits <12> through <15> correspond to IPL levels 14 through 17. When a bit is set, a corresponding interrupt is posted to CPU 3.


LCPUMASK<11:8>
LCPUMASK<11:8>; CPU 2

IPL for CPU 2. (R/W, 0) Bits <8> through <11> correspond to IPL levels 14 through 17. When a bit is set, a corresponding interrupt is posted to CPU 2.


LCPUMASK<7:4>
LCPUMASK<7:4>; CPU 1

IPL for CPU 1. (R/W, 0) Bits <4> through <7> correspond to IPL levels 14 through 17. When a bit is set, a corresponding interrupt is posted to CPU 1.


LCPUMASK<3:0>
LCPUMASK<3:0>; CPU 0

IPL for CPU 0. (R/W, 0) Bits <0> through <3> correspond to IPL levels 14 through 17. When a bit is set, a corresponding interrupt is posted to CPU 0.


LMBPR<37:6>
LMBPR<37:6>; MBX

Mailbox Data Structure Address. (R/W, 0) This field contains the 64 byte-aligned physical address of the mailbox data structure in memory where the IOP locates request information.


LMBPR<5:0>
LMBPR<5:0>; MBZ

Reserved. (MBZ) Must be zero.


IPCNSE<31>
IPCNSE<31>; INTR_NSES

Interrupt on NSES. (R/W, 0) This bit, when set to one, enables all error interrupt sources on the IOP module. If an error is detected and this bit is set, the IOP posts a level 17 interrupt. A subsequent read of LILID3 returns the vector from the IPC Vector Register (IPCVR). When this bit is clear, no interrupt is posted. (The appropriate error bit will still be set in IPCNSE or IPCHST, however.)

All IOP-specific error bits must be cleared before a subsequent error interrupt is posted.

LSB-detected errors always cause the IOP to post an LSB interrupt, by the assertion of ERR and are not maskable.


IPCNSE<30:21>
IPCNSE<30:21>; RSVD

Reserved. (MBZ) Must be zero.


IPCNSE<20>
IPCNSE<20>; MULT_INTR_ERR

Multiple Interrupt Error. (W1C)The IOP can accept up to four pending interrupts per IPL level. If more than four interrupts for a given IPL occur before the CPU services any, this bit will set. If error interrupts are enabled, setting this error bit results in an interrupt.


IPCNSE<19>
IPCNSE<19>; DN_VRTX_ERR

Down Vortex Error. (W1C) This bit is set whenever any of the following errors are detected by the Down Hose HIC:

•	Parity error

•	Illegal command error

•	Sequence error

•	Buffer overflow error

•	Internal HIC error

Reset the IOP if this error bit is set.


IPCNSE<18>
IPCNSE<18>; UP_VRTX_ERR

Up Vortex Error. (W1C) This bit is set whenever any of the following errors are detected by the Up Hose HIC:

•	Parity error

•	Illegal command error

•	Sequence error

•	Buffer overflow error

Reset the IOP if this error bit is set.


IPCNSE<17>
IPCNSE<17>; IPC_IE

IPC Internal Error. (W1C) This bit is set when the IPC detects an internal error and generally indicates that control logic encountered an undefined or inconsistent condition.

Reset the IOP if this error bit is set.


IPCNSE<16>
IPCNSE<16>; UP_HIC_IE

Up HIC Internal Error. (W1C) This bit is set whenever the Up HIC detects an error.

Reset the IOP if this error bit is set.


IPCNSE<15:12>
IPCNSE<15:12>; UP_HOSE_PAR_ERR

Up Hose Parity Error. (W1C) Each bit in this field represents a parity error on a particular hose. Bits <12> through <15> correspond to hoses 0 through 3. When a bit is set, a parity error occurred on the corresponding Up Hose.


IPCNSE<11:8>
IPCNSE<11:8>; UP_HOSE_PKT_ERR

Up Hose Packet Error. (W1C) Each bit in this field represents a packet error on a particular hose. Bits <8> through <11> correspond to hoses 0 through 3. When a bit is set, either an illegal command error or a sequence error occurred on the corresponding Up Hose.


IPCNSE<7:4>
IPCNSE<7:4>; UP_HOSE_OFLO

Up Hose FIFO Overflow Error. (W1C) Each bit in this field represents an overflow condition on FIFO of a particular hose. Bits <4> through <7> correspond to hoses 0 through 3. When a bit is set, an overflow has occurred on the FIFO of the corresponding Up Hose.


IPCNSE<3:0>
IPCNSE<3:0>; MBX_TIP

Mailbox Transaction in Progress. (W1C) Each bit in this field indicates the transmission of a Mailbox Command packet down a particular hose. Bits <0> through <3> correspond to hoses 0 through 3. When the corresponding Mailbox Return Status packet is returned, the bit is cleared.


IPCVR<31:16>
IPCVR<31:16>; RSVD

Reserved. (MBZ, 0) Must be zero.


IPCVR<15:0>
IPCVR<15:0>; Vector

Vector. (R/W, 0) When the CPU servicing an IOP error interrupt reads LILID3, the contents of this field is returned as the vector pointing to the IOP error interrupt handler.


IPCMSR<31:3>
IPCMSR<31:3>; RSVD

Reserved. (MBZ, 0) Must be zero.


IPCMSR<2:1>
IPCMSR<2:1>; ARB_CTL

Arbitration Control. (R/W, 0) Used to select how many times the IOP arbitrates at high priority before switching to low. ARB_CTL is encoded as follows:

Bits <2:1>	Priority Arbitration Algorithm
00	6 high followed by 1 losing or 2 winning at low
01	4 high followed by 1 losing or 2 winning at low
10	2 high followed by 1 losing or 2 winning at low
11	Low priority
Only the read portion of a Read-Modify-Write transaction is counted as a request in this algorithm. The write portion is always done at high priority.


IPCMSR<0>
IPCMSR<0>; ARB_HIGH

Arbitration High. (R/W, 0) When set, ARB_CTL is overridden and the IOP always arbitrates high.


IPCHST<31:28>
IPCHST<31:28>; HOSE_RST<3:0>

Hose Reset. (WO, 0) When written with a one, each bit in this field asserts the DNRST signal that resets the attached I/O subsystem. Bits <28> through <31> correspond to Down Hoses 0 through 3. Reads always return zeros.


IPCHST<27:16>
IPCHST<27:16>; RSVD

Reserved. (MBZ, 0) Must be zero.


IPCHST<15:12>
IPCHST<15:12>; H3_STAT<3:0>

Hose 3 Status. These bits indicate that an I/O adapter is present and can function. The bits encode as follows:

Bit	Description
H3_STAT<3>	Hose signal PWROK transitioned. This bit is W1C.
H3_STAT<2>	Hose signal CBLOK current level. This bit is RO.
H3_STAT<1>	Hose signal PWROK current level. This bit is RO.
H3_STAT<0>	Hose signal ERROR transitioned from 0 to 1. This bit is W1C.
Initialization depends upon the presence or absence of an I/O adapter.


IPCHST<11:8>
IPCHST<11:8>; H2_STAT<3:0>

Hose 2 Status. These bits indicate that an I/O adapter is present and can function. The bits encode as follows:

Bit	Description
H3_STAT<3>	Hose signal PWROK transitioned. This bit is W1C.
H3_STAT<2>	Hose signal CBLOK current level. This bit is RO.
H3_STAT<1>	Hose signal PWROK current level. This bit is RO.
H3_STAT<0>	Hose signal ERROR transitioned from 0 to 1. This bit is W1C.
Initialization depends upon the presence or absence of an I/O adapter.


IPCHST<7:4>
IPCHST<7:4>; H1_STAT<3:0>

Hose 1 Status. These bits indicate that an I/O adapter is present and can function. The bits encode as follows:

Bit	Description
H3_STAT<3>	Hose signal PWROK transitioned. This bit is W1C.
H3_STAT<2>	Hose signal CBLOK current level. This bit is RO.
H3_STAT<1>	Hose signal PWROK current level. This bit is RO.
H3_STAT<0>	Hose signal ERROR transitioned from 0 to 1. This bit is W1C.
Initialization depends upon the presence or absence of an I/O adapter.


IPCHST<3:0>
IPCHST<3:0>; H0_STAT<3:0>

Hose 0 Status. These bits indicate that an I/O adapter is present and can function. The bits encode as follows:

Bit	Description
H3_STAT<3>	Hose signal PWROK transitioned. This bit is W1C.
H3_STAT<2>	Hose signal CBLOK current level. This bit is RO.
H3_STAT<1>	Hose signal PWROK current level. This bit is RO.
H3_STAT<0>	Hose signal ERROR transitioned from 0 to 1. This bit is W1C.
Initialization depends upon the presence or absence of an I/O adapter.


IPCDR<31>
IPCDR<31>; DIAG_ECC_EN

Diagnostic ECC Enable. (R/W, 0) When set, the bits in IPCDR<30:24> are the ECC bits transmitted on the LSB. This feature is used to force correctable and uncorrectable ECC errors. The "failing" ECC code is driven on the LSB bus, and all other nodes watching the bus detect the error.


IPCDR<30:24>
IPCDR<30:24>; DIAG_ECC<6:0>

Diagnostic ECC <6:0>. (R/W, 0) This field is written by diagnostics with a substitute ECC pattern allowing correctable and uncorrectable ECC errors to be transmitted on the LSB. The field is enabled when DIAG_ECC_EN is set. The "failing" ECC code is driven on the LSB bus, and all other nodes watching the bus detect the error.


IPCDR<23>
IPCDR<23>; FRC_CAE

Force CA Error. (WO, 0) When this bit is set by diagnostics, the IOP causes an error by asserting a command/address during a cycle that does not accept command/addresses. Each node monitoring the LSB should set the CAE bit in its LBER register.


IPCDR<22>
IPCDR<22>; FRC_ CNFE

Force CNF Error. (WO, 0) When this bit is set by diagnostics, the IOP asserts CNF during an illegal cycle. Each node monitoring the LSB should set the CNFE bit in its LBER register.


IPCDR<21:14>
IPCDR<21:14>; RSVD

Reserved. (MBZ) Must be zero.


IPCDR<13>
IPCDR<13>; FRC_CMD_PE

Force Command Parity Error. (R/W, 0) When set, the IPC chip asserts bad parity on the LSB bus during a command cycle.


IPCDR<12>
IPCDR<12>; FRC_DAT_PE

Force Data Parity Error. (R/W, 0) When set, the IPC chip asserts bad parity on the LSB bus when returning data on a read of a CSR.


IPCDR<11>
IPCDR<11>; HIC_LPBCK_EN

HIC Loopback Enable. (R/W, 0) When set, the IOP internally loops back a Mailbox Command packet between the Down and Up Hose while it asserts the hose error signal on all Up Hoses to disable all I/O adapters.


IPCDR<10>
IPCDR<10>; DIS_LSB_CMD

Disable LSB Command Transmission. (R/W, 0) When set, the IOP does not transmit data on the LSB allowing Up Hose data path buffers in the IPC and HIC to fill. When the bit is cleared, the IOP processes all the transactions in the buffers.


IPCDR<9:4>
IPCDR<9:4>; RSVD

Reserved. (MBZ, 0) Must be zero.


IPCDR<3:2>
IPCDR<3:2>; FRC_DN_DPE<1:0>

Force Down Data Parity Error. (R/W, 0) When either of these bits is set, bad parity is sent on the Down Vortex bus.

FRC_DN_DPE<1> forces bad parity on the longword from IPC-B.

FRC_DN_DPE<0> forces bad parity on the longword from IPC-A.


IPCDR<1>
IPCDR<1>; FRC_DN_SEQ_ERR

Force Down Sequence Error. (R/W, 0) When set, the IPC cycles an incorrect number of times during the transmission of a packet on the Down Vortex bus.


IPCDR<0>
IPCDR<0>; FRC_DN_ILL_CMD

Force Down Illegal Command. (R/W, 0) When set, the IPC sends an illegal command during the transmission of a packet on the Down Vortex bus.


TB_TAG<42:13>
TB_TAG<42:13>; VA

Virtual Address. (W) Bits extracted from the virtual address to form the tags for the small pages (8 Kbytes) of the ITB.


TB_TAG<42:22>
TB_TAG<42:22>; VA

Virtual Address. (W) Bits extracted from the virtual address to form the tags for the large pages (4 Mbytes) of the ITB.


ICCSR W<52:47>
ICCSR W<52:47>; ASN

Address Space Number. (R/W, 0) The ASN field is used with the I-cache to further qualify cache entries and avoid some cache flushes. The ASN is written to the I-cache during fill operations and compared with the I-stream data on fetch operations. Mismatches invalidate the fetch without affecting the I-cache.


ICCSR R<33:28>
ICCSR R<33:28>; ASN

Address Space Number. (R/W, 0) The ASN field is used with the I-cache to further qualify cache entries and avoid some cache flushes. The ASN is written to the I-cache during fill operations and compared with the I-stream data on fetch operations. Mismatches invalidate the fetch without affecting the I-cache.


ICCSR W<42>
ICCSR W<42>; FPE

Floating-Point Enable. (R/W, 0) If set, floating-point instructions can be issued. If clear, floating-point instructions cause FEN exceptions.


ICCSR R<23>
ICCSR R<23>; FPE

Floating-Point Enable. (R/W, 0) If set, floating-point instructions can be issued. If clear, floating-point instructions cause FEN exceptions.


ICCSR R<22>
ICCSR R<22>; MAP

Map. (R/W, 0) If set, it allows superpage I-stream memory mapping of virtual PC <33:13> directly to physical PC <33:13> essentially bypassing ITB for virtual PC addresses containing virtual PC <42:41> = 2. Superpage mapping is allowed in kernel mode only. The I-cache ASM bit is always set. If clear, superpage mapping is disabled.


ICCSR W<41>
ICCSR W<41>; MAP

Map. (R/W, 0) If set, it allows superpage I-stream memory mapping of virtual PC <33:13> directly to physical PC <33:13> essentially bypassing ITB for virtual PC addresses containing virtual PC <42:41> = 2. Superpage mapping is allowed in kernel mode only. The I-cache ASM bit is always set. If clear, superpage mapping is disabled.


ICCSR R<21>
ICCSR R<21>; HWE

Hardware Enable. (R/W, 0) If set, it allows the five PALRES instructions (see the Alpha Architecture Reference Manual) to be issued in kernel mode. If cleared, attempts to execute PALRES instructions while not in PALmode result in OPCDEC exceptions.


ICCSR W<40>
ICCSR W<40>; HWE

Hardware Enable. (R/W, 0) If set, it allows the five PALRES instructions (see the Alpha Architecture Reference Manual) to be issued in kernel mode. If cleared, attempts to execute PALRES instructions while not in PALmode result in OPCDEC exceptions.


ICCSR R<20>
ICCSR R<20>; DI

Dual Issue. (R/W, 0) If set, dual-instruction issue is enabled. If cleared, instructions can only single issue.


ICCSR W<39>
ICCSR W<39>; DI

Dual Issue. (R/W, 0) If set, dual-instruction issue is enabled. If cleared, instructions can only single issue.


ICCSR R<19>
ICCSR R<19>; BHE

Branch History Enable. (R/W, 0) Used with BPE to select branch prediction.

BPE	BHE	Prediction
0	X	Not taken
1	0	Sign of displacement
1	1	Branch history table


ICCSR W<38>
ICCSR W<38>; BHE

Branch History Enable. (R/W, 0) Used with BPE to select branch prediction.

BPE	BHE	Prediction
0	X	Not taken
1	0	Sign of displacement
1	1	Branch history table


ICCSR R<18>
ICCSR R<18>; JSE

Jump SubroutineEnable. (R/W, 0) If set, it enables the JSR stack to push a return address. If cleared, JSR stack is disabled.


ICCSR W<37>
ICCSR W<37>; JSE

Jump SubroutineEnable. (R/W, 0) If set, it enables the JSR stack to push a return address. If cleared, JSR stack is disabled.


ICCSR R<17>
ICCSR R<17>; BPE

Branch Prediction Enable. (R/W, 0) Used with BHE to select branch prediction. See description of BHE above.


ICCSR W<36>
ICCSR W<36>; BPE

Branch Prediction Enable. (R/W, 0) Used with BHE to select branch prediction. See description of BHE above.


ICCSR R<16>
ICCSR R<16>; PIPE

Pipeline. (R/W, 0) If clear, it causes all hardware interlocked instructions to drain the machine and waits for the write buffer to empty before issuing the next instruction. Examples of instructions that do not cause the pipe to drain include HW_MTPR, HW_REI, conditional branches, and instructions that have a destination register of R31. If set, pipeline proceeds normally.


ICCSR W<35>
ICCSR W<35>; PIPE

Pipeline. (R/W, 0) If clear, it causes all hardware interlocked instructions to drain the machine and waits for the write buffer to empty before issuing the next instruction. Examples of instructions that do not cause the pipe to drain include HW_MTPR, HW_REI, conditional branches, and instructions that have a destination register of R31. If set, pipeline proceeds normally.


ICCSR R<15:13>
ICCSR R<15:13>; PCMUX1

Performance Counter Mux 1. (R/W, 0)

MUX1	Input	Comment
000	D-cache miss	Counts total D-cache misses.
001	I-cache miss	Counts total I-cache misses.
010	Dual issues	Counts cycles of dual issue.
011	Branch mispredicts	Counts both conditional branch mispredictions and JSR or HW_REI mispredictions. Conditional branch mispredictions cost 4 cycles and others cost 5 cycles of pipeline delay.
100	FP instructions	Counts total floating-point operate instructions; that is, no FP branch, load, or store.
101	Integer operate	Counts integer operate instructions including LDA and LDAH with destination other than R31.
110	Store instructions	Counts total store instructions.
111	PERF_CNT_H = 1	Counts external events supplied to a pin at a selected system clock cycle interval.


ICCSR W<34:32>
ICCSR W<34:32>; PCMUX1

Performance Counter Mux 1. (R/W, 0)

MUX1	Input	Comment
000	D-cache miss	Counts total D-cache misses.
001	I-cache miss	Counts total I-cache misses.
010	Dual issues	Counts cycles of dual issue.
011	Branch mispredicts	Counts both conditional branch mispredictions and JSR or HW_REI mispredictions. Conditional branch mispredictions cost 4 cycles and others cost 5 cycles of pipeline delay.
100	FP instructions	Counts total floating-point operate instructions; that is, no FP branch, load, or store.
101	Integer operate	Counts integer operate instructions including LDA and LDAH with destination other than R31.
110	Store instructions	Counts total store instructions.
111	PERF_CNT_H = 1	Counts external events supplied to a pin at a selected system clock cycle interval.


ICCSR R<12:9>
ICCSR R<12:9>; PCMUX0

Performance Counter Mux 0. (R/W, 0)

MUX0	Input	Comment
000X	Total Issues/2	Counts total issues divided by 2; dual issue increments count by 1.
001X	Pipeline Dry	Counts cycles where nothing issued due to lack of valid I-stream data. Causes include I-cache fill, misprediction, branch delay slots, and pipeline drain for exception.
010X	Load Instructions	Counts all Load instructions.
011X	Pipeline Frozen	Counts cycles where nothing issued due to resource conflict.
100X	Branch Instructions	Counts all conditional branches, unconditional branches, JSR, and HW_REI instructions.
1011	PALmode	Counts cycles while executing in PALmode.
1010	Total cycles	Counts total cycles.
110X	Total Non-issues/2	Counts total non_issues divided by 2; that is, no issue increments count by 1.
111X	PERF_CNT_H = 0	Counts external events supplied to a pin at a selected system clock cycle interval.


ICCSR W<11:8>
ICCSR W<11:8>; PCMUX0

Performance Counter Mux 0. (R/W, 0)

MUX0	Input	Comment
000X	Total Issues/2	Counts total issues divided by 2; dual issue increments count by 1.
001X	Pipeline Dry	Counts cycles where nothing issued due to lack of valid I-stream data. Causes include I-cache fill, misprediction, branch delay slots, and pipeline drain for exception.
010X	Load Instructions	Counts all Load instructions.
011X	Pipeline Frozen	Counts cycles where nothing issued due to resource conflict.
100X	Branch Instructions	Counts all conditional branches, unconditional branches, JSR, and HW_REI instructions.
1011	PALmode	Counts cycles while executing in PALmode.
1010	Total cycles	Counts total cycles.
110X	Total Non-issues/2	Counts total non_issues divided by 2; that is, no issue increments count by 1.
111X	PERF_CNT_H = 0	Counts external events supplied to a pin at a selected system clock cycle interval.


ICCSR R<2>
ICCSR R<2>; PC1

Performance Counter 1. (R/W) If clear, it enables performance counter 1 interrupt request after 2**12 events counted. If set, it enables performance counter 1 interrupt request after 2**8 events counted.

Performance Counters

The performance counters are reset to zero upon power-up. Otherwise they are never cleared. The counters are intended as a means of counting events over a long period of time, relative to the event frequency. They provide no means of extracting intermediate counter values.

Since the counters continuously accumulate selected events, despite interrupts being enabled, the first interrupt after selecting a new counter input has an error bound as large as the selected overflow range. Some inputs can overcount events occurring simultaneously with D-stream errors that abort the actual event very late in the pipeline. For example, when counting load instructions, attempts to execute a load resulting in a TB miss exception will increment the performance counter after the first aborted execution attempt and again after the TB fill routine when the load instruction reissues and completes.

Performance counter interrupts are reported six cycles after the event that caused the counter to overflow. Additional delay can occur before an interrupt is serviced if the processor is executing PALcode that always disables interrupts. Events occurring during the interval between counter overflow and interrupt service are counted toward the next interrupt. Only in the case of a complete counter wrap-around while interrupts are disabled will an interrupt be missed.

The six cycles before an interrupt is triggered implies that a maximum of 12 instructions may have completed before the start of the interrupt service routine. When counting I-cache misses, no intervening instructions can complete and the exception PC contains the address of the last I-cache miss. Branch mispredictions allow a maximum of only two instructions to complete before start of the interrupt service routine.


ICCSR W<0>
ICCSR W<0>; PC1

Performance Counter 1. (R/W) If clear, it enables performance counter 1 interrupt request after 2**12 events counted. If set, it enables performance counter 1 interrupt request after 2**8 events counted.

Performance Counters

The performance counters are reset to zero upon power-up. Otherwise they are never cleared. The counters are intended as a means of counting events over a long period of time, relative to the event frequency. They provide no means of extracting intermediate counter values.

Since the counters continuously accumulate selected events, despite interrupts being enabled, the first interrupt after selecting a new counter input has an error bound as large as the selected overflow range. Some inputs can overcount events occurring simultaneously with D-stream errors that abort the actual event very late in the pipeline. For example, when counting load instructions, attempts to execute a load resulting in a TB miss exception will increment the performance counter after the first aborted execution attempt and again after the TB fill routine when the load instruction reissues and completes.

Performance counter interrupts are reported six cycles after the event that caused the counter to overflow. Additional delay can occur before an interrupt is serviced if the processor is executing PALcode that always disables interrupts. Events occurring during the interval between counter overflow and interrupt service are counted toward the next interrupt. Only in the case of a complete counter wrap-around while interrupts are disabled will an interrupt be missed.

The six cycles before an interrupt is triggered implies that a maximum of 12 instructions may have completed before the start of the interrupt service routine. When counting I-cache misses, no intervening instructions can complete and the exception PC contains the address of the last I-cache miss. Branch mispredictions allow a maximum of only two instructions to complete before start of the interrupt service routine.


ICCSR R<1>
ICCSR R<1>; PC0

Performance Counter 0. R/W0 If clear, it enables performance counter 0 interrupt request after 2**16 events counted. If set, it enables performance counter 0 interrupt request after 2**12 events counted.

Performance Counters

The performance counters are reset to zero upon power-up. Otherwise they are never cleared. The counters are intended as a means of counting events over a long period of time, relative to the event frequency. They provide no means of extracting intermediate counter values.

Since the counters continuously accumulate selected events, despite interrupts being enabled, the first interrupt after selecting a new counter input has an error bound as large as the selected overflow range. Some inputs can overcount events occurring simultaneously with D-stream errors that abort the actual event very late in the pipeline. For example, when counting load instructions, attempts to execute a load resulting in a TB miss exception will increment the performance counter after the first aborted execution attempt and again after the TB fill routine when the load instruction reissues and completes.

Performance counter interrupts are reported six cycles after the event that caused the counter to overflow. Additional delay can occur before an interrupt is serviced if the processor is executing PALcode that always disables interrupts. Events occurring during the interval between counter overflow and interrupt service are counted toward the next interrupt. Only in the case of a complete counter wrap-around while interrupts are disabled will an interrupt be missed.

The six cycles before an interrupt is triggered implies that a maximum of 12 instructions may have completed before the start of the interrupt service routine. When counting I-cache misses, no intervening instructions can complete and the exception PC contains the address of the last I-cache miss. Branch mispredictions allow a maximum of only two instructions to complete before start of the interrupt service routine.


ICCSR W<3>
ICCSR W<3>; PC0

Performance Counter 0. (R/W0) If clear, it enables performance counter 0 interrupt request after 2**16 events counted. If set, it enables performance counter 0 interrupt request after 2**12 events counted.

Performance Counters

The performance counters are reset to zero upon power-up. Otherwise they are never cleared. The counters are intended as a means of counting events over a long period of time, relative to the event frequency. They provide no means of extracting intermediate counter values.

Since the counters continuously accumulate selected events, despite interrupts being enabled, the first interrupt after selecting a new counter input has an error bound as large as the selected overflow range. Some inputs can overcount events occurring simultaneously with D-stream errors that abort the actual event very late in the pipeline. For example, when counting load instructions, attempts to execute a load resulting in a TB miss exception will increment the performance counter after the first aborted execution attempt and again after the TB fill routine when the load instruction reissues and completes.

Performance counter interrupts are reported six cycles after the event that caused the counter to overflow. Additional delay can occur before an interrupt is serviced if the processor is executing PALcode that always disables interrupts. Events occurring during the interval between counter overflow and interrupt service are counted toward the next interrupt. Only in the case of a complete counter wrap-around while interrupts are disabled will an interrupt be missed.

The six cycles before an interrupt is triggered implies that a maximum of 12 instructions may have completed before the start of the interrupt service routine. When counting I-cache misses, no intervening instructions can complete and the exception PC contains the address of the last I-cache miss. Branch mispredictions allow a maximum of only two instructions to complete before start of the interrupt service routine.


EXC_ADDR<63:2>
EXC_ADDR<63:2>; PC

Program Counter. (R/W) Contains bits <63:2> of the PC. This field is written by hardware following an exception to provide a return address for PALcode.


EXC_ADDR<0>
EXC_ADDR<0>; PAL

PALmode. (R/W) If set, the value in EXC_ADDR<63:2> is correct. When clear, the HW_REI instruction executes a jump to native (nonPALmode) mode, enabling address translation.


EXC_ADDR IPR Usage

The instruction pointed to by the EXC_ADDR IPR did not complete its execution. The EXC_ADDR IPR is written by hardware after an exception to provide a return address for PALcode. The HW_REI instruction executes a jump to the address contained in the EXC_ADDR IPR. EXC_ADDR<0> is used to indicate PALmode to the hardware.

CALL_PAL exceptions load the EXC_ADDR with the PC of the instruction following the CALL_PAL. This function allows CALL_PAL service routines to return without needing to increment the value in the EXC_ADDR IPR. This feature requires careful treatment in PALcode. Arithmetic traps and machine check exceptions can prompt CALL_PAL exceptions resulting in an incorrect value being saved in the EXC_ADDR IPR. In the cases of an arithmetic trap or machine check exception (only in these cases), EXC_ADDR<1> takes on special meaning. PALcode servicing these two exceptions must:

•	Interpret a zero in EXC_ADDR<1> as indicating that the PC in EXC_ADDR<63:2> is too large by a value of 4 bytes and subtract 4 before executing an HW_REI from this address.

•	Interpret a one in EXC_ADDR<1> as indicating that the PC in EXC_ADDR<63:2> is correct and clear EXC_ADDR<1>.

All other PALcode entry points except reset can expect EXC_ADDR<1> to be zero. The logic allows the following code sequence to conditionally subtract 4 from the address in the EXC_ADDR register without the use of an additional register. This code sequence must be present in arithmetic trap and machine check flows only.

HW_MFPR	Rx,	EXC_ADDR	; read EXC_ADDR into GPR

SUBQ	Rx,	2,	Rx	; subtract 2 causing borrow

; if bit <1>=0

BIC	Rx,	2,	Rx	; clear bit [1]

HW_MTPR	Rx,	EXC_ADDR	; write back to EXC_ADDR

NOTE: Using the HW_MTPR instruction to update the EXC_ADDR register while in the native mode is restricted to bit <0> being equal to zero. The combination of the native mode and EXC_ADDR<0> being equal to one causes UNDEFINED behavior. This combination is only possible through the use of ICCSR<HWE>.


SL_RCV<3>
SL_RCV<3>; RCV

Serial Line Receive. (R) This bit is functionally connected to the sRomD_h pin after the I-cache is loaded from the external SROM. Using a software timing loop, RCV can be read to receive external data one bit at a time.

A serial line interrupt is requested on detection of any transition on the receive line that sets the SL_REQ bit in the HIRR IPR. The serial line interrupt can be disabled by clearing HIER<SL_EN>.


EXC_SUM<33>
EXC_SUM<33>; MSK

Mask. (RC) Exception Register Write Mask parameter window.


EXC_SUM<8>
EXC_SUM<8>; IOV

Integer Overflow. (WA) When set, indicates Fbox convert to integer overflow or integer arithmetic overflow.


EXC_SUM<7>
EXC_SUM<7>; INE

Inexact Error. (WA) When set, indicates floating inexact error.


EXC_SUM<6>
EXC_SUM<6>; UNF

Underflow. (WA) When set, indicates floating-point underflow.


EXC_SUM<5>
EXC_SUM<5>; FOV

Floating-Point Overflow. (WA) When set, indicates floating-point overflow.


EXC_SUM<4>
EXC_SUM<4>; DZE

Divide by Zero. (WA) When set, indicates divide by zero.


EXC_SUM<3>
EXC_SUM<3>; INV

Invalid. (WA) When set, indicates invalid operation.


EXC_SUM<2>
EXC_SUM<2>; SWC

Software Completion. (WA) When set, indicates software completion possible. The bit is set after a floating-point instruction containing the /S modifier completes with an arithmetic trap and all previous floating-point instructions that trapped since the last HW_MTPR EXC_SUM also contained the /S modifier. The SWC bit is cleared whenever a floating-point instruction without the /S modifier completes with an arithmetic trap. The bit remains cleared regardless of additional arithmetic traps until the register is written by way of an HW_MTPR instruction. The SWC bit is always cleared upon any HW_MTPR write to the EXC_SUM IPR.


PAL_BASE<33:14>
PAL_BASE<33:14>; PAL_BASE

PALcode Base Address. (R/W) Contains the PALcode base address.


HIRR<32:29>
HIRR<32:29>; ASTRR[3:0]

AST Request. (R) Corresponds to AST requests 3 through 0 (USEK). When a bit is set, the corresponding interrupt request is posted. The four bits are expanded as follows:

ASTRR	Operating Mode
3	UAR: User AST request
2	SAR: Supervisor AST request
1	EAR: Executive AST request
0	KAR: Kernel AST request


HIRR<28:14>
HIRR<28:14>; SIRR[15:1]

Software Interrupt Request. (R) Corresponds to software interrupt requests 15 through 1. When a bit is set, the corresponding interrupt request is posted.


HIRR<13>
HIRR<13>; SLR

Serial Line Interrupt Request. (R) When set, a serial line interrupt request is posted. See also SL_RCV, SL_XMIT, and SL_CLR.


HIRR<12:10><7:5>
HIRR<12:10><7:5>; HIRR[5:0]

Hardware Interrupt Request. (R) Reflects the state of signals Irq_h [5:0]. Any bit set in the HIRR field indicates an interrupt request on the corresponding Irq_h line.


HIRR<9>
HIRR<9>; PC0

Performance Counter 0 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC0.


HIRR<8>
HIRR<8>; PC1

Performance Counter 1 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC1.


HIRR<4>
HIRR<4>; CRR

Correctable Read. (R) When set, indicates that a correctable read error interrupt request is posted. This interrupt is cleared by way of the SL_CLR IPR.


HIRR<3>
HIRR<3>; ATR

Asynchronous Trap Request. (R) Is set if any AST request and corresponding enable is set. This bit also requires that the processor mode be equal to or higher than the request mode. SIER[2] must be asserted to allow AST interrupt requests.


HIRR<2>
HIRR<2>; SWR

Software. (R) Is set if any software interrupt request and corresponding enable is set.


HIRR<1>
HIRR<1>; HWR

Hardware. (R) Is set if any hardware interrupt request and corresponding enable is set.


SIRR<32:29>
SIRR<32:29>; USEK ASTRR[3:0]

AST Request. (R) Corresponds to AST requests 3 through 0 (USEK). When a bit is set, the corresponding interrupt request is posted. The four bits are expanded as follows:

ASTRR	Operating Mode
3	UAR: User AST request
2	SAR: Supervisor AST request
1	EAR: Executive AST request
0	KAR: Kernel AST request


SIRR<28:14>
SIRR<28:14>; SIRR[15:1]

Software Interrupt Request. (R) Corresponds to software interrupt requests 15 through 1. When a bit is set, the corresponding interrupt request is posted.


SIRR<47:33>
SIRR<47:33>; SIRR[15:1]

Software Interrupt Request. (R) Corresponds to software interrupt requests 15 through 1. When a bit is set, the corresponding interrupt request is posted.


SIRR<13>
SIRR<13>; SLR

Serial Line Interrupt Request. (R) When set, a serial line interrupt request is posted. See also SL_RCV, SL_XMIT, and SL_CLR.


SIRR<12:10><7:5>
SIRR<12:10><7:5>; HIRR[5:0]

Hardware Interrupt Request. (R) Reflects the state of signals Irq_h [5:0]. Any bit set in the HIRR field indicates an interrupt request on the corresponding Irq_h line.


SIRR<9>
SIRR<9>; PC0

Performance Counter 0 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC0.


SIRR<8>
SIRR<8>; PC1

Performance Counter 1 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC1.


SIRR<4>
SIRR<4>; CRR

Correctable Read. (R) When set, indicates that a correctable read error interrupt request is posted. This interrupt is cleared by way of the SL_CLR IPR.


SIRR<3>
SIRR<3>; ATR

Asynchronous Trap Request. (R) Is set if any AST request and corresponding enable is set. This bit also requires that the processor mode be equal to or higher than the request mode. SIER[2] must be asserted to allow AST interrupt requests.


SIRR<2>
SIRR<2>; SWR

Software. (R) Is set if any software interrupt request and corresponding enable is set.


SIRR<1>
SIRR<1>; HWR

Hardware. (R) Is set if any hardware interrupt request and corresponding enable is set.


ASTRR<32:29>
ASTRR<32:29>; USEK ASTRR[3:0]

AST Request. (R) Corresponds to AST requests 3 through 0 (USEK). When a bit is set, the corresponding interrupt request is posted. The four bits are expanded as follows:

ASTRR	Operating Mode
3	UAR: User AST request
2	SAR: Supervisor AST request
1	EAR: Executive AST request
0	KAR: Kernel AST request


ASTRR<28:14>
ASTRR<28:14>; SIRR[15:1]

Software Interrupt Request. (R) Corresponds to software interrupt requests 15 through 1. When a bit is set, the corresponding interrupt request is posted.


ASTRR<13>
ASTRR<13>; SLR

Serial Line Interrupt Request. (R) When set, a serial line interrupt request is posted. See also SL_RCV, SL_XMIT, and SL_CLR.


ASTRR<12:10><7:5>
ASTRR<12:10><7:5>; HIRR[5:0]

Hardware Interrupt Request. (R) Reflects the state of signals Irq_h [5:0]. Any bit set in the HIRR field indicates an interrupt request on the corresponding Irq_h line.


ASTRR<9>
ASTRR<9>; PC0

Performance Counter 0 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC0.


ASTRR<8>
ASTRR<8>; PC1

Performance Counter 1 Interrupt Request. (R) When set, indicates that an interrupt request is posted by PC1.


ASTRR<4>
ASTRR<4>; CRR

Correctable Read. (R) When set, indicates that a correctable read error interrupt request is posted. This interrupt is cleared by way of the SL_CLR IPR.


ASTRR<3>
ASTRR<3>; ATR

Asynchronous Trap Request. (R) Is set if any AST request and corresponding enable is set. This bit also requires that the processor mode be equal to or higher than the request mode. SIER[2] must be asserted to allow AST interrupt requests.


ASTRR<2>
ASTRR<2>; SWR

Software. (R) Is set if any software interrupt request and corresponding enable is set.


ASTRR<1>
ASTRR<1>; HWR

Hardware. (R) Is set if any hardware interrupt request and corresponding enable is set.


HIER W<32>
HIER W<32>; SLE

Serial Line Interrupt Enable. (R/W) If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


HIER R<13>
HIER R<13>; SLE

Serial Line Interrupt Enable. R/W If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


HIER<32:29>
HIER<32:29>; ASTRR[3:0]

AST Interrupt Enable. (R) Corresponds to AST interrupt enable bits 3 through 0 (USEK). If a bit is set in this field, the corresponding interrupt is enabled. The four bits are expanded as follows:

ASTRR[3:0]	Operating Mode
3	UAE: User AST interrupt enable
2	SAE: Supervisor AST interrupt enable
1	EAE: Executive AST interrupt enable
0	KAE: Kernel AST interrupt enable


HIER<28:14>
HIER<28:14>; SIER[15:1]

Software Interrupt Enable. (R) Corresponds to software interrupt requests 15 through 1. Any bit set in this field indicates that the corresponding software interrupt is enabled.


HIER R<8>
HIER R<8>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


HIER W<15>
HIER W<15>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


HIER W<14:9>
HIER W<14:9>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


HIER R<12:10><7:5>
HIER R<12:10><7:5>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


HIER W<8>
HIER W<8>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


HIER R<9>
HIER R<9>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


HIER W<2>
HIER W<2>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


HIER R<4>
HIER R<4>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


SIER W<32>
SIER W<32>; SLE

Serial Line Interrupt Enable. (R/W) If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


SIER R<13>
SIER R<13>; SLE

Serial Line Interrupt Enable. R/W If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


SIER<32:29>
SIER<32:29>; ASTRR[3:0]

AST Interrupt Enable. (R) Corresponds to AST interrupt enable bits 3 through 0 (USEK). If a bit is set in this field, the corresponding interrupt is enabled. The four bits are expanded as follows:

ASTRR[3:0]	Operating Mode
3	UAE: User AST interrupt enable
2	SAE: Supervisor AST interrupt enable
1	EAE: Executive AST interrupt enable
0	KAE: Kernel AST interrupt enable


SIER<28:14>
SIER<28:14>; SIER[15:1]

Software Interrupt Enable. (R) Corresponds to software interrupt requests 15 through 1. Any bit set in this field indicates that the corresponding software interrupt is enabled.


SIER R<8>
SIER R<8>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


SIER W<15>
SIER W<15>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


SIER W<14:9>
SIER W<14:9>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


SIER R<12:10><7:5>
SIER R<12:10><7:5>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


SIER W<8>
SIER W<8>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


SIER R<9>
SIER R<9>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


SIER W<2>
SIER W<2>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


SIER R<4>
SIER R<4>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


ASTER W<32>
ASTER W<32>; SLE

Serial Line Interrupt Enable. (R/W) If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


ASTER R<13>
ASTER R<13>; SLE

Serial Line Interrupt Enable. R/W If set, enables the serial line interrupts. See also SL_RCV, SL_XMIT, and SL_CLR.


ASTER<32:29>
ASTER<32:29>; ASTRR[3:0]

AST Interrupt Enable. (R) Corresponds to AST interrupt enable bits 3 through 0 (USEK). If a bit is set in this field, the corresponding interrupt is enabled. The four bits are expanded as follows:

ASTRR[3:0]	Operating Mode
3	UAE: User AST interrupt enable
2	SAE: Supervisor AST interrupt enable
1	EAE: Executive AST interrupt enable
0	KAE: Kernel AST interrupt enable


ASTER<28:14>
ASTER<28:14>; SIER[15:1]

Software Interrupt Enable. (R) Corresponds to software interrupt requests 15 through 1. Any bit set in this field indicates that the corresponding software interrupt is enabled.


ASTER R<8>
ASTER R<8>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


ASTER W<15>
ASTER W<15>; PC1

Performance Counter 1 Interrupt Enable. (R/W) When set, enables PC1 interrupts.


ASTER W<14:9>
ASTER W<14:9>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


ASTER R<12:10><7:5>
ASTER R<12:10><7:5>; HIER[5:0]

Hardware Interrupt Enable. (R/W) Interrupt enable bits for signals Irq_h[5:0]. Any bit set in this field enables the corresponding hardware interrupt.


ASTER W<8>
ASTER W<8>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


ASTER R<9>
ASTER R<9>; PC0

Performance Counter 0 Interrupt Enable. (R/W) When set, enables PC0 interrupts.


ASTER W<2>
ASTER W<2>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


ASTER R<4>
ASTER R<4>; CRE

Correctable Read Error Interrupt Enable. (R/W) If set, enables the interrupt. The interrupt request is cleared by way of the SL_CLR.


SL_CLR<32>
SL_CLR<32>; SLC

Serial Line Clear. (W0C) Clears the serial line interrupt request.


SL_CLR<15>
SL_CLR<15>; PC1

Performance Counter 1. (W0C) Clears the performance counter 1 interrupt request.


SL_CLR<8>
SL_CLR<8>; PC0

Performance Counter 0. (W0C) Clears the performance counter 0 interrupt request.


SL_CLR<2>
SL_CLR<2>; CRD

Correctable Read. (W0C) Clears the correctable read error interrupt request.


TB_CTL<6:5>
TB_CTL<6:5>; GH

Granularity Hint. (R/W) Selects between the DECchip 21064 TB page mapping sizes when writing or reading the ITB and the DTB. There are two sizes in the ITB and four sizes in the DTB.

TB_CTL<6:5>	ITB Page Size	DTB Page Size
00	8 Kbytes	8 Kbytes
01	8 Kbytes	8**8 Kbytes
10	8 Kbytes	64**8 Kbytes
11	512**8 Kbytes	512**8 Kbytes


MMCSR<14:9>
MMCSR<14:9>; OPCODE

Opcode. (R) Contains the Opcode field of the faulting instruction.


MMCSR<8:4>
MMCSR<8:4>; RA

Register A. (R) The RA field of the faulting instruction.


MMCSR<3>
MMCSR<3>; FOW

Fault on Write. (R) Set if the reference was a write and the PTE's FOW bit was set.


MMCSR<2>
MMCSR<2>; FOR

Fault on Read. (R) Set if the reference was a read and the PTE's FOR bit was set.


MMCSR<1>
MMCSR<1>; ACV

Access Violation. (R) Set if reference caused an access violation.


MMCSR<0>
MMCSR<0>; WR

Write. (R) Set if reference that caused error was a write.


BIU_ADDR<33:5>
BIU_ADDR<33:5>; ADDRESS

Address. (R) Reflects the states of adr_h signals [33:5] associated with the EDAL interface transaction that resulted in the error indicated in BIU_STAT<7:0>.


BIU_ADDR<4:2>
BIU_ADDR<4:2>; RB/LL

Read_Block or Load_Locked. (R) If the BIU_CMD field of the BIU_STAT IPR indicates that the transaction that received the error was Read_Block or Load_Locked, then the state of RB/LL is UNPREDICTABLE. If the BIU_CMD filed of the BIU_STAT IPR encodes any EDAL interface command other than Read_Block or Load_Locked, then RB/LL reads as zeros.


BIU_STAT<14>
BIU_STAT<14>; FATAL2

Fatal 2. (R) When set, indicates that a primary cache fill operation resulted in either a multi-bit ECC error or in a parity error while FILL_ECC or FILL_DPERR was already set.


BIU_STAT<13:12>
BIU_STAT<13:12>; FILL_QW

Fill Quadword. (R) Identifies the quadword within the hexword primary cache fill block that caused the error. This field is only meaningful when either FILL_ECC or FILL_DPERR is set. FILL_QW can be used together with FILL_ADDR<33:5> to get the complete physical address of the bad quadword.


BIU_STAT<11>
BIU_STAT<11>; FILL_IRD

Fill I-Cache Read. (R) When set, indicates that the error that caused FILL_ECC or FILL_DPERR to be set occurred during an I-cache fill. When clear, indicates that the error occurred during a D-cache fill. This bit is only meaningful when either FILL_ECC or FILL_DPERR is set.


BIU_STAT<10>
BIU_STAT<10>; FILL_DPERR

Fill Data Parity Error. (R) When set, indicates that the BIU received data with a parity error from outside the CPU chip while performing either a D-cache or I-cache fill. FILL_DPERR is only meaningful when the CPU chip is in parity mode, as opposed to ECC mode.


BIU_STAT<9>
BIU_STAT<9>; FILL_CRD

Fill Correctable Read. (R) When set, indicates that the information latched in BIU_STAT <13:8>, FILL_ADDR IPR, and FILL_SYND IPR relates to an errored quadword that does not contain multi-bit errors in either of its component longwords. This bit is only meaningful when FILL_ECC is set.


BIU_STAT<8>
BIU_STAT<8>; FILL_ECC

Fill ECC Error. (R) When set, indicates that P-cache fill data received from outside the CPU ship contained an ECC error.


BIU_STAT<7>
BIU_STAT<7>; FATAL1

Fatal 1. (R) When set, indicates that an external cycle was terminated with the cAck_h pins indicating HARD_ERROR, or that a B-cache tag probe encountered bad parity in the tag address RAM or the tag control RAM while one of BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR was already set.


BIU_STAT<6:4>
BIU_STAT<6:4>; BIU_CMD

BIU Command. (R) Latches the cycle type on the cReq_h pins when a BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR error occurs.


BIU_STAT<3>
BIU_STAT<3>; BC_TCPERR

B-Cache Tag Control Parity Error. (R) When set, indicates that an external cache tag probe encountered bad parity in the tag control RAM.


BIU_STAT<2>
BIU_STAT<2>; BC_TPERR

B-Cache Tag Parity Error. (R) When set, indicates that an external cache tag probe encountered bad parity in the tag address RAM.


BIU_STAT<1>
BIU_STAT<1>; BIU_SERR

BIU Soft Error. (R) When set, indicates that an external cycle was terminated with the cAck_h pins indicating SOFT_ERROR.


BIU_STAT<0>
BIU_STAT<0>; BIU_HERR

BIU Hard Error. (R) When set, indicates that an external cycle was terminated with the cAck_h pins indicating HARD_ERROR.


DC_STAT<3>
DC_STAT<3>; DC_HIT

D-Cache Hit. (R) Indicates whether the last load or store instruction processed by the Abox hit (DC_HIT set) or missed (DC_HIT clear) the D-cache. Loads that miss the D-cache can be completed without requiring external reads.


DC_STAT<2:0>
DC_STAT<2:0>; CHIP_ID

Chip Identification. (R) This field has a value of 111 (bin) for Revision 3 DECchip 21064 processors. Any other value in this field indicates a lower revision level.


FILL_ADDR<33:5>
FILL_ADDR<33:5>; ADDRESS

Address. (R) Identifies the 32-byte cache block that the CPU was attempting to read when the error occurred.


FILL_ADDR<4:2>
FILL_ADDR<4:2>; PA/UNP

Physical Address or Unpredictable. (R) If the FILL_IRD bit of the BIU_STAT IPR is clear, it indicates that the error occurred during a D-stream cache fill. At such times, PA/UNP contains bits <4:2> of the physical address generated by the load instruction that triggered the cache fill. If FILL_IRD is set, then the state of PA/UNP is UNPREDICTABLE.


ABOX_CTL<11>
ABOX_CTL<11>; DC_FHIT

D-Cache Force Hit. (W, 0) When set, this bit forces all D-stream references to hit in the D-cache. This bit takes precedence over DC_EN. That is, when DC_FHIT is set and DC_EN is clear, all D-stream references hit in the D-cache.


ABOX_CTL<10>
ABOX_CTL<10>; DC_EN

D-Cache Enable. (W, 0) When clear, this bit disables and flushes the D-cache. When set, this bit enables the D-cache.


ABOX_CTL<6>
ABOX_CTL<6>; EMD_EN

Endian Mode Enable. (W, 0) Used to provide limited hardware support for big endian data formats. When set, this bit enables the D-cache.


ABOX_CTL<5>
ABOX_CTL<5>; SPE_2

Superpage Enable 2. (W, 0) When set, enables one-to-one superpage mapping of the D-stream virtual addresses with VA <33:13> directly to physical addresses PA <33:13>, if virtual address bits VA <42:41> = 2. Virtual address bits VA <40:34> are ignored in this translation. Access is only allowed in kernel mode.


ABOX_CTL<4>
ABOX_CTL<4>; SPE_1

Superpage Enable 1. (W, 0) When set, enables one-to-one superpage mapping of the D-stream virtual addresses with VA <42:30> = 1FFE to the physical addresses with PA <33:30> = 0. Access is allowed only in kernel mode.


ABOX_CTL<3>
ABOX_CTL<3>; IC_SBUF_EN

I-Cache Stream Buffer Enable. (W, 0) When set, enables operation of a single-entry I-cache stream buffer.


ABOX_CTL<2>
ABOX_CTL<2>; CRD_EN

Correctable Read Interrupt Enable. (W, 0) When set, the Abox generates an interrupt request whenever an EDAL interface transaction is terminated with a cAck_h code of SOFT_ERROR.


ABOX_CTL<1>
ABOX_CTL<1>; MCHK_EN

Machine Check Enable. (W, 0) When set, the Abox generates a machine check when errors (that are not correctable by the hardware) are encountered. When cleared, uncorrectable errors do not cause a machine check. However, the BIU_STAT, DC_STAT, BIU_ADDR, and FILL_ADDR IPRs are updated and locked when the errors occur.


ABOX_CTL<0>
ABOX_CTL<0>; WB_DIS

Write Buffer Unload Disable. (W, 0) When set, prevents the write buffer from sending write data to the BIU. This bit should be set only by diagnostics.


ALT_MODE<4:3>
ALT_MODE<4:3>; AM

Alternate Mode. (W) Specifies the alternate processor mode used by HW_LD and HW_ST instructions that have their ALT bit (<14>) set. The alternate modes are selected as follows:

AM	Processor Mode
00	Kernel
01	Executive
10	Supervisor
11	User


BIU_CTL<36>
BIU_CTL<36>; BAD_DP

Bad Data Parity. (W, 0) When set, causes the DECchip 21064 to invert the value placed on bits <0, 7, 14, 21> of the check_h [27:0] field during off-chip writes. This produces bad parity when the DECchip 21064 is in parity mode and bad check bit codes when in ECC mode.


BIU_CTL<35:32>
BIU_CTL<35:32>; BC_PA_DIS

B-Cache Physical Address Disable. (W, 0) This 4-bit field is used to prevent the CPU chip from using the B-cache to service reads and writes based upon the quadrant of physical address space that they reference. The correspondence between this bit field and the physical address space is as follows:

BIU_CTL Bits	Physical Address
<35>	PA <33:32> = 3
<34>	PA <33:32> = 2
<33>	PA <33:32> = 1
<32>	PA<33:32> = 0
When a read or write reference is presented to the BIU, the values of BC_PA_DIS, BC_EN, and the physical address bits <33:32> determine whether an attempt is to be made to use the B-cache to satisfy the reference. If the B-cache is not to be used for a given reference, the BIU does not probe the tag store and makes the appropriate system request immediately. The value of BC_PA_DIS has no impact on which portions of the physical address space may be cached in the P-cache. System components control this by way of the dRAck_h field of the EDAL interface.


BIU_CTL<31>
BIU_CTL<31>; BAD_TCP

Bad Tag Control Parity. (W, 0) When set, causes the DECchip 21064 to write bad parity into the tag control RAM whenever DECchip 21064 does a fast B-cache write.


BIU_CTL<30:28>
BIU_CTL<30:28>; BC_SIZE

B-Cache Size. (W, 0) This field is used to indicate the size of the B-cache as follows:

BC_SIZE	Size of B-Cache
000	128 Kbytes
001	256 Kbytes
010	512 Kbytes
011	1 Mbyte
100	2 Mbytes
101	4 Mbytes
110	8 Mbytes


BIU_CTL<27:13>
BIU_CTL<27:13>; BC_WE_CTL

B-Cache Write Enable Control. (W, 0) This field is used to control the timing of the write enable and chip enable signals during writes into the data and tag control RAMs. It consists of 15 bits, where each bit determines the value placed on the write enable and chip enable signals during a given CPU cycle of the RAM write access. When a given bit of the BC_WE_CTL is set, the write enable and chip enable signals are asserted during the corresponding CPU cycle of the RAM access. BIU_CTL<13> corresponds to the second cycle of the write access, BIU_CTL<14> to the third CPU cycle, and so on. The write enable signals will never be asserted in the first CPU cycle of a RAM write access. Unused bits in this field must be written with zeros.


BIU_CTL<11:8>
BIU_CTL<11:8>; BC_WR_SPD

B-Cache Write Speed. (W, 0) Indicates to the BIU the write cycle time of the RAMs used to implement the off-chip B-cache, measured in CPU cycles. It should be written with a value equal to one less than the write cycle time of the B-cache RAMs. The access times for writes must be in the range of 16 to 2 CPU cycles, which means that the values for the BC_RD_SPD field are in the range of 15 to 1.


BIU_CTL<7:4>
BIU_CTL<7:4>; BC_RD_SPD

B-Cache Read Speed. (W, 0) Indicates to the BIU the read access time of the RAMs used to implement the off-chip B-cache, measured in CPU cycles. It should be written with a value equal to one less than the read access time of the B-cache RAMs. The access times for reads must be in the range of 16 to 4 CPU cycles, which means that the values for the BC_RD_SPD field are in the range of 15 to 3.


BIU_CTL<3>
BIU_CTL<3>; BC_FHIT

B-Cache Force Hit. (W, 0) When this bit is set and the BC_EN bit is also set, all EDAL interface Read_Block and Write_Block transactions are forced to hit in the B-cache. Tag and tag control parity are ignored. The BC_EN takes precedence over BC_FHIT. When BC_EN is cleared and BC_FHIT is set, no tag probes occur and external requests are directed to the cReq_h pins.

NOTE: The BC_PA_DIS field takes precedence over BC_FHIT.


BIU_CTL<2>
BIU_CTL<2>; OE

Output Enable. (W, 0) When set, the DECchip 21064 does not assert its chip enable signals during RAM write cycles, thus allowing the corresponding pins to be connected to the output enable pins of the cache RAMs.


BIU_CTL<1>
BIU_CTL<1>; ECC

Error Checking and Correction. (W, 0) When set, the DECchip 21064 generates/expects ECC on the check_h pins. When cleared, the DECchip 21064 generates/expects parity on four of the check_h signals.


BIU_CTL<0>
BIU_CTL<0>; BC_EN

B-Cache Enable. (W, 0) When cleared, the B-cache is disabled. When the B-cache is disabled, the BIU does not probe the B-cache tag store for read/write references; it launches a request on cReq_h immediately.


FILL_SYND<13:7>
FILL_SYND<13:7>; HI<6:0>

High <6:0>. (R) Contains the syndrome associated with the upper longword of the quadword. If the processor is operating in parity mode, bit <0> (FILL_SYND<7>) of this field is set to indicate that the upper longword was corrupted. Bits <6:1> (FILL_SYND<13:8>) read as zeros in parity mode.


FILL_SYND<6:0>
FILL_SYND<6:0>; LO<6:0>

Low <6:0>. (R) Contains the syndrome associated with the lower longword of the quadword. If the processor is operating in parity mode, bit <0> (FILL_SYND<0>) of this field is set to indicate that the lower longword was corrupted. Bits <6:1> (FILL_SYND<6:1>) read a zeros in parity mode.


Syndromes for Single-Bit Errors

Data	Syndrome	Check	Syndrome
<0>	4F	0	01
<1>	4A	1	02
<2>	52	2	04
<3>	54	3	08
<4>	57	4	10
<5>	58	5	20
<6>	5B	6	40
<7>	5D
<8>	23
<9>	25
<10>	26
<11>	29
<12>	2A
<13>	2C
<14>	31
<15>	34
<16>	0E
<17>	0B
<18>	13
<19>	15
<20>	16
<21>	19
<22>	1A
<23>	1C
<24>	62
<25>	64
<26>	67
<27>	68
<28>	6B
<29>	6D
<30>	70
<31>	75


BC_TAG<22>
BC_TAG<22>; TAGADR_P

Tag Address Parity. (R) Reflects the state of the tagAdrP_h signal of the DECchip 21064 when a tag, tag control, or data parity error occurs.


BC_TAG<21:5>
BC_TAG<21:5>; TAG<33:17>

Tag. (R) Contains the tag that is being probed currently. NOTE: Unused bits in the TAG field are always clear, based on the size of the B-cache, as determined by BIU_CTL<BC_SIZE>.


BC_TAG<4>
BC_TAG<4>; TAGCTL_V

Tag Control Valid. (R) Reflects the state of the tagCtlV_h signal of the DECchip 21064 when a tag, tag control, or data parity error occurs.


BC_TAG<3>
BC_TAG<3>; TAGCTL_S

Tag Control Shared. (R) Reflects the state of the tagCtlS_h signal of the DECchip 21064 when a tag, tag control, or data parity error occurs.


BC_TAG<2>
BC_TAG<2>; TAGCTL_D

Tag Control Dirty. (R) Reflects the state of the tagCtlD_h signal of the DECchip 21064 when a tag, tag control, or data parity error occurs.


BC_TAG<1>
BC_TAG<1>; TAGCTL_P

Tag Control Parity. (R) Reflects the state of the tagCtlP_h signal of the DECchip 21064 when a tag, tag control, or data parity error occurs.


BC_TAG<0>
BC_TAG<0>; HIT

Hit. (R) When set, indicates that there was a tag match when a tag, tag control, or data parity error occured.


XDEV <31:28>
XDEV<31:28>; RSVD

Reserved. (RO) Must be zero.


XDEV<27:24>
XDEV<27:24>; LGA_REV

LGA Revision. (RO) DWLMA gate array revision.


XDEV<23:20>
XDEV<23:20>; RSVD

Reserved. (RO) Must be zero.


XDEV<19:16>
XDEV<19:16>; DREV

Device Revision. (RO) Identifies the revision of the DWLMA module.


XDEV<15:0>
XDEV<15:0>; DTYPE

Device Type. (RO) Identifies the type of node. For the DWLMA this field is 102A (hex).


XBER<31>
XBER<31>; ES

Error Summary. (RO) Sets whenever any bit in the XBER<27:10> range sets.


XBER<30>
XBER<30>; NRST

Node Reset. (RO) Not implemented.


XBER<29>
XBER<29>; NHALT

Node Halt. (RO) Not implemented.


XBER<28>
XBER<28>; XBAD

XMI Bad. (RO) Indicates the state of the XMI BAD signal. When set, the signal is asserted.


XBER<27>
XBER<27>; CC

Corrected Confirmation. (W1C) When set, indicates that a single-bit CNF error has been detected.


XBER<26>
XBER<26>; XFAULT

XMI Fault. (RO) Not implemented.


XBER<25>
XBER<25>; WEI

Write Error Interrupt. (W1C) When set, indicates that a write error interrupt has been received. While the bit is set, all other IVINTRs are NO ACKed.


XBER<24>
XBER<24>; IPE

Inconsistent Parity Error. (W1C) When set, indicates that the DWLMA detected bad parity on the XMI when another node (the responder) detected good parity and ACKed the same cycle.


XBER<23>
XBER<23>; PE

Parity Error. (W1C) When set, indicates that the DWLMA detected a parity error on the XMI.


XBER<22>
XBER<22>; WSE

Write Sequence Error. (W1C) When set, indicates that the DWLMA aborted a write transaction due to missing data cycles.


XBER<21>
XBER<21>; RIDNAK

READ/IDENT Data NO ACK. (W1C) When set, indicates that a read data or IDENT cycle transmitted by the DWLMA received a NO ACK confirmation.


XBER<20>
XBER<20>; WDNAK

Write Data NO ACK. (W1C) When set, indicates that a write data cycle transmitted by the DWLMA received a NO ACK and timed out.


XBER<19>
XBER<19>; CRD

Corrected Read Data. (W1C) When set, indicates that the DWLMA received a CRD response to an I/O read request.


XBER<18>
XBER<18>; NRR

No Read Response. (W1C) When set, indicates that an I/O read request or IDENT initiated by the DWLMA failed due to a read response timeout.


XBER<17>
XBER<17>; RSE

Read Sequence Error. (W1C) When set, indicates that the DWLMA received a return read data function code other than a CRD0 or GRD0 to a CPU read request or IDENT.


XBER<16>
XBER<16>; RER

Read Error Response. (W1C) When set, indicates that an RER read data function code was received to a read request or IDENT.


XBER<15>
XBER<15>; CNAK

Command NO ACK. (W1C) When set, indicates that a command cycle transmitted by the DWLMA received a NO ACK and timed out.


XBER<14>
XBER<14>; RSVD

Reserved. (RO) Must be zero.


XBER<13>
XBER<13>; TTO

Transaction Timeout. (W1C) When set, indicates that a transaction initiated by the DWLMA failed due to a transaction timeout. Write Data NO ACK (WDNAK), No Read Response (NRR), or Command NO ACK (CNAK) indicate the reason for the timeout. If none of these bits are set, the DWLMA was not granted the XMI bus.


XBER<12>
XBER<12>; NSES

Node-Specific Error Summary. (W1C) This bit is set when any one of the following bits in the LERR are set: DHDPE, MBPE, MBIC, MBIA, DFDPE, RBDPE, MBOF, or FE.


XBER<11>
XBER<11>; ETF

Extended Test Fail. (RO) Not implemented, reads as zero.


XBER<10>
XBER<10>; STF

Self-Test Fail. (W1C) When set, indicates that the DWLMA has not yet successfully completed self-test. This bit is cleared by the console software when self-test completes successfully.


XBER<9:4>
XBER<9:4>; FCID

Failing Commander ID. (RO) This field logs the commander ID of a failing I/O or IDENT transaction initiated by the DWLMA. These bits are locked under the same conditions as the XFADR register.


XBER<3>
XBER<3>; EHWW

Enable Hexword Write. (RO) Not implemented, reads as zero.


XBER<2>
XBER<2>; DXTO

Disable XMI Timeout. (R/W) This bit is used to enable/disable the reporting of all XMI timeouts by a commander. When this bit is set, the DWLMA never encounters a TTO or an NRR. LDIAG<14>, Disable Retries, overrides this bit. If LDIAG<14> is set, the DWLMA sets TTO or NRR on the first error.


XBER<1>
XBER<1>; EMP

Enable More Protocol. (R/W) When this bit is clear, the DWLMA ignores the state of the More bit (D<59> of an XMI command/address cycle). When the bit is set, the DWLMA buffers More stream Writes into double hexwords and prefetches read data for More stream Reads.


XBER<0>
XBER<0>; RSVD

Reserved. (RO) Must be zero.


XFADR<31:30>
XFADR<31:30>; FLN

Failing Length. (RO) Logs the value of XMI D<31:30>, the length of the failing transaction.


XFADR<29:0>
XFADR<29:0>; FADRA

Failing Address. (RO) Logs the value of XMI D<29:0>, the failing address.


IBR<31:3>
IBR<31:3>; RSVD

Reserved. (MBZ) Must be zero.


IBR<2>
IBR<2>; SCLK

Serial Clock Input. (R/W) Used to implement the SEEPROM serial clock interface. When the bit is set by software, the SEEPROM serial clock input is forced high. When the bit is cleared by software, the SEEPROM serial clock input is forced low.


IBR<1>
IBR<1>; XMT_SDAT

Transmit Serial Data. (R/W) Used to assert the serial data line of the SEEPROM to either a high or low level. It is used, in conjunction with SCLK by the software, to transfer command, address, and write data to the SEEPROM.


IBR<0>
IBR<0>; RCV_SDAT

Receive Serial Data. (RO) Returns the status of the SEEPROM serial data line. It is used by software to receive serial read data and SEEPROM responses. XMT_SDAT must be set to receive a SEEPROM response or serial read data.


XFAER<31:28>
XFAER<31:28>; FCMD

Failing XMI Command. (RO) Logs the value of XMI D<63:60> lines during the command cycle. These D lines contain the command code of the failing transaction.


XFAER<27:26>
XFAER<27:26>; RSVD

Reserved. (RO) Must be zero.


XFAER<25:16>
XFAER<25:16>; ADR

Address Extension. (RO) Logs the value of XMI D <57:48> during the command cycle of a failing transaction. These D lines are address bits <38:29> of the failing transaction.


XFAER<15:0>
XFAER<15:0>; MASK

Mask. (RO) Logs the value of XMI D <47:32> during the command cycle of a failing transaction. These D lines contain the write mask for write transactions and are undefined for other transactions.


LDIAG<31:28>
LDIAG<31:28>; NODE

Node ID. (RO) Contains the XMI node ID.


LDIAG<27:26>
LDIAG<27:26>; DLLF

DMA Loopback Length Field. (R/W) This field allows diagnostic software to force the length of a DMA loopback read/write transaction to: 00:HW, 01:LW, 10:QW, 11:OW.


LDIAG<25>
LDIAG<25>; AS

ARB Supress Status. (RO) When clear, indicates that a node on the XMI is asserting ARB Suppress.


LDIAG<24>
LDIAG<24>; LOCK

Lockout Status. (RO) When clear, indicates that Lockout is asserted on the XMI.


LDIAG<23>
LDIAG<23>; LOOP

DMA Loopback Mode. (R/W) Setting this bit places the DWLMA in loopback mode.


LDIAG<22:21>
LDIAG<22:21>; FRRM

Force Read Response Mode. (R/W) This field allows diagnostics to force all variations of response to read commands. The DWLMA returns the following response codes to DMA or register read data: 00:Normal, 01:CRD, 10:GRD01, 11:RER.


LDIAG<20>
LDIAG<20>; CRE

Commander Request Enable. (R/W) When clear, the DWLMA uses XMI RES REQ to request the XMI bus. When set, I/O commands use XMI CMD REQ and the return read data uses XMI RES REQ. Under normal circumstances the DWLMA always uses XMI RES REQ.


LDIAG<19:16>
LDIAG<19:16>; FPE

Force Parity Errors. (R/W)

Bits <19:16>	Function
0000	Normal operation, correct parity asserted.
0001	Force parity error, XCI_P<0>, CMD cycle
0010	Force parity error, XCI_P<1>, CMD cycle
0011	Force parity error, XCI_P<2>, CMD cycle
0100	Reserved
0101	Force parity error, XCI_P<0>, data cycle
0110	Force parity error, XCI_P<1>, data cycle
0111	Force parity error, XCI_P<2>, data cycle
1000	Force parity error, DDP<0> on the first longword of the next packet coming into the LGA from the Down Hose. The field is cleared when the error is reported.
1001	Force parity error, DDP<1> on the second longword of the next packet coming into the LGA from the Down Hose. The field is cleared when the error is reported.
1010	Force parity error, UPP<1:0>, all valid cycles that are stored in Up Hose memory.
1011	Reserved
1100	Reserved
1101	Reserved
1110	Reserved
1111	Reserved


LDIAG<15>
LDIAG<15>; FWSE

Force Write Sequence Error. (R/W) When set, the DWLMA forces a WSE on any write transaction it issues. This bit is used only for diagnostic testing of the WSE bit.


LDIAG<14>
LDIAG<14>; DRNK

Disable Retries on NO ACK. (R/W) When set, the DWLMA flags an error on the first NO ACK received from the XMI.


LDIAG<13>
LDIAG<13>; RSVD

Reserved. (RO) Must be zero.


LDIAG<12:11>
LDIAG<12:11>; ASM

ARB Suppress Modes. (R/W)

Bits <12:11>	Free Queue Locations when ARB Suppress Is Asserted
00	6 Default
01	8
10	16 Causes ARB Suppress to assert unconditionally.
11	16 Causes ARB Suppress to assert unconditionally.


LDIAG<10>
LDIAG<10>; FXA

Force XMI Register Access. (R/W) When set, this bit forces all DWLMA registers to be accessed by self-directed XMI transactions when using mailbox commands with DWLMA node space addresses.


LDIAG<9>
LDIAG<9>; STE

Short XMI Timeout Enable. (R/W) When set, XMI timeouts are 1 to 2 ms. instead of the normal 16 ms.


LDIAG<8>
LDIAG<8>; F39

Force Address Bit 39 to One. (R/W) When set, address bit <39> is forced to a one when an address is sent on the Up Hose. When clear, address bit <39> is forced to a zero when an address is sent on the Up Hose.


LDIAG<7:0>
LDIAG<7:0>; RSVD

Reserved. (RO) Must be zero.


IMSK<31:28>
IMSK<31:28>; RSVD

Reserved. (RO) Must be zero.


IMSK<27>
IMSK<27>; ICC

CC Interrupt. (R/W) Interrupt on corrected confirmation error.


IMSK<26>
IMSK<26>; RSVD

Reserved. (RO) Must be zero.


IMSK<25>
IMSK<25>; IWEI

WEI Interrupt. (R/W) Interrupt on write error interrupt.


IMSK<24>
IMSK<24>; IIPE

IPE Interrupt. (R/W) Interrupt on XMI inconsistent parity error.


IMSK<23>
IMSK<23>; IXPE

XMI PE Interrupt. (R/W) Interrupt on XMI parity error.


IMSK<22>
IMSK<22>; IWSE

WSE Interrupt. (R/W) Interrupt on write sequence error.


IMSK<21>
IMSK<21>; IRIDNAK

Read/IDENT Data NO ACK Interrupt. (R/W) Interrupt on a Read/IDENT data NO ACK error.


IMSK<20>
IMSK<20>; IWDNAK

WDNAK Interrupt. (R/W) Interrupt on write data NO ACK error.


IMSK<19>
IMSK<19>; ICRD

CRD Interrupt. (R/W) Interrupt on corrected read data.


IMSK<18>
IMSK<18>; INRR

NRR Interrupt. (R/W) Interrupt on no read response.


IMSK<17>
IMSK<17>; IRSE

RSE Interrupt. (R/W) Interrupt on read sequence error.


IMSK<16>
IMSK<16>; IRER

RER Interrupt. (R/W) Interrupt on read error response.


IMSK<15>
IMSK<15>; ICNAK

CNAK Interrupt. (R/W) Interrupt on command NO ACK.


IMSK<14>
IMSK<14>; RSVD

Reserved. (RO) Must be zero.


IMSK<13>
IMSK<13>; ITTO

TTO Interrupt. (R/W) Interrupt on transaction timeout.


IMSK<12:7>
IMSK<12:7>; RSVD

Reserved. (RO) Must be zero.


IMSK<6>
IMSK<6>; IDFDPE

DFDPE Interrupt. (R/W) Interrupt on data FIFO data field parity error.


IMSK<5>
IMSK<5>; IRBDPE

RBDPE Interrupt. (R/W) Interrupt on read buffer data parity error.


IMSK<4>
IMSK<4>; IMBER

MBER Interrupt. (R/W) Interrupt on mailbox errors (MBOF, MBPE, MBIC, MBIA).


IMSK<3:0>
IMSK<3:0>; RSVD

Reserved. (RO) Must be zero.


LEVR<31:16>
LEVR<31:16>; RSVD

Reserved. (RO) Must be zero.


LEVR<15:0>
LEVR<15:0>; VEC

Vector. (R/W) This field contains the vector supplied with error interrupts to CPU(s) on the LSB. Operating system software initializes this register.


LERR<31:29>
LERR<31:29>; XMIPE

XMI Parity Error. (RO) This field represents which parity bit failed when XBER<23> is set. These bits are cleared when XBER<23> is cleared.


LERR<28>
LERR<28>; DHDPE

Down Hose Data Parity Error. (W1C) When set, indicates that the Down Hose data lines have a parity error while the DNDATAVAL line is asserted.


LERR<27:19>
LERR<27:19>; RSVD

Reserved. (RO) Must be zero.


LERR<18:15>
LERR<18:15>; IVID

IVINTR Source ID. (RO) This field contains the source node ID for the last IVINTR. This field is valid only when WEI, XBER<25>, is set.


LERR<14>
LERR<14>; MBPE

Mailbox Parity Error. (W1C) When set, indicates that a mailbox packet had a parity error on the Down Hose. The error bit in the Mailbox Status Return packet is set.


LERR<13>
LERR<13>; MBIC

Mailbox Illegal Command. (W1C) When set, indicates that the mailbox packet had an illegal command. The error bit in the Mailbox Status Return packet is set.


LERR<12>
LERR<12>; MBIA

Mailbox Illegal Address. (W1C) When set, indicates that the mailbox packet had an illegal DWLMA address. The error bit in the Mailbox Status Return packet is set.


LERR<11:7>
LERR<11:7>; RSVD

Reserved. (RO) Must be zero.


LERR<6>
LERR<6>; DFDPE

Data FIFO Data Field Parity Error. (W1C) When set, indicates that there was a data parity error on one of the longwords of a DMA Read Return packet. If the DHDPE is also set, the parity error most likely occurred on the Down Hose.


LERR<5>
LERR<5>; RBDPE

Read Buffer Data Parity Error. (W1C) When set, indicates that there was a data parity error on one of the longwords of a More Read stream that was stored in the read buffer. If the DHDPE bit is also set, the parity error most likely took place on the Down Hose.


LERR<4>
LERR<4>; MBOF

Mailbox Overflow. (W1C) When set, indicates that another mailbox command came from the IOP while a mailbox command was still in progress.


LERR<3>
LERR<3>; FE

Fatal Error. (W1C) When set, indicates that a fatal error has occurred.


LERR<2:0>
LERR<2:0>; RSVD

Reserved. (RO) Must be zero.


LGPR<31:0>
LGPR<31:0>; Data

Data. (R/W) Used during DMA read loopback testing as a temporary storage location.


IPR1<31:28>
IPR1<31:28>; IP8<3:0>

(RO) Interrupt-pending bits for node 8. When set, bits <28> through <31> correspond to IPL levels 14 through 17.


IPR1<27:24>
IPR1<27:24>; IP7<3:0>

(RO) Interrupt-pending bits for node 7. When set, bits <24> through <27> correspond to IPL levels 14 through 17.


IPR1<23:20>
IPR1<23:20>; IP6<3:0>

(RO) Interrupt-pending bits for node 6. When set, bits <20> through <23> correspond to IPL levels 14 through 17.


IPR1<19:16>
IPR1<19:16>; IP5<3:0>

(RO) Interrupt-pending bits for node 5. When set, bits <16> through <19> correspond to IPL levels 14 through 17.


IPR1<15:12>
IPR1<15:12>; IP4<3:0>

(RO) Interrupt-pending bits for node 4. When set, bits <12> through <15> correspond to IPL levels 14 through 17.


IPR1<11:8>
IPR1<11:8>; IP3<3:0>

(RO) Interrupt-pending bits for node 3. When set, bits <8> through <11> correspond to IPL levels 14 through 17.


IPR1<7:4>
IPR1<7:4>; IP2<3:0>

(RO) Interrupt-pending bits for node 2. When set, bits <4> through <7> correspond to IPL levels 14 through 17.


IPR1<3:0>
IPR1<3:0>; IP1<3:0>

(RO) Interrupt-pending bits for node 1. When set, bits <0> through <3> correspond to IPL levels 14 through 17.


IPR2<31>
IPR2<31>; LEIP

(RO) DWLMA Error Interrupt Pending bit.


IPR2<30:24>
IPR2<30:24>; RSVD

(RO) Reserved; must be zero.


IPR2<23:20>
IPR2<23:20>; IP14<3:0>

(RO) Interrupt-pending bits for node 14. When set, bits <20> through <23> correspond to IPL levels 14 through 17.


IPR2<19:16>
IPR2<19:16>; IP13<3:0>

(RO) Interrupt-pending bits for node 13. When set, bits <16> through <19> correspond to IPL levels 14 through 17.


IPR2<15:12>
IPR2<15:12>; IP12<3:0>

(RO) Interrupt-pending bits for node 12. When set, bits <12> through <15> correspond to IPL levels 14 through 17.


IPR2<11:8>
IPR2<11:8>; IP11<3:0>

(RO) Interrupt-pending bits for node 11. When set, bits <8> through <11> correspond to IPL levels 14 through 17.


IPR2<7:4>
IPR2<7:4>; IP10<3:0>

(RO) Interrupt-pending bits for node 10. When set, bits <4> through <7> correspond to IPL levels 14 through 17.


IPR2<3:0>
IPR2<3:0>; IP9<3:0>

(RO) Interrupt-pending bits for node 9. When set, bits <0> through <3> correspond to IPL levels 14 through 17.


IIPR<31:20>
IIPR<31:20>; RSVD

Reserved. (RO) Must be zero.


IIPR<19:16>
IIPR<19:16>; IDENTID

IDENT ID. (RO) Node ID of the IDENT in progress.


IIPR<15:12>
IIPR<15:12>; IPL17ID<3:0>

(RO) Node ID of interrupt in progress at IPL 17.


IIPR<11:8>
IIPR<11:8>; IPL16ID<3:0>

(RO) Node ID of interrupt in progress at IPL 16.


IIPR<7:4>
IIPR<7:4>; IPL15ID<3:0>

(RO) Node ID of interrupt in progress at IPL 15.


IIPR<3:0>
IIPR<3:0>; IPL14ID<3:0>

(RO) Node ID of interrupt in progress at IPL 14.


LDEV<31:16>
LDEV<31:16>; DREV

Device Revision. (R/W) Identifies the functional revision level of the module. The value of this field is contained in the EEPROM of the memory module and is loaded into the LDEV register by console software at system initialization. For the MS7AA memory module, the value of this field is zero.


LDEV<15:0>
LDEV<15:0>; DTYPE

Device Type. (R/W) Loaded at initialization with a value of 4000 (hex), which identifies the node as a memory module. The device type may be modified by console software when the device type field is fetched from the serial EEPROM located on the memory module.


LBER<31:19>
LBER<31:19>; RSVD

Reserved. (R/W, 0)


LBER<18>
LBER<18>; NSES

Node-Specific Error Summary. (RO, 0) Set when one of bits <11>, <10>, <9>, <5>, or <4> of the MERA register is set.


LBER<17>
LBER<17>; CTCE

Control Transmit Check Error. (W1C, 0) Not implemented on memory.


LBER<16>
LBER<16>; DTCE

Data Transmit Check Error. (W1C, 0) Not implemented on memory.


LBER<15>
LBER<15>; DIE

DIRTY Error. (W1C, 0)


LBER<14>
LBER<14>; SHE

SHARED Error. (W1C, 0) Not implemented on memory.


LBER<13>
LBER<13>; CAE

Command/Address Error. (W1C, 0)


LBER<12>
LBER<12>; NXAE

Nonexistent Address Error. (W1C, 0) Not implemented on memory.


LBER<11>
LBER<11>; CNFE

CNF Error. (W1C, 0)


LBER<10>
LBER<10>; STE

STALL Error. (W1C, 0)


LBER<9>
LBER<9>; TDE

Transmitter During Error. (W1C, 0)


LBER<8>
LBER<8>; CDPE2

Second CSR Data Parity Error. (W1C, 0) Not implemented on memory.


LBER<7>
LBER<7>; CDPE

CSR Data Parity Error. (W1C, 0) Not implemented on memory.


LBER<6>
LBER<6>; CPE2

Second Command Parity Error. (W1C, 0)


LBER<5>
LBER<5>; CPE

Command Parity Error. (W1C, 0)


LBER<4>
LBER<4>; CE2

Second Correctable Data Error. (W1C, 0)


LBER<3>
LBER<3>; CE

Correctable Data Error. (W1C, 0)


LBER<2>
LBER<2>; UCE2

Second Uncorrectable Data Error. (W1C, 0)


LBER<1>
LBER<1>; UCE

Uncorrectable Data Error. (W1C, 0)


LBER<0>
LBER<0>; E

Error. (W1C, 0) Signals assertion of error line.


LCNR<31>
LCNR<31>; STF

Self-Test Fail. (R/W, 1) When set, indicates that this node has not yet completed self-test. Memory clears this bit at the completion of self-test regardless of defective locations found in the DRAM array.


LCNR<30>
LCNR<30>; NRST

Node Reset. (WO, 0) When set, the node enters console mode and undergoes a reset sequence. CSRs are reset to their initialized state. Any pending transactions are lost or left uncompleted. Memory self-test halts, if running, and does not restart. An internally generated reset signal remains asserted for 16 LSB bus cycles after NRST is set, providing sufficient time to reset memory state and clear NRST. If NRST is set, a value of zero must be written to the MDRA register; otherwise, the memory operation is UNDEFINED.


LCNR<29>
LCNR<29>; NHALT

Node Halt. (R0) Not implemented on memory.


LCNR<28>
LCNR<28>; RSTSTAT

Reset Status. (R0) Not implemented on memory.


LCNR<27:1>
LCNR<27:1>; RSVD

Reserved. (R0) Read as zero.


LCNR<0>
LCNR<0>; CEEN

Correctable Error Detection Enable. (R/W, 0) When set, enables detection of correctable errors.


IBR<31:3>
IBR<31:3>; MBZ

Must Be Zero. (R/W, 0) Must always be written as zero.


IBR<2>
IBR<2>; SCLK

Serial Clock. (R/W, 0) Used by software to implement the EEPROM serial clock interface. When this bit is written with a one, the EEPROM serial clock input is forced to logic high. When it is cleared, the serial clock input is forced to logic low.


IBR<1>
IBR<1>; XMT_SDAT

Transmit Serial Data. (R/W, 1) Used by software to assert the serial data line of the EEPROM to either high or low logic levels. This bit is used with SCLK to transfer command/address and write data to the EEPROM.


IBR<0>
IBR<0>; RCV_SDAT

Receive Serial Data. (RO, 1) Returns the status of the EEPROM serial data line. Used by software to receive serial read data and EEPROM responses. XMT_SDAT must be one to receive an EEPROM response or serial read data.


LBESR<31:7>
LBESR<31:7>; RSVD

Reserved. (R0) Read as zero.


LBESR<6:0>
LBESR<6:0>; SYND_0

Syndrome 0. (RO, 0) Syndrome computed from D<31:0> and ECC<6:0> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_1

Syndrome 1. (RO, 0) Syndrome computed from D<63:32> and ECC<13:7> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_2

Syndrome 2. (RO, 0) Syndrome computed from D<95:33> and ECC<20:14> during error cycle.


LBESR<6:0>
LBESR<6:0>; SYND_3

Syndrome 3. (RO, 0) Syndrome computed from D<127:96> and ECC<27:21> during error cycle.


LBECR<31:0>
LBECR<31:0>; CA

Command/Address. (RO) Contents of D<31:0> during command cycle.


LBECR<31:20>
LBECR<31:20>; RSVD

Reserved. (R0) Read as zero.


LBECR<19:18>
LBECR<19:18>; DCYCLE

Data Cycle. (RO) Value indicates which data cycle had the data error.

LBECR<19:18>	Data Cycle in Error
00	1
01	2
10	3
11	4


LBECR<17>
LBECR<17>; DIRTY

Dirty. (RO) Set when DIRTY is asserted for the current command.


LBECR<16>
LBECR<16>; SHARED

Shared. (RO) Set when SHARED is asserted for the current command.


LBECR<15>
LBECR<15>; CNF

Confirmation. (RO) Set when CNF is asserted for the current command.


LBECR<14:11>
LBECR<14:11>; RSVD

Reserved. (R0) Read as zero.


LBECR<10:7>
LBECR<10:7>; CID

Commander ID. (R0) Reflects the contents of REQ<3:0> during a command cycle.


LBECR<6>
LBECR<6>; P

Parity. (RO) Contents of D<38> during command cycle.


LBECR<5:3>
LBECR<5:3>; CMD

Command. (RO) Contents of D<37:35> during command cycle. CMD is decoded as follows:

Command	Function	DAS Value
000	Read	00
001	Write	08
010	Reserved
011	Write Victim	18
100	Read CSR	20
101	Write CSR	28
110	Reserved
111	Private	38
DAS Value is the hex value commonly found in the low byte of this register when less than 8 Gbytes of memory are present in the system.


LBECR<2:0>
LBECR<2:0>; CA

Command/Address. (RO) Contents of D<34:32> during command cycle.


MCR<31:4>
MCR<31:4>; RSVD

Reserved. (R0) Read as zero.


MCR<3:2>
MCR<3:2>; STRG

String.	 (RO, X) Supplies information about the number of strings installed on a module. This field, in conjunction with DTYP, indicates module capacity. It is loaded at system initialization.

MCR<3:2>	No. of Strings
00	1
01	2
10	4
11	8


MCR<1>
MCR<1>; RSVD

Reserved. (R0) Reads as zero.


MCR<0>
MCR<0>; DTYP

Device Type. (RO, X) Supplies information about the size of DRAM technology used for the memory module. This bit, along with STRG, indicates module capacity. It is loaded at system initialization.

MCR<0>	DRAM Type
0	4 Mbit
1	16 Mbit


AMR<31:17>
AMR<31:17>; MADR

Module Address. (R/W, 0) The contents of MADR is compared with the LSB address contained on D<34:20> for a match. (MADR bit <17> correlates to LSB address line D<20>, and so on.)


AMR<16:11>
AMR<16:11>; RSVD

Reserved. (R0) Read as zero.


AMR<10:9>
AMR<10:9>; NBANKS

Number of Banks. (R/W, 0) Specifies the number of banks (1, 2, 4, or 8) contained on individual memory modules.

AMR<10:9>	No. of Banks
00	1
01	2
10	Reserved
11	Reserved


AMR<8:5>
AMR<8:5>; AW

Address Width. (R/W, 0) Specifies the number of bits in the LSB address field <34:20> that are significant. Only those bits are compared with the same number of corrersponding bits in the AMR<MADR> (bits <31:17>). The remaining bits are ignored. The theoretical range of significant bits selected by different values of the AMR<AW> is given below. In the initialized state, no bits of D<34:20> are matched to bits AMR<31:17> (AW = 0000). When AW contains a value of 0001, only the MSBs are compared (AMR<31> is compared to LSB<34>). Access is allowed if a match occurs. If a value of F (hex) is written in AW, all bits are significant, and the LSB <34:20> must match AMR<31:17>.

	Significant Bits Compared
AMR<8:5>	LSB Data	AMR<MADR>
1111	<34:20>	<31:17>
1110	<34:21>	<31:18>
1101	<34:22>	<31:19>
1100	<34:23>	<31:20>
1011	<34:24>	<31:21>
1010	<34:25>	<31:22>
1001	<34:26>	<31:23>
1000	<34:27>	<31:24>
0111	<34:28>	<31:25>
0110	<34:29>	<31:26>
0101	<34:30>	<31:27>
0100	<34:31>	<31:28>
0011	<34:32>	<31:29>
0010	<34:33>	<31:30>
0001	<34>	<31>
0000	No compare


AMR<4:3>
AMR<4:3>; IA

Interleave Address. (R/W, 0) Determines module selection based upon level of interleave with other memory modules.


AMR<2:1>
AMR<2:1>; INTL

Interleave. (R/W, 0) Determines the level of interleave of this module with other modules for a given address space.

AMR<2:1>	Interleave Level
00	1-way interleave. Module is not interleaved with any other module.
01	2-way interleave. Module is interleaved with one other module.
10	4-way interleave. Module is interleaved with three other modules.
11	Reserved.


AMR<0>
AMR<0>; E

Enable. (R/W, 0) Enables the module to respond to LSB memory space transactions.


MSTR<31:0>
MSTR<31:0>; STFAS

Self-Test Failing Address Segment. (RO, 0) A bit in the MSTR registers is set when the associated memory segment fails self-test (is defective) in a noninterleaved memory configuration. Each module executes self-test as if it were the only memory module in the system.

The following table gives a listing of memory address segments associated with each bit in the MSTR registers. Address segments are given for 4-Mbit and 16-Mbit DRAM arrays.

Memory Error Address Segments

	MSTR0	MSTR1
Failing Bit	4-Mbit	16-Mbit	4-Mbit	16-Mbit
0	0000 0000 to 007F FFFF	0000 0000 to 01FF FFFF	1000 0000 to 107F FFFF	4000 0000 to 41FF FFFF
1	0080 0000 to 00FF FFFF	0200 0000 to 03FF FFFF	1080 0000 to 10FF FFFF	4200 0000 to 43FF FFFF
2	0100 0000 to 017F FFFF	0400 0000 to 05FF FFFF	1100 0000 to 117F FFFF	4400 0000 to 45FF FFFF
3	0180 0000 to 01FF FFFF	0600 0000 to 07FF FFFF	1800 0000 to 11FF FFFF	4600 0000 to 47FF FFFF
4	0200 0000 to 027F FFFF	0800 0000 to 09FF FFFF	1200 0000 to 127F FFFF	4800 0000 to 49FF FFFF
5	0280 0000 to 02FF FFFF	0A00 0000 to 0BFF FFFF	1280 0000 to 12FF FFFF	4A00 0000 to 4BFF FFFF
6	0300 0000 to 037FFFFF	0C00 0000 to 0DFF FFFF	1300 0000 to 137F FFFF	4C00 0000 to 4DFF FFFF
7	0380 0000 to 08FF FFFF	0E00 0000 to 0FFF FFFF	1380 0000 to 13FF FFFF	4E00 0000 to 4FFF FFFF
8	0400 0000 to 047F FFFF	1000 0000 to 13FF FFFF	1400 0000 to 147F FFFF	5000 0000 to 51FF FFFF
9	0480 0000 to 04FF FFFF	1200 0000 to 15FF FFFF	1480 0000 to 14FF FFFF	5200 0000 to 53FF FFFF
10	0500 0000 to 057F FFFF	1400 0000 to 15FF FFFF	1500 0000 to 157F FFFF	5400 0000 to 55FF FFFF
11	0580 0000 to 05FF FFFF	1600 0000 to 17FF FFFF	1580 0000 to 15FF FFFF	5600 0000 to 57FF FFFF
12	0600 0000 to 067F FFFF	1800 0000 to 19FF FFFF	1600 0000 to 167F FFFF	5880 0000 to 59FF FFFF
13	0680 0000 to 06FF FFFF	1A00 0000 to 1BFF FFFF	1680 0000 to 16FF FFFF	5A00 0000 to 5BFF FFFF
14	0700 0000 to 077F FFFF	1C00 0000 to 1DFF FFFF	1700 0000 to 177F FFFF	5C00 0000 to 5FFF FFFF
15	0780 0000 to 07FF FFFF	1E00 0000 to 1FFF FFFF	1780 0000 to 17FF FFFF	5E00 0000 to 5FFF FFFF
16	0800 0000 to 087F FFFF	2000 0000 to 21FF FFFF	1800 0000 to 187F FFFF	6000 0000 to 61FF FFFF
17	0880 0000 to 08FF FFFF	2200 0000 to 23FF FFFF	1880 0000 to 18FF FFFF	6200 0000 to 63FF FFFF
18	0900 0000 to 097F FFFF	2400 0000 to 25FF FFFF	1900 0000 to 197F FFFF	6400 0000 to 65FF FFFF
19	0980 0000 to 09FF FFFF	2600 0000 to 27FF FFFF	1980 0000 to 19FF FFFF	6600 0000 to 67FF FFFF
20	0A00 0000 to 0A7F FFFF	2800 0000 to 29FF FFFF	1A00 0000 to 1A7F FFFF	6800 0000 to 69FF FFFF
21	0A80 0000 to 0AFF FFFF	2A00 0000 to 2BFF FFFF	1A80 0000 to 1AFF FFFF	6A00 0000 to 6BFF FFFF
22	0B00 0000 to 0B7F FFFF	2C00 0000 to 2DFF FFFF	1B00 0000 to 1B7F FFFF	6C00 0000 to 6DFF FFFF
23	0B80 0000 to 0BFF FFFF	2E00 0000 to 2FFF FFFF	1B80 0000 to 1BFF FFFF	6E00 0000 to 6FFF FFFF
24	0C00 0000 to 0C7F FFFF	3000 0000 to 31FF FFFF	1C00 0000 to 1C7F FFFF	7000 0000 to 71FF FFFF
25	0C80 0000 to 0CFF FFFF	3200 0000 to 33FF FFFF	1C80 0000 to 1CFF FFFF	7200 0000 to 73FF FFFF
26	0D00 0000 to 0D7F FFFF	3400 0000 to 35FF FFFF	1D00 0000 to 1D7F FFFF	7400 0000 to 75FF FFFF
27	0D80 0000 to 0DFF FFFF	3600 0000 to 37FF FFFF	1D80 0000 to 1DFF FFFF	7600 0000 to 77FF FFFF
28	0E00 0000 to 0E7F FFFF	3800 0000 to 39FF FFFF	1E00 0000 to 1E7F FFFF	7800 0000 to 79FF FFFF
29	0E80 0000 to 0EFF FFFF	3A00 0000 to 3BFF FFFF	1E80 0000 to 1EFF FFFF	7A80 0000 to 7BFF FFFF
30	0F00 0000 to 0F7F FFFF	3C00 0000 to 3DFF FFFF	1F00 to 1F7F FFFF	7C00 0000 to 7DFF FFFF
31	0F80 0000 to 0FFF FFFF	3E00 0000 to 3FFF FFFF	1F80 0000 to 1FFF FFFF	7E00 0000 to 7FFF FFFF


FADR<31:0>
FADR<31:0>; FADR

Failing Address. (RO) Contains the LSB address driven on D<31:0> during a command/address cycle. The failing address bits are saved when the memory interface controller detects either a correctable or uncorrectable ECC error within the 64-bit ECC logic during LSB memory read transactions. If this field is already locked with the failing address of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the failing address of the uncorrectable error.


MERA<31:12>
MERA<31:12>; RSVD

Reserved. R0 Read as zero.


MERA<11>
MERA<11>; UCERB

Uncontrollable Error on MIC-B. (W1C, 0) Set when MIC-B detects an uncorrectable 64-bit ECC error. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks UCERA (MERA<10>) from being set. If MIC-A and MIC-B were to detect simultaneous 64-bit ECC errors, then either bits <11> and <10>, or bits <5> and <4> would be set at the same time. The failing string and the address in the FADR register would pertain to failures detected in both MIC-A and MIC-B. If either MIC-A or MIC-B detects an error, then the setting of the appropriate bit and the blocking of the other bit in the combination allows isolation of independent failures on MIC-A or MIC-B to the failing string and LSB address.


MERA<10>
MERA<10>; UCERA

Uncorrectable Error on MIC-A. (W1C, 0) Set when MIC-A detects an uncorrectable 64-bit ECC error. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks UCERB (MERA<11>) from being set. See description of UCERB above.


MERA<9>
MERA<9>; BNKER

Bank Conflict Error. (W1C, 0) When set, indicates that an LSB request was made to a currently active memory bank. When this bit is set, LSB ERR is asserted.


MERA<8:6>
MERA<8:6>; FSTR

Failing String. (RO, 0) Indicates which of the eight strings were being accessed during an LSB memory read when an uncorrectable or correctable ECC error was detected by memory's 64-bit ECC logic. This field, along with the two syndrome registers, isolates single-bit errors to a failing DRAM component. FSTR is locked when a correctable or uncorrectable error bit is set in either MIC-A or MIC-B. If this field is already locked with the failing address of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the failing address of the uncorrectable error.


MERA<5>
MERA<5>; CERB

Correctable ECC Error on MIC-B. (W1C, 0) Set when a correctable ECC error is detected on MIC-B. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks CERA MERA<4>) from being set. See description of UCERB (MERA<11>) above.


MERA<4>
MERA<4>; CERA

Correctable ECC Error on MIC-A. (W1C, 0) Set when a correctable ECC error is detected on MIC-A. The high state of this bit locks bits <8:6> of this register, the contents of the FADR register and the contents of the MSYNDA register. It also blocks CERB (MERA<5>) from being set. See description of UCERB (MERA<11>) above.


MERA<3>
MERA<3>; APER

Address Parity Error. (W1C, 0) Set when a row or column address parity error is detected. If APER is set, UCERA (MERA<1>) is also set.


MERA<2>
MERA<2>; MULE

Multiple Errors. (W1C, 0) Set when a second correctable or uncorrectable error is detected after either UCER (MERA<1>) or CER (MERA<0>) has been set. This bit sets only if an error is detected on a subsequent read transaction. It does not set if multiple errors are detected within the same transaction.


MERA<1>
MERA<1>; UCER

Uncorrectable Read Error. (W1C, 0) Set when an uncorrectable read data error is detected within memory's 64-bit ECC logic protecting D<63:0>. Memory supplies the data with uncorrectable errors forced on LSB check bits ECC<13:0>. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome.


MERA<0>
MERA<0>; CER

Correctable Read Error. (W1C, 0) Set when a correctable read data error is detected within memory's 64-bit ECC logic protecting D<63:0>. Memory corrects the data in error and supplies good data to LSB. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome.


MSYNDA<31:8>
MSYNDA<31:8>; RSVD

Reserved. (R0) Read as zero.


MSYNDA<7:0>
MSYNDA<7:0>; SYNDA

Syndrome A. (RO, 0) Contains the error syndrome protecting D<63:0>.


MDRA<31>
MDRA<31>; DRFSH

Disable Refresh. (R/W, 0) If set, "on-board" refresh of the module is disabled and diagnostic burst refresh (see BRFSH, MDRA<30>) is enabled. When this bit is set concurrently with BRFSH, a burst refresh cycle is executed.


MDRA<30>
MDRA<30>; BRFSH

Burst Refresh. (WO, 0) When BRFSH is set, and DRFSH (MDRA<31>) is also set, a single row address within the accessed DRAMs is refreshed as per CAS before RAS refresh operation. When this bit is set concurrently with DRFSH, a burst refresh cycle is executed.


MDRA<29:28>
MDRA<29:28>; RFR

Refresh Rate. (R/W, 0) Determines the refresh rate of the module.

MDRA<29:28>	Refresh Rate
00	1 x default
01	2 x default
10	4 x default
11	Reserved


MDRA<27>
MDRA<27>; DCRD

Disable CRD Assertion. (R/W, 0) If set, LSB_CRD does not assert when memory detects a read CRD error in the 64-bit ECC logic.


MDRA<26:10>
MDRA<26:10>; RSVD

Reserved. (R0) Read as zero.


MDRA<9>
MDRA<9>; FCPE

Force Column Parity Error. (R/W, 0) If set, incorrect column address parity is written into the addressed location in memory.


MDRA<8>
MDRA<8>; FRPE

Force Row Parity Error. (R/W, 0) If set, incorrect row address parity is written into the addressed location in memory.


MDRA<7>
MDRA<7>; IGSB

Ignore Single-Bit Self-Test Failures. (R/W, 0) If set, self-test logic does not report errors in the MSTR0/ MSTR1 registers when a single bit is detected to be in error for each octaword read. Only errors of two or more bits are reported.


MDRA<6>
MDRA<6>; MODE

Self-Test Mode. (R/W, 0) If set, self-test executes a defined "ones/zeros" data pattern when running under diagnostic control. Two passes are executed. In the first pass, all data bits in an odd hexword address are written with ones, while those in an even hexword are written with zeros. In the second pass, hexword addresses are written with inverse data patterns.


MDRA<5>
MDRA<5>; STPM

Self-Test Pause Mode. (R/W, 0) If set, self-test completes one of its three passes. To execute the next pass, EXST (MDRA<4>) must be set. This feature is necessary for memory manufacturing tests. STPM must be set at the start of each pass. Otherwise, self-test begins at pass 1.


MDRA<4>
MDRA<4>; EXST

Execute Self-Test. (R/W, 1) If EXST is set, memory self-test is invoked. The self-test logic examines this bit to determine if self-test should be executed. This bit is set upon system power-up or LSB reset. It is cleared when self-test completes execution. It is also cleared in diagnostic mode when STPM is set for each pass that the self-test state machine completes.


MDRA<3>
MDRA<3>; BPAS

Bypass. (R/W, 0) If set, both the read data path and write data path ECC logic is bypassed to aid in memory manufacturing tests. LSB ECC<7:0> is directly mapped to the eight ECC check bits protecting D<63:0> in the MIC-A.


MDRA<2>
MDRA<2>; DWDC

Disable Write Data Correction. (R/W, 0) If set, ECC correction of LSB memory write data is disabled. Uncorrected data is written to memory with a no error ECC check bit code. The setting of this bit affects the correction of D<63:0>. Thirty-two bit ECC errors, if present, are logged.


MDRA<1>
MDRA<1>; DRDC

Disable Read Data Correction. (R/W, 0) If set, ECC correction of memory read data is disabled. The setting of this bit affects the correction of D<63:0>.


MDRA<0>
MDRA<0>; FCBS

Force Check Bit Substitution. (R/W, 0) If set, the contents of the MCBSB register is gated into the 64-bit write ECC logic in place of the DRAM check bits. The setting of this bit affects D<63:0>.


MCBSA<31:8>
MCBSA<31:8>; RSVD

Reserved. (R0) Read as zero.


MCBSA<7:0>
MCBSA<7:0>; SCB_A

Substituted Check Bits A. (R/W, 0) SCB_A is used in place of the DRAM check bits protecting D<63:0> when DRDC (MDRA <1>) is set.


MERB<31:4>
MERB<31:4>; RSVD

Reserved. (R0) Read as zero.


MERB<3>
MERB<3>; APER

Address Parity Error. (W1C, 0) Set when a row or column address parity error is detected. If APER is set, UCER (MERB<1>) is also set.


MERB<2>
MERB<2>; MULE

Multiple Errors. (W1C, 0) Set when a second correctable or uncorrectable error is detected after either UCER (MERB<1>) or CER (MERB<0>) has been set. This bit sets only if an error is detected on a subsequent read transaction. It does not set if multiple errors are detected within the same transaction.


MERB<1>
MERB<1>; UCER

Uncorrectable Read Error. (W1C, 0) Set when an uncorrectable read data error is detected within memory's 64-bit ECC logic protecting D<127:64>. Memory supplies the data with uncorrectable errors forced on LSB check bits ECC<27:14>. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome.


MERB<0>
MERB<0>; CER

Correctable Read Error. (W1C, 0) Set when a correctable read data error is detected within memory's 64-bit ECC logic protecting D<127:64>. Memory corrects the data in error and supplies good data to the LSB. When this bit sets, the Memory Error Syndrome Register B is locked with the failing syndrome.


MSYNDB<31:8>
MSYNDB<31:8>; RSVD

Reserved. (R0) Read as zero.


MSYNDB<7:0>
MSYNDB<7:0>; SYNDB

Syndrome B. (RO, 0) Contains the error syndrome protecting D<127:64>.


MDRB<31:8>
MDRB<31:8>; RSVD

Reserved. (R0) Read as zero.


MDRB<7>
MDRB<7>; IGSB

Ignore Single-Bit Self-Test Failures. (R/W, 0) If set, self-test logic does not report errors in the MSTR0/ MSTR1 registers when a single bit is detected to be in error for each octaword read. Only errors of two or more bits are reported.


MDRB<6>
MDRB<6>; MODE

Self-Test Mode. (R/W, 0) If set, self-test executes a defined "ones/zeros" data pattern when running under diagnostic control. Two passes are executed. In the first pass, all data bits in an odd hexword address are written with ones, while those in an even hexword are written with zeros. In the second pass, hexword addresses are written with inverse data patterns.


MDRB<5>
MDRB<5>; STPM

Self-Test Pause Mode. (R/W, 0) If set, self-test completes one of its three passes. To execute the next pass, EXST (MDRB<4>) must be set. This feature is necessary for memory manufacturing tests. STPM must be set at the start of each pass. Otherwise, self-test begins at pass 1.


MDRB<4>
MDRB<4>; EXST

Execute Self-Test. (R/W, 0) If EXST is set, memory self-test is invoked. The self-test logic examines this bit to determine if self-test should be executed. This bit is set upon system power-up or LSB reset. It is cleared when self-test completes execution. It is also cleared in diagnostic mode when STPM is set for each pass that self-test completes.


MDRB<3>
MDRB<3>; BPAS

Bypass. (R/W, 0) If set, both the read data path and write data path ECC logic is bypassed to aid in memory manufacturing tests. LSB ECC<15:8> is directly mapped to the eight ECC check bits protecting D<127:64> in the MIC-B chip.


MDRB<2>
MDRB<2>; DWDC

Disable Write Data Correction. (R/W, 0) If set, ECC correction of LSB memory write data is disabled. Uncorrected data is written to memory with a no error ECC check bit code. The setting of this bit affects the correction of D<127:64>. Thirty-two bit ECC errors, if present, are logged.


MDRB<1>
MDRB<1>; DRDC

Disable Read Data Correction. (R/W, 0) If set, ECC correction of memory read data is disabled. The setting of this bit affects the correction of D<127:64>.


MDRB<0>
MDRB<0>; FCBS

Force Check Bit Substitution. (R/W, 0) If set, the contents of the MCBSB register is gated into the 64-bit write ECC logic in place of the DRAM check bits. The setting of this bit affects D<127:64>.


MCBSB<31:8>
MCBSB<31:8>; RSVD

Reserved. (R/W, 0) Read as zero.


MCBSB<7:0>
MCBSB<7:0>; SCB_B

Substituted Check Bits B. (R/W, 0) SCB_B is used in place of the DRAM check bits protecting D<127:64> when DRDC (MDRB <1>) is set.


Glossary

-A-	-I-
AC input box	IOP module (I/O port module)
Address space	ISE (integrated storage element)
Alpha primary boot program	-K-
Asymmetric multiprocessing	KA7AA CPU module (VAX 7000)
-B-	KDM70
Bandwidth	KFMSA
Battery backup	KN7AA CPU module (DEC 7000)
Boot device	KZMSA
Boot primitives	-L-
Boot processor	LDC (local disk converter)
Bootblock	LEVI interface
-C-	LFU (Loadable Firmware Update)
CCL module	LSB bus
Centerplane	-M-
CIXCD	Mailbox
Console CD-ROM	Memory
Compact disk server	Memory interleaving
Console language	More protocol
Console mode	-N-
Console program	Node, LSB
Control panel	-P-
CPU module	Physical address space
-D-	Plug-in units (PIUs)
DEMFA	Power
DEMNA	-R-
Device	Reset sequence
DSSI	-S-
DSSI PIU	SCSI
DWLMA adapter	SCSI PIU
DWMBB	SROM (serial ROM) code
-E-	Symmetric multiprocessing
Environment variables	-T-
Expander cabinet	TF85 tape drive
-F-	TLZ06 tape drive
FDDI	Transactions
Filler module	-V-
Flash ROM	VAXBI PIU
Flash ROM recovery code (FRRC)	Virtual address space
-G-	VMB
Gbus	-X-
-H-	XMI clock
Hardware restart parameter block	XMI PIU
Hose	XMI-to-LSB interface


AC input box

Receives three-phase AC power and outputs that to the power regulators. The system circuit breaker and a Dranetz port are on the AC input box. See also Power.


Address space

Physical address space -- The 1 terabyte of physical address space that the LSB bus can access using a 40-bit memory address space.

Virtual address space -- Memory space available to a user program. The operating system dynamically maps a given virtual address to a physical adddress.


Alpha primary boot program (DEC 7000 system)

The Alpha primary boot program (APB.EXE) that boots OpenVMS Alpha AXP. APB is the primary bootstrap program and is stored on the boot device.


Asymmetric multiprocessing

A multiprocessing configuration in which the processors are not equal in their ability to execute operating system code. In general, a single processor is designated as the primary, or master, processor; other processors are the slaves. The slave processors are limited to performing certain tasks, whereas the master processor can perform all system tasks. Contrast with Symmetric multiprocessing.


Bandwidth

The data transfer rate measured in information units transferred per unit of time (for example, Mbytes per second).


Battery backup

Provides power to the entire system cabinet (or to an expander cabinet) in the event of a power failure. A system can maintain power for approximately 11 minutes. Each power regulator requires a battery pack of four batteries.


Boot device

A storage device that holds the software that carries out the system bootstrap process.


Boot primitives

Small programs stored in ROM on each processor with the console program. Boot primitives read the bootblock from boot devices. There is a boot primitive for each type of boot device.


Boot processor

The CPU module that boots the operating system and communicates with the console; also known as the primary processor.


Bootblock

Block zero on the system disk; it contains the block number where the Alpha primary boot (APB), OSF/1 boot, or virtual memory boot (VMB) program is located on the system disk and contains a program that, with the boot primitive, reads APB or VMB from the system load device into memory.


CD-ROM, DEC 7000, VAX 7000 Console CD-ROM

Contains the LFU utility used in upgrading firmware and copies of the firmware for all modules in the system, including the console and diagnostic firmware.


Centerplane

The LSB backplane, located in the center of the card cage, which physically shortens the bus thus increasing bandwidth.


CCL module

Module at the top right of the system cabinet that provides the control panel interface and power sequencing; includes air pressure and temperature sensors.


CIXCD

XMI CI port interface; connects a system to a Star Coupler.


Compact disk server

In-cabinet CD server (for DEC 7000 systems) or Ethernet-based CD server (for VAX 7000 systems); provides access to CD-ROMs for software installation, diagnostics, and on-line documentation.


Console language

Used by the system operator at the console terminal to communicate with the primary processor; provides the interface to diagnostics. The console language uses options, environment variables, and arguments.

Options modify the action of the command in some way, or give details of how the command is to operate; they appear in the form -xxx and are preceded by a space.

Environment variables determine the environment; some are set in manufacturing and set up a default environment. Most environment variables are defined with the set command. See also Environment variables.


Console mode

A mode of operation where the processor is not running the operating system but allows a console terminal operator to communicate with nodes on the LSB bus and I/O bus adapters and devices.


Console program

The code that the boot processor executes during console mode. Each processor has a copy of this code in flash ROMs. After a boot processor has been determined, that processor begins console initialization. The console code is then loaded into memory.


Control panel

Consists of a keyswitch to control the state of the system and three status LEDs.


CPU module

The KN7AA processor is the CPU module used in DEC 7000 systems. The KA7AA processor is the CPU module used in VAX 7000 systems.


Device

From the console perspective, "device" can be used to refer to a physical device, a block of memory, or a set of registers. The console commands operate on byte streams, so any of these can be expressed as a byte stream.

Each physical device in a system has a unique mnemonic assigned by the console program, which is displayed as part of the show configuration, show device, and show network commands.


DEMFA

XMI adapter to the FDDI (Fiber Distributed Data Interface).


DEMNA

XMI adapter; Ethernet port interface.


DSSI

Digital Storage Systems Interconnect. A Digital Storage Architecture interconnect used by the KFMSA adapter and RF and TF series integrated storage elements to transfer data and to communicate with each other.


DSSI PIU

Houses DSSI based disks inside the system and expander cabinets (BA654).


DWLMA adapter

An XMI adapter that is the interface between the LSB bus and the XMI bus; always node 8 of the XMI. The XMI plug-in unit includes the T2028-AA module and necessary cables and the XMI clock card. See also XMI PIU and XMI clock.


DWMBB

The XMI-to-VAXBI adapter; a 2-module adapter that allows data transfer from the XMI to the VAXBI.


Environment variables

UNIX-like options used with console commands. An environment variable consists of an identifier (ID) and a byte stream value maintained by the console. See also Console language.


Expander cabinet

A cabinet to hold plug-in units that can be installed on either side of the system cabinet.


FDDI

Fiber Distributed Data Interface. A high-performance fiber optic network that can be accessed by the XMI DEMFA adapter.


Filler module

Required to fill unused LSB slots when fewer than six CPU, memory, or I/O modules are installed.


Flash ROM
Flash ROM or FEPROM

Flash-erasable programmable read-only memory, which can be bulk erased and reprogrammed. The KN7AA and KA7AA processors use flash ROMs to hold the console and diagnostic firmware. In addition, one flash ROM holds initialization code that bootstraps the main console/diagnostic firmware. It also holds flash ROM recovery code. See also SROM code and Flash ROM recovery code.


Flash ROM recovery code (FRRC)

The minimum amount of code necessary for remote flash ROM recovery; used if the console/diagnostic ROMs have become corrupted.


Gbus

The path between the processor and the console/diagnostic firmware and to two UART chips. The Gbus has two lines, one to the console terminal and one to the power supply.


Hardware restart parameter block (HWRPB)

A page-aligned data structure shared between the console and system software; a critical resource during bootstraps, recovery from power failures, and other restart situations.


Hose

The interconnect between the IOP module on the LSB bus and the interface module on another bus, such as the DWLMA module on the XMI bus.


IOP module (I/O port module)

The LSB module that provides the interface from the LSB bus to I/O buses. The IOP module has four ports to support up to four I/O channels. Each channel is known as a "hose." The IOP module must be node 8 of the LSB. Node 8 is dedicated as both the highest and lowest arbitration level; the IOP usually arbitrates at the highest priority. Besides providing for I/O, the IOP module also generates the clock signals for the LSB bus.


KA7AA CPU module (VAX 7000)

The LSB CPU module that uses the NVAX+ chip, a CMOS-4 implementation with a macropipelined design. An 8-Kbyte cache is part of the CPU chip and a 4-Mbyte cache is implemented in RAMs. The KA7AA processor supports writeback caching.


KN7AA CPU module (DEC 7000)

The LSB CPU module that uses the DECchip 21064 using CMOS-4 implementation with a super scalar super-pipelined design. An 8-Kbyte cache is part of the CPU chip and a 4-Mbyte cache is implemented in RAMs. The KN7AA processor supports writeback caching.


KDM70

XMI adapter for RA disks and TA tapes used to enable connection to nodes on a DSSI bus.


KFMSA

XMI adapter for RF disks and TF tapes used in VAX 7000 systems. It enables connection to nodes on a DSSI bus. Each KFMSA adapter supports two DSSI buses.


KZMSA

XMI adapter to the SCSI (Small Computer System Interface) used in DEC 7000 systems. It enables connection to nodes on a SCSI bus.


ISE (integrated storage element)

All DSSI storage devices, such as RF disks and TF tapes, are ISEs.


LDC (local disk converter)

Converts 48 VDC to +5V and +12V needed by the storage arrays in the DSSI PIU (BA654).


LEVI interface

The logical and physical interface of the CPU module to the LSB bus. Two different chips are used. The LEVI interface also determines if data is in the backup cache or if it must do a transaction to memory.


LFU (Loadable Firmware Update) Utility

Used to update firmware on LSB and I/O device modules.


LSB bus

The 128-bit system bus. The LSB bus is implemented in a 9-slot card cage with its "backplane" in the center of the cage, so that modules are installed from the front and the back. Module placement is indicated by a node number 0 through 8. Node 8 is reserved for the LSB I/O port (IOP) module.


Mailbox

A software-created data structure in memory used to read and write to I/O device registers.


Memory

Systems use the MS7AA memory modules, available with 64, 128, 256, or 512 Mbytes of memory. Total memory supported is determined by the operating system. Memory transfers are 64 bytes in length.


Memory interleaving

Method to optimize memory access time; the console program automatically interleaves the memories in the system unless a command is used to set a specific interleave or no interleave (which would result in serial access to each memory module). Interleaving causes a number of memories to operate in parallel.


More protocol

A protocol used on the XMI bus that allows XMI nodes to make noninterlocked memory reads and writes. Using the More protocol increases I/O performance.


Node, LSB

LSB nodes are numbered from 0 to 8 and correspond to specific slots in the LSB card cage.


Physical address space

The 1 terabyte of physical address space that the LSB bus can access using a 40-bit memory address space.


Power

Three-phase AC power is supplied to the AC input box which is then fed to one to three power regulators that provide 48 VDC. Power enters the LSB card cage through a 48V filter and then is distributed to the bus bars on the centerplane. Each module on the LSB bus has a power converter, which converts the 48V to the voltage required by the module. Power sequencing logic is provided by the CCL module.

Plug-in units are powered by the system, but in addition bus PIUs have their own power regulators. Batteries supply power to the system cabinet for approximately 11 minutes. Expander cabinets have their own supply.


Plug-in units (PIUs)

Self-contained assemblies that are easily installed in the system cabinet or expander cabinet. There are PIUs for the XMI bus, the VAXBI bus, disks, and batteries.


Reset sequence

A process leading to the execution of a copy of the console firmware from memory. Purpose is to test the machine, establish the console environment, indicate that the console is executing, and dispatch to entry handling procedures. Power-up testing executes from the backup cache, a boot processor is determined, which creates the HWRPB and copies the console image from ROM/cache to memory. Registers are set to their default values, and internal console data structures are initialized. After power-up the secondary processors also use the console code from memory.


SCSI (Small Computer System Interface)

An industry-standard interface for connecting disks and other peripheral devices to computer systems. Requires the KZMSA XMI adapter.


SCSI PIU

Houses SCSI based disks and tapes inside system and expander cabinets (BA655).


SROM (serial ROM) code

The initialization code that bootstraps the main console/diagnostic firmware.


Symmetric multiprocessing

A multiprocessing system configuration in which all processors have equal access to operating system code residing in shared memory and can perform all, or almost all, system tasks.


Transactions

LSB transactions consist of a command and four data cycles, which follow some fixed time after an arbitration cycle. All LSB modules monitor the request lines to see which of them wins the bus. Up to three transactions can be in progress at one time. Because arbitration occurs on a dedicated set of control lines, it can overlap with data transfer.


TF85 tape drive

A 5.25-inch tape drive on the DSSI bus, which is supported by the KFMSA adapter; used in VAX 7000 systems.


TLZ06 tape drive

A 5.25-inch tape drive on the SCSI bus, which is supported by the KZMSA adapter; used in DEC 7000 systems.


VAXBI PIU

A plug-in unit consisting of a VAXBI card cage and two power regulators which occupy two quadrants. The VAXBI PIU must be installed next to an XMI PIU. Installation of a VAXBI PIU means that battery backup cannot be supported. The 12-slot VAXBI includes a DWMBB/B module installed in slot 1, which connects to the DWMBB/A in the XMI.


Virtual address space

Memory space available to a user program. The operating system dynamically maps a given virtual address to a physical adddress.


VMB

The virtual memory boot program (VMB.EXE) that boots the OpenVMS VAX operating system. VMB is the primary bootstrap program and is stored on the boot device.


XMI clock

Implemented on the T2030-YA module which must be node 7 of the XMI.


XMI PIU

A plug-in unit consisting of an XMI card cage and two power regulators which occupy two quadrants. Each XMI requires a DWLMA module in slot 8 and a clock module at slot 7. The first I/O option must be installed in slot 1 or 14 to terminate the XMI bus. Also known as the XMI I/O channel PIU.


XMI-to-LSB interface

On the XMI the interface is the DWLMA module which must be node 8 of the XMI. On the LSB bus the interface is the IOP module, which must be node 8 of the LSB. The connection between the two modules is known as a "hose." See also IOP module.