Copyright: Copyright © 1996 Digital Equipment Corp


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Digital Alpha XL 300, 366, and 433 Service Guide Team

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Please reference order number AK-QXMHB-CA in your correspondence about this guide.


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Alpha XL 300 and 366 Service Guide Table of Contents


Alpha XL 300 and 366 Service Guide Draft Notices
Digital Alpha XL Service Guide - Draft Notes

This draft version of the Service Information is based on the following:

Please send your comments to WREATH::DONALD.


Copyright and Trademarks

The information used in this document is subject to change without notice and should not be construed as a commitment from Digital Equipment Corporation.  Digital Equipment Corporation assumes no responsibility for any errors that appear in this document.

Possession, use, duplication, or dissemination of the software described in this documentation is authorized only pursuant to a valid written license from Digital or the third-party owner of the software copyright.

Copyright © Digital Equipment Corporation 1996.  All rights reserved.

The following are trademarks of Digital Equipment Corporation: AlphaGeneration, AlphaServer, AlphaStation, DEC, DECstation, Digital, Digital Semiconductor, OpenVMS, StorageWorks, and the DIGITAL logo.

Matrox is a registered trademark of Matrox Electronic Systems Ltd.  MGA Millennium is a trademark of Matrox Graphics Inc.  SuperI/O is a trademark of National Semiconductor Corporation.  UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd.  Windows NT is a registered trademark of Microsoft Corporation.


AlphaGeneration
Welcome to the fast world of AlphaGeneration systems.  Performance has arrived on your desktop.  Fasten your seatbelt and hang on for the ride of your life!


Copying and Printing Popup Displays

Normally, information contained in popup displays cannot be copied or printed.  The Digital Alpha XL 300, 366, and 433 Service Guide makes provisions to allow you to copy and print popups.

Popups that you can copy or print have a hotspotted title line.  Simply click on the title to make the popup a main window topic.  Then you can copy or print the text using the File and Edit menus on the menu bar.  When you have finished, click on the Back button to return to the popup parent topic.


Who is the Audience?
Audience

The primary audience of the Alpha XL 300, 366, and 433 Service Guide is Digital's Multivendor Customer Services (MCS) organization.  Secondary audiences include customers who maintain their own systems as well as value added resellers (VARs).


Disoriented?
Getting Disoriented?

Are you losing track of where you are in the service information?  A couple of buttons will help keep you oriented.  The  BACK button takes you backward a topic at a time along the path you have traveled already .  For example, if you click on the topic title of a popup, the popup becomes the main topic to facilitate printing and copying the information.  To return to the previous topic, click on the BACK button.

Another helpful button is the CONTENTS button.  Just click on this button to go back to the main menu screen.


For More Information

	Digital Alpha XL User's Guide	EK-ALXLA-UG
	Digital Alpha XL CPU Guide	EK-ALXLA-CG
	Alpha 21164-AA Microprocessor Hardware Reference Manual	EC-QAEQC-TE
	Digital Semiconductor 21164 (366 MHz Through 433 MHz) Alpha Microprocessor Hardware Reference Manual	EC-QP99A-TE
	PCI Local Bus Specification, Revision 2.0	PCI Special Interest Group, order number 281446-001
	Alpha XL 300, 366, and 433 Service Guide  Can be loaded from: http://www.workstation.digital.com	AK-QXMHB-CA


Rev B Changes
Revision B Changes

Changes made to revision B of this document include:

  Added 433-MHz CPU module.

  Updated configuration package information.

  Added CPU speed switch settings.

  Additional troubleshooting information.

  Minor bug fixes in the service guide's code.

  Added ISA device address information.

  Added some information to help with SIMM width identification.

  Updated firmware pointers and procedures.

  Added Windows NT V4.0 install procedure.


Alpha XL Overview
Overview Menu

Features
The Digital Alpha XL 300, 366, and 433 personal workstations have the following features:

  Low-cost, high-performance, fastest available
      on the market
  Windows NT operating system
  Easy upgradability
  Digital Semiconductor 21164
  Up to 512 MB of system memory
  Cache: 2 MB
  Local bus architecture - 32-bit, 33 MHZ PCI
      (also includes ISA bus)
  3-year warranty

Specifications:

  Mechanical
  Electrical
  Environmental


Mechanical (Size and Weight)

Mechanical Specifications

Height:	431.8 mm (17 inches)
Width:	177.8 mm (7 inches)
Depth:	431.8 mm (17 inches)
Weight:	12+ kg (28+ lbs) (less options)


Electrical Specifications

Auxiliary AC output	Do not use this outlet.
DC Outputs	Max Load	Max Power	Ripple  (Peak to Peak)
+3.3 V	35.0 Amp	115.5 W	50  mV
+5.0 V	38.0 Amp	190.0 W	50  mV
-5.0 V	0.5 Amp	2.5 W	150  mV
+12.0 V	7 Amp	84 W	100  mV
-12.0 V	0.5 Amp	6.0 W	150  mV
	Total	300   W

Note: The maximum power from any combination of +3.3 V and +5.0 V together does not exceed 210 W.


Environmental Specifications

Operating temperature range	10 [image] C to 40 [image] C
Maximum rate of change	11 [image] C per hour
Relative humidity	20% to 80% with diskette or tape
Altitude	2400 meters (8000 feet) @36 [image] C
Acoustic - power	5.1 B LWAd (Idle), 5.2 B LWAd (operating)
Acoustic - pressure	33 dBA LpAm (idle), 34 dBA LpAm (operating)
Vibration	.01G sine


Front View of the Alpha XL
Front View of the System


Digital Alpha XL Overview
Front View of the System (Door Removed)

1. Upper storage bays
2. CD-ROM drive
3. 3.5-inch floppy drive and
    nonaccessible hard disk
4. Floppy-drive diskette eject button
5. Power switch
6. Reset switch
7. Indicators
    Power-on indicator (top).
    Disk activity (middle).
    Bottom indicator is not used.


Rear View of the Alpha XL


Digital Alpha XL Overview
Rear View of the System

1.   AC selection switch.
2.   Auxiliary AC outlet. (Do not use.)
3.   AC input.
4.   Mouse connector.
5.   Keyboard connector.
6.   Serial line unit connectors (COM2 is on the left).
7.   External SCSI port.
8.   Bidirectional parallel port.
9.   Media access unit (MAU) for the embedded
      Ethernet controller.
10. Two PCI, one PCI/ISA combination, and two
       ISA expansion slots.
11. Enclosure lock.
12. Typical expansion connector.
13. Security loop (for attaching a cable or lock).


Block Diagram


Block Diagram (Hot spotted)


SROM description
SROM

The serial ROM (SROM) and the SROM bus are necessary for initial program load and diagnosis of the DECchip 21164.  The SROM contains eight jumper-selectable programs (each up to 16 KB in length).  The programs are used to perform power-up initialization and configuration of the CPU and I/O system, load floppy programs, perform manufacturing test routines, and so forth.


Digital Semiconductor 21164 Features
Digital Semiconductor 21164

The Digital Semiconductor 21164 is the system's CPU.  The chip includes integer and floating point units (FPUs), and the primary caches.  The CPU is a CMOS super-scalar, super-pipelined, quad instruction issue processor with the following features:

	300-, 366-, or 433-MHz versions.
	3.3V (300 MHz) and 2.5V (366 & 433 MHz) supply voltages.
	Quad-instruction issue.
	Pipelined floating point unit (FPU).
	Instruction cache - 8-KB on-chip, virtual, direct-mapped cache with 32-byte blocks.
	Data cache - 8-KB on-chip write-through, direct-mapped, read allocated, physical cache with 32-byte blocks.
	Second-level cache - 96-KB, three-way, set associative, physical, writeback, write allocate, mixed instruction and data cache, with 32- or 64-byte blocks.
	Write buffer with six 32-byte entries
	Demand-paged memory management unit with:   48 entry I-stream translation buffer   64 entry D-stream translation buffer
	Parity for the onboard Icache, Dcache, and Scache memories and the data bus.


Bcache features
Cache

The backup cache (Bcache) has the following features:

	2 MB cache, single-set, direct-mapped, write back, allocate on read and write.
	144 bits wide (128 data bits plus 16 ECC bits).
	Cache block size = 32 or 64 bytes (must be same as Scache).
	32K Tag Store containing: 19-bit tag address, 3-bit control and 2-bit parity.


FlashROM features
Support and flashROM

The support logic contains the flashROM interface and system interrupt logic.  The flashROM is used to store firmware.  There are two 256 KB flashROMs for a total size of 512 KB.  Under certain conditions, the flashROMs may be written, which allows field updates to the AlphaBIOS firmware.

The interrupt logic gathers the interrupt signals, provides controls, and sends the results to the CPU.


Memory SIMMs

The main memory system has the following features:

	Eight industry-standard 72-pin SIMM sockets arranged in two banks: 0 and 1.  A bank consists of four SIMMs, which must be the same size.
	Total size ranges from 32 MB to 512 MB.
	70 ns access time SIMMs.
	Each bank (four SIMMs) is 144 bits wide (128 data bits and 16 ECC bits).


PCI to SCSI Adapter

The PCI-based SCSI controller is an NCR 53C810A.  It supports 8-bit single-ended fast SCSI-2 peripherals and devices at speeds from 5 MB/second (asynchronous) to 10 MB/second (synchronous).  The system supports internal SCSI peripherals as well as those external to the system unit.  Up to seven peripherals can be on the SCSI bus.

The default device ID of the SCSI controller is 7.


Realtime Clock (TOY)

The realtime clock is a DS1287A.  The chip contains time and date information and has a provision to periodically interrupt the CPU.  The chip also contains some nonvolatile RAM.  The contents of the RAM can be cleared with motherboard jumper J22.


ISA Bus

The ISA bus originates at the PCI-ISA bridge.  In addition to the three ISA slots on the main logic board (MLB), the ISA bus connects to the Super I/O chip (adapter for the floppy disk, two serial lines, and parallel port).

ISA bus data width: 16 bits.


SuperI/O Chip

The SuperI/O chip (National PC87312) connects the ISA bus to the following:

  Floppy disk controller (FDC) - a tape backup drive also may use this bus.

  Two serial lines (UARTs) (COM1 and COM2).

  Enhanced bidirectional parallel port.


Keyboard Controller

The keyboard controller chip (8242) ties the keyboard and mouse to the utility bus.


Non_Volatile RAM
Nonvolatile RAM

The nonvolatile RAM (NVRAM) is an 8-KB device.  The NVRAM retains its contents, even while the system is turned off.  The NVRAM is used to store setup information for the AlphaBIOS firmware.  The NVRAM is accessed from the PCI-ISA bridge over the utility bus.


Memory Bus

The memory bus connects the data path chips to main memory SIMMs.

Width to/from memory:  128 data bits plus 16 ECC bits.


PCI Bus

The peripheral component interconnect (PCI) is a 32-bit-wide multiplexed address/data bus with a clock speed of 33.33 MHz (allowing a transfer rate of up to 132 MB per second).

The PCI bus provides the system with its primary I/O interconnect.  The PCI bus originates in the PCI bridge portion of the control, I/O, and address (CIA) chip.  Three PCI expansion slots, an Ethernet controller, a SCSI-2 controller, and the PCI-ISA bridge are attached to the PCI bus.

PCI bus width: 32 bits (AD[31:0])

An even parity bit (PAR) is calculated on 36 bits ( AD[31:0] and C/BE[3:0] ).


ISA Bridge

The ISA bridge manages traffic flow between the PCI bus and the ISA bus.  The bridge is an Intel 82378 System I/O chip.  Three ISA expansion slots and the SuperI/O chip (floppy, COM1, COM2, and parallel ports) are attached to the ISA bridge.  The bridge also provides a utility bus that attaches to the keyboard and mouse controller, time of year (TOY) clock, and the NVRAM.


ISA Slots
ISA Expansion Slots

There are three ISA expansion slots on the main logic board (MLB).  The uppermost ISA slot shares its position with the lowermost PCI slot, so the option in this position can be either PCI- or ISA-based.


PCI Bus Expansion Slots

There are three PCI expansion slots located on the main logic board (MLB).  The slots accommodate full-sized 32-bit PCI options requiring +5V and/or +3.3V DC.  The lowest of the three slots shares its position with the uppermost ISA slot, so the option in this position can be either PCI- or ISA-based.


Bcache Index
Bcache Interface

The Bcache interface consists of index address bits [20:04] (addresses for Bcache accesses) and tag and state bits for determining hit and conherence.  The tag data field bits are [38:20] and data parity.  The state bits are: valid, dirty, shared, and control parity.


Memory Control

The memory control is part of the core logic.  The memory control logic is physically located in the control I/O and address (CIA) chip.  The major features of this area are:

	Provides the row and column address for the memory banks.
	Provides the memory control signals (CAS and RAS).
	Controls memory refresh.


Data Path

The data path is part of the core logic.  The major data path functions are provided by:

	Bidirectional data path between the CPU, PCI bridge, and the memory SIMMs.
	The victim buffer is a 64-byte single-entry buffer where the victim of a CPU memory read transaction is saved until it can be written to memory.
	The data-out register buffers CPU victim data or DMA write data to memory.  The data-in register accepts CPU memory read data.
	The I/O write buffer consists of four 32-byte buffers.  The buffers allow the data path to sustain maximum bandwidth during large operations from memory, through the CPU, to I/O space.
	The 32-byte I/O read buffer assembles the 128-bit data required by the CPU from the 64-bit data transfers from the IOD bus.
	The DMA read/write buffers consist of two identical buffers (DMA buffer 0 and DMA buffer 1).  Each buffer consists of three 64-byte, single-entry data buffers used to hold data from memory, Bcache, and the PCI.


Memory Address
Memory Address Bus

The memory-control portion of the core logic uses this bus to send the memory address and CAS/RAS signals to the main memory SIMMs.

Bus width: 12 memory address, 2 CAS, 2 RAS, 4 Set Select, and 2 Mem Write


IOD Bus

The input/output data bus (IOD bus) carries data between the PCI bridge and the data path.

IOD Bus width: 64 bits
ECC: 8 bits


System Data Bus

The system data bus connects to the CPU, Bcache, and data path chips.

System data bus width: 128 bits plus 16 ECC bits.


System Address Bus

The system address bus connects the CPU, memory control, and the PCI bridge.

System address bus width: 31 bits.


Utility Bus

The utility bus is a subset of the ISA bus.  It is generated by the PCI to ISA bridge and provides an interface to the realtime clock, NVRAM, keyboard, and mouse.

Bus data width: 8 bits.


Ethernet Controller

The Ethernet controller (21040) is embedded in the system.  A media adapter unit (MAU) connects to the controller through a ribbon cable.  The MAU provides Twisted-Pair and ThinWire connectors on the rear bulkhead of the system.


PCI Bridge

This logic functions as a bridge between the PCI bus, CPU, and data path chips.  The PCI bridge logic has the following features:

	Scatter/gather mapping from the 32-bit PCI address to the 34-bit physical address.  Address translations are speeded up by an eight-entry translation lookaside buffer (TLB).
	Sparse and dense space addressing is supported.
	Stores address information for the DMA write buffer and I/O write buffer.


Scatter/Gather
Scatter/Gather Address Translation

Incoming 32-bit PCI memory addresses have to be mapped to the 34-bit physical memory space.  The mapping can be either direct (physical mapping with an extension register) or scatter/gather mapped (contiguous virtual pages can be mapped to pages scattered throughout physical memory).

Each time an incoming PCI address hits in a PCI target window which has scatter/gather mapping enabled, bits <31:15> of the PCI address are compared with the PCI page address in the TLB tag.  If a match is found, the required CPU page address is used along with PCI address <12:2> to form the physical memory address.

The scatter/gather map table is stored in memory.  The PCI bridge incorporates an 8-entry translation lookaside buffer (TLB) to improve scatter/gather performance.


PCI Sparse Memory Space
PCI Sparse Memory Space (80.0000.0000 - 85.7FFF.FFFF)

Sparse memory space is a region in which the lower bits of the CPU address, [6:3], indicate the transfer size.  This space provides byte, word, or tri-byte granularity, which the PCI bus requires.  CPU address bits [31:7] are sent out on the PCI bus as PCI AD[26:3].  The high-order PCI address bits <31:26> are obtained from either the HAE_MEM register or the CPU address depending on sparse space regions.


PCI Dense Memory Space
PCI Dense Memory Space (86.0000.0000 - 86.FFFF.FFFF)

Dense memory space is a region in which the minimum access granularity is a longword.  There is a one-to-one mapping between the CPU address and the PCI address.  In other words, a longword address from the CPU maps to a longword on the PCI bus.

Typically, dense space is used for data buffers on the PCI.


What Is AlphaBIOS?

AlphaBIOS brings a new look to the previous ARC firmware.  ARC stands for Advanced RISC Computing.  It dates back to an attempt to define an architecture for an industry-standard computing platform based on a non-Alpha architecture family of RISC CPUs.

To the user, AlphaBIOS refers to the firmware system that supports the Microsoft Windows NT Workstation operating system.  AlphaBIOS does not support the Digital UNIX or OpenVMS operating systems. (These systems use the SRM console.)

The AlphaBIOS firmware is a simple-to-use menu-driven system.  The firmware resides in a portion of the system flashROMs.  The design goal was to hide the complexities of older console designs from the console user.  For example, the user does not need to remember actual environment variable names but just makes a selection from a clearly worded list of choices.


What Is SRM?

The intuitive term SRM stands for System Reference Manual.  Anyone working for or with Digital knows that are many system reference manuals (VAX, Alpha, and so forth) There is probably an interesting history as to how this console earned the SRM moniker.  It might have something to do with the effort to make it the penultimate console.  This console can be so complex that some people consider it another operating system.

To the user, SRM means the console system that supports the Digital UNIX or OpenVMS operating systems.  SRM does not support the Microsoft Windows NT Workstation operating system.  (It uses the ARC or AlphaBIOS console.)

The SRM console is a full-blown command-line-interface system.  In the SRM world, syntax is king (or queen).  The SRM console code resides in a portion of the system flashROMs.  It becomes evident to the user when typing Help that this is a substantial console.  That means the SRM is more suited as a troubleshooting tool than other consoles.  During troubleshooting, you might need to switch to the SRM console to locate an otherwise-unobtainable piece of information.


Configuring the Alpha XL Personal Workstation

Configuration Menu


Basic Alpha XL Configurations
Basic Configuration Information


Configuring the Digital Alpha XL
Basic Configuration Information

Digital Alpha XL 300 and 366 systems include:

	300- or 366-MHz CPU module with 2-MB cache
	Two 32-bit PCI expansion slots, one PCI/ISA combination slot, and two ISA expansion slots.
	Eight SIMM sockets and ECC-protected main memory.
	Integrated PCI-based SCSI-2 controller with DMA and an external high-density SCSI-2 connector on the rear panel.
	Windows NT Workstation operating system.
	4X CD-ROM drive.
	1.44-MB, 3.5-inch floppy disk drive.
	Two serial ports and one bidirectional enhanced parallel port.
	PS/2 style keyboard and mouse ports.
	Keyboard and three-button mouse.
  Alpha XL Advantage Configuration information.

  Alpha XL 300 package information.

  Alpha XL 366 package information.

  Alpha XL Upgrade package information.


Alpha XL Advantage Configuration Packages
Digital Alpha XL Advantage Configuration Packages

The Alpha XL Advantage Configurations include either a 300- or 366-MHz CPU Module with 2 MB Bcache, embedded Ethernet controller, 1.44-MB floppy drive, 4X CD-ROM drive, and factory-installed Windows NT.

Advantage Order Numbers (North America/Worldwide)	Memory (1 bank)	Disk	Graphics
Alpha XL 300 SN-A22AA-NM/SN-A22WW-CM	32 MB	1.05 GB (SN-PCXRE-AA)	Matrox Millennium (SN-PCXAG-AQ)
Alpha XL 366 SN-A23AA-NM/SN-A23WW-CM	32 MB	1.05 GB  (SN-PCXRE-AA)	Matrox Millennium (SN-PCXAG-AQ)


Alpha XL 300 Packages
Digital Alpha XL 300 Packages

The systems include a 300-MHz CPU Module with 2 MB Bcache, embedded Ethernet controller, 1.44-MB floppy drive, 4X CD-ROM drive, and Windows NT.

Base System Order Numbers (North America/Worldwide)	Memory (1 bank)
SN-A22AA-AG/SN-A22WW-AG	32 MB
SN-A22AA-AH/SN-A22WW-AH	64 MB
SN-A22AA-AJ/SN-A22WW-AJ	128 MB


Alpha XL 366 Packages
Digital Alpha XL 366 Packages

The systems include a 366- MHz CPU Module with 2 MB Bcache, embedded Ethernet controller, 1.44-MB floppy drive, 4X CD-ROM drive, and Windows NT.

Base System Order Numbers (North America/Worldwide)	Memory (1 bank)
SN-A23AA-AG/SN-A23WW-AG	32 MB
SN-A23AA-AH/SN-A23WW-AH	64 MB
SN-A23AA-AJ/SN-A23WW-AJ	128 MB


Alpha XL Upgrade Packages
Digital Alpha XL Upgrade Packages

The Alpha XL upgrade packages (PowerGrade) include a new CPU module.  Depending on the upgrade path, other components, such as a motherboard and Ethernet MAU may be included with the upgrade kit.

CPU Upgrade  Order Numbers	From	To
SN-A230U-AA	Alpha XL 233 or 266 Celebris XL 5100, 5120,  5133, 6150, 6180, or 6200	Alpha XL 366
SN-A230U-AB	Alpha XL 300	Alpha XL 366
SN-A250U-AA	Alpha XL 233 or 266 Celebris XL 5100, 5120,  5133, 6150, 6180, or 6200	Alpha XL 433
SN-A250U-AB	Alpha XL 366	Alpha XL 433


Internal Mass Storage Bays


Configuring the Digital Alpha XL
Internal Mass Storage Bays

The Digital Alpha XL enclosure has five internal mass storage bays in two areas.

1.  In addition to the CD-ROM drive, the upper-bay area can hold two 5.25-inch half-height, front-accessible or nonaccessible storage devices.

2.  The lower-bay area can hold two 3.5-inch, 1.6-inch high storage devices.  One is nonaccessible from the front and typically contains the boot drive.

3.  The second drive in the lower-bay area is the standard 1.44 MB, 3.5-inch floppy diskette drive.  The floppy disk is controlled by the floppy disk controller (FDC).


Expansion Card Configuration

Configuring the Digital Alpha XL

Expansion Card Configurations

The Digital Alpha XL supports both PCI and ISA options.  There are two PCI slots (0 and 1), two ISA slots (0 and 1), and one combination PCI/ISA slot (2).  An expansion option in the combination slot may either be an ISA option or a PCI option - never both at the same time.

The following configuration rule applies to the slots:

If the system has:	There may be up to:
Three PCI-slot options	Two ISA-slot options
Two PCI-slot options	Three ISA-slot options
  Return to the Configuration Menu.


Memory Configuration


Configuring the Digital Alpha XL
Memory Configuration

The Digital Alpha XL memory may range from 32 to 512 MB.  The 70 ns DRAM memory plugs into the motherboard as two banks of four SIMMs each (eight SIMM sockets).  Alpha XL 300, 366, and 433 systems must use 36-bit SIMMs.

An important guideline to keep in mind when adding memory is: A populated bank of memory must contain four SIMMs of the same capacity.  There are no restrictions on the physical ordering among the banks when using different sized bank pairs.  For example, the SIMM group in bank 0 may be larger or smaller than the SIMM group in bank 1.  The initialization code sets the base address of the largest bank to the lowest address.


SIMM Width (33-bit or 36-bit)
SIMM Width (36-bit)

The Alpha XL 233 and 266 systems can use 33- or 36-bit SIMMs because longword parity protection is used.  The Alpha XL 300, 366, and 433 systems use ECC protection.  The extra bits needed for ECC require that 36-bit SIMMs be used.  The following table shows how to distinguish between some 33-bit and 36-bit SIMMs:

SIMM  Size (MB)	Number of DRAM Chips (36-bit SIMM)	Number of DRAM Chips (33-bit SIMM)
8	24	18
16	12	9
32	24	18


Console Configuration


Configuring the Digital Alpha XL
Console Configuration

The Digital Alpha XL flashROMs contain the AlphaBIOS firmware.

Use the AlphaBIOS firmware to:

  Display system configuration information.

  Set up the hard disks (partition and format).

  Upgrade the AlphaBIOS firmware.

  Install the Windows NT Workstation operating system.

  Control PCI parity.

  Set the date and time.

  Maintain the operating system selection list.

  AlphaBIOS section.

Configuration information is stored in the NVRAM and the TOY (RTC) on the motherboard.  If the motherboard is replaced, the information in the NVRAM and TOY is lost.  Keep records of the configuration information to facilitate getting your system back into use.


PCI Device Configuration


Configuring the Digital Alpha XL
PCI Device Configuration

The PCI bus must be initialized each time the system is powered on.  Configuration cycles (accesses to CPU addresses 87.0000.0000 through 87.1fff.ffff) are used for this purpose.  The initialization device select (IDSEL) input is used to select a PCI device during configuration read and write transactions.  The AD bits associated with the PCI devices in the Digital Alpha XL 300 and 366 are shown below:

Device	IDSEL Bit Assignment	PCI Base Address	CPU  Base Address
Ethernet Controller	AD[17]	0002.0000	87.0006.0000
PCI Bus Slot #0	AD[18]	0004.0000	87.0007.0000
SCSI	AD[20]	0010.0000	87.0009.0000
ISA Bridge	AD[21]	0020.0000	87.000a.0000
PCI Bus Slot #2	AD[22]	0040.0000	87.000b.0000
PCI Bus Slot #1	AD[23]	0080.0000	87.000c.0000

CPU base address <20:16> represents the encoded value of the IDSEL bit to be asserted (IDSEL bits range from PCI AD<31:11>).  For example, in a CPU base address of 87.0006.0000, the encoded IDSEL value is 06.  Starting at PCI AD<11> and counting up 7 bits (0-6) points to PCI AD<17>, which is hardwired as an IDSEL line to the Ethernet controller.

The PCI specification defines three physical address spaces.  Besides the usual memory and I/O space, there is configuration address space.  Configuration address space allows the devices to be initialized and configured by software/firmware.  PCI devices have 256 bytes of configuration register information.  Of the 256 bytes, 64 bytes are the predefined header region.  The remaining 192 bytes are device-specific.

The console firmware performs the following PCI-configuration tasks:

Task		Action
Determine what PCI devices are present.		Try to read the ID registers.
When a device is located, determine its address space requirements.		All 1's are written to its base address register. Device returns the address bits it uses set to 1's, all others are 0's.
Initialize the base registers.		Set up all base address registers in order from largest to smallest.


PCI Expansion Slots

Each of the three PCI expansion slots is identical except for the IDSEL assignment and arbitration.  The top slot (0) is hardwired to IDSEL bit <18>.  Slots 1 and 2 are hardwired to IDSEL bits <23> and <22>, respectively.  These bits are used during configuration cycles.

Requests from PCI slot 2 go to a sub arbitor along with embedded SCSI and Ethernet controller requests.  The sub arbitor provides round-robin arbitration before forwarding the request to the PCI arbitration unit in the PCI-ISA bridge.  Requests from PCI slots 0 and 1 go directly to the PCI-ISA bridge chip.

If an additional SCSI controller is added to the system, consider putting it in PCI slot 2 to prevent possible loss of system performance.

PCI slot 2 is part of a combination slot shared with ISA slot 2.


ISA Expansion Slots

The three ISA slots (0-2) are identical.  Each slot can hold a full-height ISA option.  ISA slot 2 is part of a combination slot with PCI slot 2.


PCI Configuration Space Header
PCI Predefined Header Region


SCSI Bus Configuration, Termination, and Length
SCSI Bus Configurations


Configuring the Digital Alpha XL
SCSI Bus Configurations

The SCSI controller (NCR 53C810) is a PCI option mounted on the motherboard.  The Digital Alpha XL supports internal and external fast SCSI-2 devices (up to four internal and seven total devices).  Termination is required at both the internal and external ends of the SCSI bus.

The internal SCSI bus cable connects to the motherboard at (1).  The daisy-chained cable has a connector (2) available for the system hard drive.  The CD-ROM and two other connectors (3) are in the upper storage bay.  The cable end connector (4) contains a SCSI terminator plug.  Additional SCSI controllers may be installed in the PCI/ISA expansion slots.
For more information:
  SCSI bus length restrictions
  Internal termination
  External termination


SCSI Bus Length

The total SCSI bus length, including internal cables and etch on the motherboard as well as the external cables between storage enclosures and the cables inside the storage enclosures, must not exceed 3 meters (9.8 feet) for fast SCSI operation or 4 meters (13.1 feet) for slow SCSI (5 MB/second) operation.  The Alpha XL system's internal SCSI length depends on the part number of the motherboard, as follows:

Part Number	Internal Length	Allowable External Length
54-24725-01	1.9 meters (6.2 feet)	1.1 meters (3.6) for fast SCSI 2.1 meters (6.9) for slow SCSI
54-24807-01	1.6 meters (5.2 feet)	1.4 meters (4.6) for fast SCSI 2.4 meters (7.9) for slow SCSI


SCSI Bus Internal Termination

The last jack of the internal SCSI bus cable is shipped with internal terminator inserted.  If you add devices on the internal SCSI bus, make sure their termination is disabled.  Refer to the appropriate drive manual.


SCSI Bus External Termination

  When no external peripherals are present, the external portion of the SCSI bus is automatically terminated (see number 1 in the figure)  If you add external SCSI peripherals (see number 2 in the figure) the automatic termination sensing detects them and turns off termination.  When external SCSI peripherals are attached, make sure the last peripheral provides proper termination.

NOTE:  The automatic termination sensing circuit functions by monitoring one of the external SCSI bus ground signals (pin 35).  If an attached SCSI device uses this signal for another purpose, you must disable the sensing circuit by jumpering J21 pin 2 to 3. (This is the case with the Digital StorageWorks devices that include the High Availability Storage Subsystem Fault bus.)


ISA Bus Configurations


Configuring the Digital Alpha XL
ISA Bus Configurations

The Digital Alpha XL 300, 366, and 433 systems have a built-in ISA device as well as slots for up to three additional ISA options.  The built-in device is a SuperI/O chip (National PC87312) which provides controllers for the floppy disk bus, two serial lines, and the bidirectional enhanced parallel port.

  Embedded ISA device addresses.


Interrupts


Configuring the Digital Alpha XL
Interrupts (Click on the blocks for more information.)


CPU Interrupts

Seven lines are used to signal interrupts to the CPU.  During initialization, these signals are used to set up the CPU cycle time divisor.

Name	Source	IPL	Comments
sys_mch_chk_irq_h	CIA error or NMI/SERR from the PCI/ISA bridge	31	The system machine check interrupt is used to indicate catastrophic errors.  Either the CIA error or the nonmaskable interrupt (IOCHK and SERR) was asserted.
irq_h<0>	CIA interrupt	20	The CIA has detected a corrected ECC error.
irq_h<1>	PCI and ISA devices	21	PCI device interrupts and 8259-compatible types (ISA device interrupts).
irq_h<2>	TOY clock	22	The TOY chip provides a periodic interrupt.
irq_h<3>	Reserved	23	Not used.
mch_hlt_irq_h	Not used	N/A	Machine halt interrupt request.  There is no provision for halting the Alpha XL systems.
pwr_fail_irq_h	Reserved	30	Power fail interrupt request (not used).


IRQ Assignments

The timer, keyboard, and mouse are hardwired to IRQs 0, 1, and 12, respectively.  The parallel port (LPT1) is assigned to IRQ7 by the AlphaBIOS firmware, although the Windows NT parallel port driver does not use interrupts.  The driver uses programmed I/O by monitoring ready/busy.  This means IRQ7 is available to other devices.

IRQ8, normally the interval timer interrupt, is not connected in the Alpha XL.  Instead, the timer interrupt signal (TOY_IRQ) is routed directly to the CPU IRQ<2> by way of the Main Interrupt Logic.

IRQ13, normally used to signal a co-processor error or signal the end of a DMA scatter/gather operation, is not connected in the Alpha XL system.


PCI Interrupt Assignments

Unlike the Alpha XL 233 and 266 systems, the 300, 366, and 433 systems do not assign PCI interrupts to IRQs.

Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD).  Typically, PCI devices use INTA.  PCI boards with multiple devices may use more than one INT signal.  All of the INT signals are routed to the Main Interrupt Logic.  Along with other signals (ISA interrupt, board rev level, and console jumpers), they are OR'd together and sent to the CPU on its IRQ<1> line.


Main Interrupt Logic

The Main Interrupt Logic is located on the GRU chip.  The interrupt logic performs the following functions:

	Logically OR's the NMI and CIA_ERROR signals together.  The result is sent to CPU as a machine check interrupt.
	Routes corrected ECC errors from the CIA to the IRQ<0> interrupt on the CPU.
	Collects all PCI interrupts (INTA, INTB, INTC, INTD, embedded Ethernet, and embedded SCSI), the etch type (300 or 366 Mhz module), console jumpers (secure and alternate), and the ISA INT signal. Registers (Interrupt Request, Interrupt Mask, Interrupt Level/Edge, Interrupt High/Low, and Interrupt Clear) control the various interrupt inputs.  The result is sent to the CPU on the IRQ<1> signal line.
	Routes the TOY chip periodic interrupt to the CPU on the IRQ<2> signal line.
	During initialization, the interrupt logic routes the clock divisor value to the CPU over the IRQ<3:0> signal lines.


IRQ Controller

The interrupt controller is the functional equivalent of two 82C59 controllers and is located in the PCI to ISA bridge chip.  IRQ2 on the master controller is used to cascade the controllers together.  This means that IRQ8-IRQ15 have a higher priority than IRQ3-IRQ7.


TOY Interrupt

The realtime clock (Dallas 1287A) sends the CPU a periodic interrupt request.


CIA Interrupts

The CIA chip, which contains the memory logic, PCI bridge, and I/O and DMA address logic, can request two types of interrupts: corrected ECC and error.

The INT signal is used to notify the CPU that the CIA has detected a corrected ECC error.

The ERROR signal is used to notify the CPU that the CIA has detected an error other than a corrected ECC error (for example, nonexistent memory, uncorrectable ECC, PCI bus errors, sysBus parity errors, and so forth).


Ethernet Controller Interrupt

The interrupt signal from the embedded PCI-based Ethernet controller is wired directly to the main interrupt logic.


SCSI Controller Interrupt

The interrupt signal from the embedded PCI-based SCSI controller is wired directly to the main interrupt logic.


DMA Channel Assignments


Configuring the Digital Alpha XL
DMA Channel Assignments

The ISA interface uses eight DMA channels.  DMA channel 4 is used to cascade the two four-channel controllers together and therefore is unavailable.

Any DMA channel may be programmed for 8-bit or 16-bit transfers.

Channel	Device
0	Available to ISA option slots.
1	Available to ISA option slots.
2	Floppy Disk Controller (FDC).
3	Available to ISA option slots and the parallel port.
4	Unavailable (channels 0-3 are cascaded to this channel).
5	Available to ISA option slots.
6	Available to ISA option slots.
7	Available to ISA option slots.


Address Space Map


Configuring the Digital Alpha XL
Address Space Map

Cacheable
00.0000.0000 -	00.1fff.ffff	Main memory
00.2000.0000 -	7f.ffff.ffff	Reserved
Noncacheable
PCI sparse memory space
80.0000.0000 -	83.ffff.ffff	16 GB: PCI memory region 0 - 512 MB of PCI memory space.
84.0000.0000 -	84.ffff.ffff	4 GB: PCI memory region 1 - 128 MB of PCI memory space.
85.0000.0000 -	85.7fff.ffff	2 GB: PCI memory region 2 - 64 MB of PCI memory space.
85.8000.0000 -	85.bfff.ffff	1 GB: PCI I/O region A -  32 MB of PCI I/O space.   Embedded ISA device addresses.
85.c000.0000 -	85.ffff.ffff	1 GB: PCI I/O region B -  32 MB of PCI I/O space.
PCI dense memory space
86.0000.0000 -	86.ffff.ffff	4 GB: PCI memory.
Miscellaneous
87.0000.0000 -	87.1fff.ffff	512 MB: PCI configuration space.
87.2000.0000 -	87.3fff.ffff	512 MB: GB: PCI interrupt/special cycle.
87.4000.0000 -	87.4fff.ffff	256 MB: CIA main CSRs.
87.5000.0000 -	87.5fff.ffff	256 MB: CIA PCI memory control CSRs.
87.6000.0000 -	87.6fff.ffff	256 MB: CIA PCI address translation.
87.7000.0000 -	87.7fff.ffff	256 MB: Reserved.
87.8000 0000 -	87.ffff.ffff	2 GB: GRU registers and flashROM


I/O View of Address Space


Configuring the Digital Alpha XL
I/O View of Address Space


ISA Device Addresses

All addresses are shown in hexadecimal.

Device	ISA Address	CPU Address
Keyboard	060	85.8000 0C00
Mouse	064	85.8000 0C80
TOY clock	070 071	85.8000 0E00 85.8000 0E20
COM1	03F8 - 03FF	85.8000 7F00 - 85.8000 7FE0
COM2	02F8 - 02FF	85.8000 5F00 - 85.8000 5FE0
Parallel port	0378 - 037F	85.8000 6F00 - 85.8000 6FE0
Floppy disk controller	03F2 - 03F7	85.8000 7E40 - 85.8000 7EE0


Troubleshooting

Troubleshooting Menu

When troubleshooting, select the button from the upper group that identifies the area where the system is experiencing problems.

The lower group of buttons furnish access to supporting information.


Troubleshooting Strategy


Digital Alpha XL
Troubleshooting Strategy

A successful troubleshooting strategy requires a plan of attack.  Gathering information is the first action to perform.  Use the site log to review the system's service history.  Ask the user or customer contact the following questions:

	What first alerted the user to the problem?
	Were there any recent changes or upgrades to the operating system, firmware, or application software?
	What symptoms did the user notice?  Ask about any unusual sounds or smells.
	Did the user make any initial troubleshooting efforts?  What were the results?
	Is the operating system functioning? If the answer is No, use power on self test (POST) and other loadable diagnostics. If the answer is Yes, use the system to gather information from log files such as the error log , operator log, and crash dump files.  Run operating system-based diagnostics, such as DEC VET.


Troubleshooting Process
A Troubleshooting Strategy


Power System Troubleshooting


Digital Alpha XL
Power System Troubleshooting

Click on the arrows for information about power-related indicators.  A power troubleshooting checklist will be displayed if you click on the checklist button.


Indicator Panel

There are three indicators on the control panel.  The upper indicator should be ON when the system is switched on.  The middle indicator lights during disk activity.  The lower indicator is unpredictable.


Power Switch

The power switch must be pushed in to turn on the system.  If the switch is bad, replace the power supply.  (The switch is hardwired to the power supply.)


Power Troubleshooting Checklist


Digital Alpha XL
Power Troubleshooting Checklist

Symptom	Check

Control panel power indicator is OFF.	Front-panel power switch pushed in.
	Power at wall receptacle.
	AC cord.
	Voltage selection switch.
Control panel power indicator is ON for a few seconds and then goes OFF.	There are two fans.  One is at the front of the system near the 21164, and the other is in the power supply. Caution: The power supply shuts OFF if it senses that either fan has failed.
Control panel power indicator is ON, and display monitor is blank.	Monitor power indicator is ON. Raster present if brightness is turned up.
	Fuses and circuit breakers.
	Video controller cable properly connected.
	Power present at system board.  Click here for pinouts.


Power Supply Pinouts


Power Supply Pinouts

Power 	Pin	Wire 	Voltage
Supply 	Number	Color
Connector

P8 and P9 (Disk Drive)	1 2 3 4	Red Black Black Blue	+5V GND GND +12V
P4-P7 and P11 (Disk Drive)	1 2 3 4	Blue Black Black Red	+12V GND GND +5V
P1 (motherboard)	1 2 3 4 5 6	White Red Blue Yellow Black Black	POK_H +5V +12V -12V (key) GND GND
P2 (motherboard)	1 2 3 4 5 6	Black Black Gray Red Red Red	GND (key) GND -5V +5V +5V +5V
P3 (motherboard)	1 2 3 4 5 6	Red Red Red Black Black Black	+5V +5V +5V(key) GND GND GND
P10 (motherboard)	1-8 9-16	Black Orange	GND +3.3V
Fan Connector Variable (8.5-15.2V)	1 2	Red Black	+Fan Fan Rtn


Cooling Problems
Thermal Problems


Digital Alpha XL
Thermal Problems

The Digital Alpha XL system operates in an ambient temperature range of 10 to 40C.  The system unit is cooled by two speed-controlled fans.  One fan is in the power supply, and one is in front of the CPU.

The power supply varies the fan voltage based on the feedback from a temperature sensor located in the fan/speaker assembly.  The voltage may range from 7.0 to 13.0V.  The power supply contains a fan-fail detector that shuts down power after a one-second delay if either fan fails.  Fan failures are detected by monitoring fan ripple current.

Intermittent problems could result from overheating.  Check that the air flow path is clear.  Make sure there are not any materials blocking the input grill.  Also check to see that the cables inside the system are properly dressed.  A dangling cable will impede the airflow.


Powerup Status Codes


Digital Alpha XL
Powerup Status Codes

Powerup status codes are available to a terminal connected to the SROM port.  The symptoms of an initialization problem may also be heard as beep codes or displayed on the monitor (if enough of the logic is functioning correctly).

When power is turned on, SROM code initializes the CPU, core logic, and memory.  After successful initialization, the SROM code loads and starts the AlphaBIOS firmware.  The SROM powerup status codes are divided into three main categories:

1.	FF to F0	Fatal error codes (Powerup program halts with no further activity.)
2.	EF to E0	Error codes (May not prevent AlphaBIOS from starting.)
3.	DF to CC	Status codes (Identify current process in the powerup sequence.)

The SROM contains other programs, including the SROM Mini-Console (300-MHz CPU - J10; 366- and 433-MHz CPU - J12). and the SROM Floppy Loader Program (300-MHz CPU - J9; 366- and 433-MHz CPU - J13).

For more status and initialization information:

  SROM Powerup Status Codes

  AlphaBIOS firmware initialization steps

  Beep codes


SROM Powerup Status Codes


Digital Alpha XL
SROM Powerup Status Codes

Powerup Codes                Description

FF	No Scache bits set in SC_CTL register.
FE	Reserved.
FD	Floppy driver error.
FC	Reserved.
FB	Reserved.
FA	No usable memory was detected.
F9	System initialization error.
F8	PCI data path error.
F7	Reserved.
F6	Bad CIA memory CSR detected.
F5	Bcache data path error.
F4	Bcache address line error.
F3	Bcache cell error.
F2-EC	Reserved.
EB	CPU speed detection failure.
EA	Reserved.
E9	No realtime clock (TOY) detected.
E8-E6	Reserved.
E5	Memory data path error.
E4	Memory address line error.
E3	Memory cell error.
E2	Reserved.
E1	FlashROM data path read error.
E0	FlashROM checksum error.  If checksum error, jump to code anyway.  (If the AlphaBIOS firmware fails to run, move the SROM program selection jumper to J9 [300-MHz CPU] or J13 [366- or 433-MHz CPU] to select the SROM Floppy Loader Program and insert a floppy disk containing the firmware.
DF	SROM program entered.
DE	Initializing CPU/system interface.
DD	Sizing CPU speed.
DC	Sizing the Scache.
DB	Initializing and testing the PCI bus (read the PCI-ISA bridge chip Vendor ID and Device ID).
DA	Reserved.
D9	Memory sizing in progress.
D8	Memory configuration in progress.
D7	Bcache initialization in progress.
D6	Memory test initialization. (32 MB of memory is tested.)
D5	Bcache bits test in progress.
D4	Memory bits test in progress.
D3	Bcache address test in progress.
D2	Memory address test in progress.
D1	Bcache cell test in progress.
D0	Memory cell test in progress.
CF	Memory initialization.
CE	FlashROM code loaded (AlphaBIOS firmware).
CD	CPU/system interface reinitialization.
CC	Transferred control to the flashROM code.


AlphaBIOS Firmware Initialization Steps


Digital Alpha XL
AlphaBIOS Firmware Initialization Steps

Initialization Steps

Initialize the video and keyboard.  If either is not functioning or is missing, AlphaBIOS directs output to the COM1 port.

Display a windowed, graphical-style user interface.

Test memory.

Initialize SCSI controllers and disks.

Display the boot screen.


Beep Codes


Digital Alpha XL
Beep Codes

Beep Code     Meaning

1-1-4	FlashROM data path error (manufacturing data pattern not what expected) or flashROM checksum error.
1-2-4	The SROM code detected a hard failure (for example, a Bcache or memory failure).
1-3-3	The SROM could not find 2 MB of good memory, or no memory is present.


What Is a Beep Code?

Beep codes emit from the system's speaker as three groups of beeps.  For example, if the SROM code could not find any good memory, you would hear a 1-3-3 beep code (one beep, a pause, a burst of three beeps, a pause, and another burst of three beeps).


SROM Mini-Console

The SROM mini-console is provided for use by manufacturing and service.  You need an SROM Serial Port Adapter Module (54-21827-01) to connect to J12 on the 300-MHz CPU module (J24 on the 366- or 433-MHz CPU).  The other end of the adapter connects to the COM port of a terminal interface (for example, laptop, PC, or workstation running a communication utility).  The SROM port is set to 19.2 Kbaud.  The following table lists some of the communications utilities that furnish a terminal interface:

System	Communications Utility
MS DOS	Kermit
Windows	Terminal, KEA
Digital UNIX	Tip, Kermit
OpenVMS	Set host/dte, Kermit

The console features a set of basic commands.


SROM Floppy Loader Program

The primary function of the SROM Floppy Loader Program is to provide a mechanism to easily recover from system flashROM corruption.

The SROM Floppy Loader Program performs the following tasks:
  Initializes the CPU for the SROM powerup code environment.
  Initializes the I/O system and tests its data path, including the PCI/ISA bridge.
  Determine the CPU clock frequency.
  Size and configure main memory.
  Test and initialize the Bcache and main memory.
  Test the data path to the system flashROMs.
  Load the system firmware from the floppy to main memory.
  Initialize the SROM mailbox data structure for the firmware.
  Transfer execution to the system firmware.

The floppy must be formatted as Files-11 with an OpenVMS boot block pointing to the file to be loaded.


SROM Mini-Console Commands

Command	Description
BA	Get a base address and set the base address mode flag.
SA	Set the base address flag mode.
CA	Clear the base address flag mode.
HM	Set the high memory address flag mode.
LM	Clear the high memory address flag mode.
QW	Set the quadword data mode flag.
LW	Clear the quadword data mode flag.
DM	Deposit data to one memory location.
EM	Examine data at one memory location.
FM	Fill a block of memory with a data pattern.
BM	Block read between two memory locations.
WM	Looping write sequence to one memory location.
RM	Looping read sequence from one memory location.
!M	Looping read/write sequence at one memory location.
XM	Load an external image to memory.
ST	Start the execution at an address.


Console Troubleshooting


Digital Alpha XL
Console Troubleshooting

The Digital Alpha XL contains AlphaBIOS firmware.  AlphaBIOS firmware supports the Windows NT operating system.  The firmware does not contain diagnostics.  (Manufacturing has a set of loadable diagnostics to support their environment.)

If a power failure occurs while the firmware was being updated in the flashROMs, it could corrupt the contents of the flashROMs.

The flashROMs (containing the AlphaBIOS firmware) typically are loaded by SROM's flash loader code.  If the flashROMs are corrupted, or if the checksum verification failed, the SROM flash loader will go ahead and attempt to start the AlphaBIOS code.

If the firmware fails to start, try the floppy load program.  Select the SROM floppy load program by moving J11 to J9 on the 300-MHz CPU module (J11 to J13 on the 366- or 433-MHz CPU).  Insert the diskette containing the firmware and power on the system.  Select Upgrade AlphaBIOS from AlphaBIOS Setup to rewrite the flashROMs.


Boot Troubleshooting


Digital Alpha XL
Boot Troubleshooting

Possible Cause	Action

Will not boot from an IDE hard disk drive.	Configuration not supported.
Operating system software is not installed on the hard disk drive.	Install the Windows NT operating system.
Someone forgot the AlphaBIOS password.	Replace the motherboard.
System cannot find the boot device.	Check the system configuration for correct device parameters. Use the AlphaBIOS firmware to display the hardware configuration.  First, from the Boot screen, press F2 to enter AlphaBIOS Setup.  Select Display System Configuration.  Verify that the target boot device is listed.  Also, go to Utilities - OS Selection Setup and verify that the path is correct.
Environment variables incorrectly set (this could happen if the CPU module or the motherboard was replaced, thereby losing the previous configuration information).	Check and set the environment variables, if necessary. From AlphaBIOS Setup, go to CMOS Setup and Advanced CMOS Setup.  Check the values and correct as necessary. From AlphaBIOS Setup, go to Utilities and select OS Selection Setup.  Verify the boot paths are correct.
Bad device name/number or partition number...	The system partition value is pointing to an invalid partition. From the AlphaBIOS Setup screen, select Utilities and OS Selection Setup.  Press F9 to validate the selection.  To edit the selection, press F6.
File is not a directory..., or No such file or directory...	The osloader value is incorrect.  The system partition value is okay. From the AlphaBIOS Setup screen, select Utility then OS Selection Setup.  Press F9 to validate the selection.  To edit the selection, press F6.
Windows NT could not start because the following file is missing or corrupt:  <winnt root> \system32\ntoskrnl.exe	The osloadpartition and/or osloadfilename values are incorrect.  Your best bet is to delete the boot selection and start again.  Carefully consider the question, "Is the operating system in the same partition as the osloader?".  Typically, they are in different partitions.
Windows NT started initializing, but the system hung.	Try booting with the /SOS boot option.  This will display a list of files as they are loaded. When the hang occurs, the last file listed might be the cause of the hang (maybe it is missing or corrupt).
Hard disk drive is not correctly formatted or the requested partition does not exist.	Partition and format the hard disk drive using Hard Disk Setup section of AlphaBIOS Setup.  Press F7 for to perform an express setup on disk 0.
There is no software on the requested partition.	If the command is pointing to the correct partition, install the software.  Otherwise, change the variables to point to the correct partition.
Target boot device is not listed in the Display hardware configuration display due to a SCSI bus problem.	Check the cables.  Are the cables oriented properly and not cocked? Are there bent pins? Check all the SCSI devices for incorrect or conflicting IDs.  Refer to the device's documentation. SCSI termination: The SCSI bus must be terminated at the last internal and the last external SCSI peripherals.  The last connector of the internal SCSI cable contains a terminator.  If there are no external options, the external portion of the SCSI bus is automatically terminated..
System boots, but too slowly.	Check the SCSI bus termination.
Floppy drive runs continuously.	Check the cable. Make sure it is not reversed.  The drive ID may also be set incorrectly.


Troubleshooting Errors and Machine Checks
Machine Checks


Digital Alpha XL
Machine Checks

When an error exception occurs, the CPU does the following:

1.	Drains the pipeline.
2.	Loads the program counter (PC) into the EXC_ADDR register.
3.	Dispatches to a PALcode exception routine located at PAL_BASE plus an offset.  The offset for machine checks is 0x0020.
4.	The Windows NT PALcode performs some information gathering and dumps the results on the screen.  Write down the information displayed otherwise it will be lost.  Note that the error information is not logged in the Windows NT Event Logger.  (It may be logged in the future.)

  One approach to analyzing a machine check.


Error Checking Map


Error Checking Map (Hot spotted)


21164 Error Detection

Error detection in the 21164 is concentrated in the Bus Interface Unit (BIU).  The Alpha XL CPU uses ECC to ensure data integrity.  Click on an error for more information.

Icache Tag or Data Parity Error

Scache Data Parity Error - Istream

Scache Tag Parity Error - Istream

Scache Data Parity Error - Dstream

Scache Tag Parity Error - Dstream

Dcache Data Parity Error

Dcache Tag Parity Error

Istream Uncorrectable ECC Error

Dstream Uncorrectable ECC Error

Bcache Tag Parity Error - Istream

Bcache Tag Parity Error - Dstream

System Command/Address Parity Error

Istream or Dstream Correctable ECC Errors


Icache Data or Tag Parity Error

The Icache is parity protected.  A machine check occurs before the instruction causing the parity error is executed.

ICPERR_STAT: DPE (data parity error) or TPE (tag parity error) is set.

EXC_ADDR contains either the PC of the instruction causing the parity error or that of an earlier trapping instruction.

The Icache is not flushed by hardware in this event.

  Return to the CPU error detection window


Scache Data Parity Error - Istream

A machine check occurs before the instruction causing the parity error is executed.  Bad data may be written to the Icache or Icache refill buffer and validated.  The operation can be retired if there are not multiple errors.

SC_STAT: SC_DPERR<7:0> is set; <SC_SCND_ERR> is set if there are multiple errors.
SC_STAT: CBOX_CMD is IREAD.

SC_ADDR: Contains the address of the 32-byte block containing the error.  (Bit 4 indicates which octaword was accessed first, but the error may be in either octaword.)

  Return to the CPU error detection window


Scache Tag Parity Error - Istream

A machine check occurs before the instruction causing the parity error is executed.  Bad data may be written to the Icache or Icache refill buffer and validated.  The operation cannot be retired.

SC_STAT: SC_TPERR<2:0> is set; <SC_SCND_ERR> is set if there are multiple errors.
SC_STAT: CBOX_CMD is IREAD.

SC_ADDR: Contains the address of the 32-byte block containing the error.  (Bit 4 indicates which octaword was accessed first, but the error may be in either octaword.)

  Return to the CPU error detection window


Scache Data Parity Error - Dstream

A machine check occurs.  The machine state may have changed.  You cannot retry this, but deleting the process may be sufficient if the data was confined to a single process and no second error occurred.

SC_STAT: SC_DPERR<7:0> is set; <SC_SCND_ERR> is set if there are multiple errors.
SC_STAT: CBOX_CMD is DREAD, DWRITE, or READ_DIRTY.

SC_ADDR: Contains the address of the 32-byte block containing the error.  (Bit 4 indicates which octaword was accessed first, but the error may be in either octaword.)

  Return to the CPU error detection window


Scache Tag Parity Error - Dstream

A machine check occurs.  The machine state may have changed.  You cannot retry this, and probably will not be able to recover by deleting a single process because the exact address is unknown.

SC_STAT: SC_TPERR<2:0> is set; <SC_SCND_ERR> is set if there are multiple errors.
SC_STAT: CBOX_CMD is DREAD, DWRITE, READ_DIRTY, SET_SHARED, or INVAL.

SC_ADDR: Records physical address bits <39:04> of the location with the error.

  Return to the CPU error detection window


Dcache Data Parity Error

The Dcache data is parity protected.  A machine check occurs. The machine state may have changed.  You cannot retry this, but may only need to delete the process if data is confined to a single process and no second error occurred.

DCPERR_STAT: <DP0> or <DP1> (data parity error in bank 0 or 1) is set.  <LOCK> is set.  <SEO> is set if there are multiple errors.

VA: Contains the virtual address of the quadword with the error.

MM_STAT: Locked. Contents contain information about instruction causing the error.

  Return to the CPU error detection window


Dcache Tag Parity Errors
Dcache Tag Parity Error

The Dcache Tag is parity protected.  A machine check occurs. The machine state may have changed.

DCPERR_STAT: <TP0> or <TP1> (tag parity error in bank 0 or 1) is set.  <LOCK> is set.  <SEO> is set if there are multiple errors.

VA: Contains the virtual address of the Dcache block (hexword) with the error.

MM_STAT: Locked. Contents contain information about instruction causing the error. The <WR> bit is set if the error occurred on a store instruction.

  Return to the CPU error detection window


Istream Uncorrectable ECC Error

A machine check occurs before the instruction causing the parity error is executed.  Bad data may be written to the Icache or Icache refill buffer and validated.  You can retry the operation if there are not multiple errors.

The Icache must be flushed to remove bad data.  The Icache refill buffer may be flushed by executing enough instructions to fill the refill buffer with new data (32 instructions).  Then re-flush the Icache.

EI_STAT: <UNC_ECC_ERR> is set; <SEO_HRD_ERR> is set if there are multiple errors.
EI_STAT: <EI_ES> is set if source of fill data is memory/system, clear if Bcache.
EI_STAT: <FIL_IRD> is set.

EI_ADDR: Contains the physical address bits <39:4> of the octaword associated with the error.

FILL_SYN: Contains the syndrome bits associated with the failing octaword.

BC_TAG_ADDR: Holds the result of external cache tag probe if external cache was enabled for this transaction.

  Return to the CPU error detection window


Dstream Uncorrectable ECC Error

A machine check occurs.  The machine state may have changed.  You cannot retry the operation, but may only need to delete the process if the data is confined to a single process and no second error occurred.

EI_STAT: <UNC_ECC_ERR> is set; <SEO_HRD_ERR> is set if there are multiple errors.
EI_STAT: <EI_ES> is set if source of fill data is memory/system, clear if Bcache.
EI_STAT: <FIL_IRD> is clear.

EI_ADDR: Contains the physical address bits <39:4> of the octaword associated with the error.

FILL_SYN: Contains the syndrome bits associated with the failing octaword.

BC_TAG_ADDR: Holds the result of external cache tag probe if external cache was enabled for this transaction.

  Return to the CPU error detection window


Bcache Tag Parity Error - Istream

A machine check occurs before the instruction causing the parity error is executed.  Bad data may be written to the Icache or Icache refill buffer and validated.  You can retry the operation if there are not multiple errors.

The Icache must be flushed to remove bad data.  The Icache refill buffer may be flushed by executing enough instructions to fill the refill buffer with new data (32 instructions).  Then re-flush the Icache.

EI_STAT: <BC_TPERR> or <BC_TC_PERR>is set; <SEO_HRD_ERR> is set if there are multiple errors.
EI_STAT: <EI_ES> is clear.
EI_STAT: <FIL_IRD> is set.

EI_ADDR: Contains the physical address bits <39:4> of the octaword associated with the error.

BC_TAG_ADDR: Holds the result of external cache tag probe.

  Return to the CPU error detection window


Bcache Tag Parity Error - Dstream

A machine check occurs.  The machine state may have changed.  You cannot retry the operation, but may only need to delete the process if the data is confined to a single process and no second error occurred.

EI_STAT: <BC_TPERR> or <BC_TC_PERR>is set; <SEO_HRD_ERR> is set if there are multiple errors.
EI_STAT: <EI_ES> is clear.
EI_STAT: <FIL_IRD> is clear.

EI_ADDR: Contains the physical address bits <39:4> of the octaword associated with the error.

BC_TAG_ADDR: Holds the result of external cache tag probe.

  Return to the CPU error detection window


System Command/Address Parity Error

A machine check occurs and the machine state may have changed.

EI_STAT: <EI_PAR_ERR> is set; <SEO_HRD_ERR> is set if there are multiple errors.
EI_STAT: <EI_ES> is set.

EI_ADDR: contains the physical address bits <39:4> of the octaword associated with the error.

BC_TAG_ADDR: Holds results of external cache tag probe if external cache was enabled for this transaction.

When the 21164 detects a command or address parity error, the command is unconditionally NOACKed.

  Return to the CPU error detection window


Istream or Dstream Correctable ECC Error

The 21164 hardware corrects the data before filling the Scache and Icache.  The Dcache is completely invalidated.  The data in the Bcache contains the ECC error but is scrubbed by PALcode in the correctable interrupt routine.

A separately maskable correctable error interrupt occurs at IPL 31 (same as machine check) (masked by clearing ICSR<CRDE>).

ISR: <CRD> is set.

EI_STAT: <COR_ECC_ERR> is set.
EI_STAT: <FIL_IRD> is set if Istream or clear if Dstream.
EI_STAT: <EI_ES> is clear if source of the error is Bcache, and set otherwise.

EI_ADDR: Contains the physical address bits <39:4> of the octaword associated with the error.

FILL_SYN: Contains the syndrome bits associated with the octaword containing the ECC error.

BC_TAG_ADDR: Unpredictable (not loaded on correctable errors).

  Return to the CPU error detection window


Serial ROM (SROM)

The SROM and the SROM interface to the 21164 do not have error checking capability.


Memory Logic Error Detection

The memory logic provides the row and column address for the memory banks.  The memory logic provides control signals to the data path, informing the data path logic when to send/strobe data to/from memory.  The memory logic also controls memory refresh.  The memory logic is capable of detecting nonexistent memory errors (CIA_ERR:<MEM_NEM>)

When this error is detected, CIA_ERROR is sent to the machine check interrupt request pin of the 21164 CPU.  In addition, the following actions occur:

	Locking the current sysBus address into CPU_ERR0 and CPU_ERR1.
	Locking the MEM_ERR0 and MEM_ERR1 registers.
	Locking the CIA_ERR, except for the LOST bits, which are set if another error occurs when the register is locked.


Bcache Error Detection

The Bcache does not detect errors, but it is protected; the data by ECC and the tag by parity.  ECC is generated by the CPU for each group of 8 bytes written into the Bcache.  Fill data from the Bcache to the system is not checked for errors.

During a fill from the Bcache, if a correctable error is detected (single- bit error), the CPU traps and the fill is replayed with corrected data.

Double bit errors are detected.

The tag data <38:20> is protected by a tag data parity bit.

The tag control bits: shared, valid, and dirty. are protected by the tag control parity bit.

A Bcache tag data parity or tag control parity error is usually not recoverable.

Keep your cache cool.  Dress the cables properly to let the air flow without blockage.


ROM Error Detection

The flashROM section of the system uses checksums to protect the data.  The SROM code verifies ROM data through a checksum.


Memory Data Path Error Detection

There is no ECC or parity logic in the data path.  Data from memory is passed unmodified to the CPU/Bcache or the PCI bridge logic.


Memory Error Detection

The memory SIMMs do not detect errors, but they do furnish information though ECC bits to error detection networks in the CPU and PCI bridge.  During CPU initiated transactions, ECC is typically generated by the CPU (in the case of a write Bcache victim to memory, the ECC is from the Bcache).  For DMA write transactions, ECC is generated in the PCI bridge.

If there is bad parity on data being written from the PCI to memory during a DMA write, the PCI agent which instigated the DMA write is allowed to complete normally, but the write data is discarded (CIA_ERR<PERR> will be set).


PCI Bridge Detected Errors

When the PCI Bridge detects errors, the CIA_ERR, PCI_ERR0, 1, and 2, MEM_ERR0 and 1, and CPU_ERR0 and 1 registers log information and addresses that might be related to the error.  Click on an error for information the actions taken as a result of the error.

CPU-Initiated Transaction Errors:

Bad PCI address (No device error)	ECC errors
PCI address parity errors	CPU system interface parity errors
PCI data parity errors	IO timeout
DMA-Transaction Errors:

PCI address parity error	Address/command bad parity
PCI data parity errors	Scatter/gather invalid errors
Uncorrectable data error	Bcache tag bad parity
Non-existent memory errors


Bad PCI Address (No Device Error)

On an I/O transaction initiated by the PCI bridge, if DEVSEL# is not asserted within five cycles, the PCI bridge assumes that no PCI device is going to respond to this transaction.  The following actions are taken:

  The RCVD_MAS_ABT bit in CIA_ERR is set.

  PCI_ERR0 and 2 contain information relevant to the error.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


PCI Address Bad Parity

On an I/O transaction initiated by the PCI bridge, a PCI address parity error can be detected in one of the following ways:

	During a CPU read or write, the PCI agent detected the address parity error and terminated the transaction with a PCI target abort.  CIA_ERR:<RCVD_TAR_ABT> is set.
	During a CPU write, the PCI agent allowed the CPU write to complete cleanly and asserted SERR.
	During a CPU read or write, if no PCI agent responds, the PCI bridge generates a PCI master abort (CIA_ERR:<RCVD_MAS_ABT> is set.
For all of the above, information relevant to the error is stored in PCI_ERR0 and 2.  A machine check interrupt is requested.

An address parity error on the ISA bus will result in a nonmaskable interrupt (NMI) being sent to the CPU.

  Return to the PCI bridge error detection window


PCI Data Parity Error
PCI Data Parity Errors

The parity of the PCI AD lines, the byte enables, and the parity bit (PAR) is checked for even parity.  If even parity does not exist, a PCI data parity error has occurred.

On CPU I/O read transactions, a PCI data parity error is detected by the PCI bridge which asserts PERR.

On CPU I/O write transactions, a PCI data parity error is detected by the target PCI device, which asserts PERR.

For all of the above, CIA_ERR:<PERR> is set and information relevant to the error is stored in PCI_ERR0 and 2.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


ECC Errors

There are two types of ECC errors: corrected and uncorrectable.

For CPU I/O writes:

	Corrected ECC occurs when the CPU I/O write data had a single-bit error which was corrected.  The CIA_ERR:<COR_ERR> is set and a low-level interrupt (CPU IRQ<0>) is issued.
	Uncorrectable ECC errors are stopped at the PCI bridge.  The PCI transaction is cleanly terminated.  The PCI agent does not receive any bad data.  The CIA_ERR:<UN_COR_ERR> bit is set.
Information relevant to both types of ECC error can be found in CIA_SYN and the PCI_ERR0 and two registers (if status bits indicate that an I/O operation is in progress).

For CPU I/O reads, the CPU detects the ECC error and takes a machine check.

A machine check interrupt is requested for the uncorrectable errors.

  Return to the PCI bridge error detection window


I/O Timeout

On a read or write I/O transaction, the PCI bridge uses an I/O timeout register to detect fatal PCI bus hangs.  When an I/O timeout occurs, CIA_ERR:<IOA_TIMEOUT> is set.  Information relevant to the error is stored in PCI_ERR0 and 2.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


CPU System Interface Bad Parity

On a read or write I/O transaction, the PCI bridge checks parity on the sysBus.  When a parity error occurs, CIA_ERR:<CPU_PE> is set.  Information relevant to the error is stored in CPU_ERR0 and 1.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


Address Parity Error (DMA)
PCI Address Parity error (DMA)

On any DMA (PCI-initiated) transaction address phase, if the parity of the incoming address (PCI AD), command (C/BE),and parity (PAR) is not even, an address parity error occurred.

For DMA reads, the PCI bridge will target abort the transaction to the PCI agent which instigated the transaction.  The CIA_ERR:<PCI_ADDR_PE> bit is set.  Relevant error information is stored in PCI_ERR0,1, and 2.

For DMA writes, the PCI bridge allows the PCI agent which instigated the transaction to complete normally, except that the write data is not written to memory.  The PCI bridge does not issue a target abort.  The CIA_ERR:<PCI_ADDR_PE> bit is set.  Relevant error information is stored in PCI_ERR0 and 1.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


PCI Data Parity Error (DMA)

On any DMA read or write transaction (data phase), if the parity of the incoming data (PCI AD), byte enables (C/BE), and the parity bit (PAR) is not even, a data parity error occurred.  Even if the device asserts PERR and the PCI bridge takes no action, it is the master's responsibility to handle the error.

For DMA reads, the PCI agent which instigated the transaction will detect the data parity error, and will assert PERR (and possibly post an interrupt).  The CIA_ERR:<PERR> bit is set.  Relevant error information is stored in PCI_ERR0, 1, and 2.

For DMA writes, the PCI agent which instigated the transaction is allowed to complete normally, but the write data is discarded by the PCI bridge.  The CIA_ERR:<PERR> bit is set.  Relevant error information is stored in PCI_ERR0 and 1.

A machine check interrupt is requested.

  Return to the PCI bridge error detection window


ECC Errors (DMA)

Corrected and uncorrectable ECC errors may occur on DMA reads and writes in the following instances: DMA data to/from memory, DMA data to/from Bcache, scatter/gather TLB miss from memory, and scatter/gather TLB miss from Bcache.

For DMA reads or writes, a corrected ECC error causes the CIA_ERR:<COR_ERR> bit to set.  Relevant error information is stored in CIA_SYN and PCI_ERR0 and 1 and a low-level interrupt (CPU IRQ<0>) is issued.

For DMA reads, an uncorrectable ECC error causes the CIA_ERR:<UN_COR_ERR> bit to set.  Relevant error information is stored in CIA_SYN and PCI_ERR0 and 1.  The PCI agent which instigated the DMA read has the transaction target aborted by the PCI bridge.

For DMA writes, an uncorrectable ECC error causes the CIA_ERR:<UN_COR_ERR> bit to set.  Relevant error information is stored in CIA_SYN and PCI_ERR0 and 1.  The PCI agent that instigated the DMA write is allowed to complete normally, except that the write data is not written to memory.  The PCI bridge does not issue a target abort.

A machine check interrupt is requested for uncorrectable ECC errors.

  Return to the PCI bridge error detection window


Scatter/Gather TLB Entry Invalid Error

On scatter/gather mapped DMA transactions, the scatter/gather entry being accessed might be invalid.

For DMA reads, the PCI agent which instigated the operation has the transaction target aborted by the PCI bridge.

For DMA writes, the PCI agent which instigated the operation is allowed to complete normally, except that the write data is not written to memory.  For a long DMA write (consisting of many blocks), the PCI bridge will take the first block of data and disconnect the DMA write (because of a TLB miss - invalid TLB entries always start with a TLB miss).  The PCI bridge discards the data in its write buffer and the bridge accepts the next PCI transaction.  The retired (bad) DMA write may get in again because the whole procedure repeats on a block-by-block basis.  Thus, the interrupt handler should be aware that a bad DMA device may still be active when servicing the error condition.

For both DMA read and writes, the CIA_ERR:<PA_PTE_INV> bit is set, and relevant error information is stored in PCI_ERR0 and 1.

  Return to the PCI bridge error detection window


Non-Existent Memory Access (DMA)
Nonexistent Memory Access Error

A nonexistent memory access error occurs when a DMA or a PTE (page table entry) tries to access nonexistent memory.

For DMA reads, the PCI agent which instigated the DMA read has the transaction target aborted by the PCI bridge.

For DMA writes, the PCI agent which instigated the DMA write is allowed to complete normally, except that the write data is not written to memory.  The PCI bridge does not issue a target abort.

When the error occurs, the CIA_ERR:<MEM_NEM> bit is set.  Relevant error information is stored in MEM_ERR0 and 1, and PCI_ERR0 and 1 (if doing DMA).

  Return to the PCI bridge error detection window


Address/Command Parity Error (DMA)
Address/Command Parity Error

During DMA transactions, the sysBus is driven by the PCI bridge to flush or read the caches.  The bus is protected with odd parity.  If the CPU receives an address/command with a parity error, the EI_STAT:<EI_ES> and <EI_PAR_ERR> bits are set, and the EI_ADDR register is loaded with the physical address, and the CPU initiates a machine check.

  Return to the PCI bridge error detection window


Bcache Tag Parity Error (DMA)

During DMA transactions, the Bcache can be flushed or read.  The Bcache tag address and tag control bits are read during these transactions.  The tag address bits and the tag control bits are protected with parity bits to maintain odd parity.  If the CPU detects a tag address parity error or a tag control parity error, the EI_STAT:<BC_TPERR> or the <BC_TC_PERR> bits are set.  The EI_ADDR register is loaded with the physical address, and the CPU initiates a machine check.

  Return to the PCI bridge error detection window


PCI Bus Error Detection

Not all PCI devices are required to detect and report parity errors, but all are required to generate parity on all of their transactions. Some do this more successfully then others.  See Disabling PCI Parity.

During the address phase, the PAR bit provides even parity for AD [31:0] and C/BE[3:0] regardless of whether or not all the lines carry meaningful information.

Master devices drive PAR for the address and data phases on write transactions. Target devices drive PAR during the data phase of read transactions.

The PCI contains PERR and SERR to signal errors.  PERR reports data parity errors for all transactions except special cycle commands.  PERR can only be driven by one device at a time.  Targets signal data parity errors back to the master using PERR.

SERR reports address parity errors and data parity errors on special cycles.  It is a wire-OR'd signal that can be driven by multiple devices at any one time.  SERR will be sent to the CPU as an NMI.


ISA Bus Error Detection

The ISA bus uses I/O Channel Check (IOCHK) to signal that some ISA device detected a parity error on the ISA bus.  The assertion of IOCHK will cause an NMI to be sent to the main interrupt controller, which in turn sends a machine check interrupt request to the CPU.


Analyze a Machine Check
Analyzing Machine Checks


Digital Alpha XL
Analyzing Machine Checks

At this time, the Windows NT PALcode and the Hardware Abstraction Layer (HAL) do not build machine check frames.  Presently, when a machine check error occurs some information is dumped on the screen.  You must write the error information down when it is displayed, or it will be lost.

When error logging capability is finally added to the PALcode and HAL, use the following approach to analyze a machine check:

First, get the machine check code.  If the error code is less the 0x200, then the error is a CPU-detected error.  Codes above 0x201 are system-detected errors, that is, errors detected by the CIA chip. (The CIA includes the PCI bridge and the memory control logic.)

Isolate an uncorrectable ECC error to a failing SIMM.

Troubleshoot CPU detected errors (codes less than 0x200) by using the following registers:

Register	Description
EI_STAT	Contains bits for:   Bcache Tag Parity Error.   Bcache Tag Control Parity Error.   External interface source (Bcache or memory).   Uncorrectable ECC error.   External Interface Parity Error.   FILL_IRD bit to determine of the error    was detected on an I-stream or D-stream fill.   Second Error Occurred Bit.
EI_ADDR	Contains the physical address associated with errors reported in the EI_STAT register.
SC_STAT	Contains bits that allow you to:   Isolate the set on an Scache data parity error.   Isolate the failing longword on an Scache data parity error.   Log the Scache transaction at the time of the error.
SC_ADDR	Contains the physical address associated with errors reported in the SC_STAT register.
IC_PERR_STAT	Contains information about an Icache parity error.
DC_PERR_STAT	Contains information about a Dcache parity error.

Troubleshoot CIA detected errors (codes greater than 0x201) by using the following registers:

Register	Description
CIA_ERR	Contains bits that indicate:   Bcache/memory ECC error.   S/G map invalid error.   Address/Command bus parity error.   Non-existent memory.   PCI SERR asserted.   PCI PERR asserted.   PCI address parity error.   CIA received a PCI master abort.   CIA received a PCI target abort.   FlashROM write error.   PCI I/O timeout error.   Various lost error bits.
CIA_STAT	Information about what the CIA was doing at the time of the error.  However, because the CIA can do numerous concurrent operations, the status may have nothing to do with the error condition.
CPU_ERR0 CPU_ERR1	Address and command field for:   Interface parity error.   CPU read/write to non-existent memory.
CIA_SYN	Contains the syndromes for ECC errors detected by the CIA (PCI bridge).
MEM_ERR0 MEM_ERR1 MEM_ERR2	Address, command, and memory timing parameters when the CPU performed a read/write to non-existent memory.
PCI_ERR0 PCI_ERR1 PCI_ERR2	PCI address and command pertaining to the error. Also indicates if the CIA (PCI bridge) was the master or target of the PCI transaction.
ERR_MASK	Used to mask the detection and reporting of CIA errors.


Failing SIMM Isolation


Digital Alpha XL
Failing SIMM Isolation

Here is an example of how to troubleshoot an uncorrectable ECC error and identify the failing SIMM.  Assume that for this example, the machine check code is 0x88 (CPU detected uncorrectable ECC error).  The code would be 0x203 for a system (CIA) detected uncorrectable ECC error and would be investigated using different registers.

Check the EI_STAT:<32>(UNC_ECC_ERR) bit.  If set, fill data from outside the CPU contained an uncorrectable ECC error, so check the following:

EI_STAT<30>=1 or 0	If set, the bad fill data is from main memory. If clear, the bad fill data is from the Bcache.
EI_STAT<34>=1 or 0	If set, the error occurred during an Icache fill. If clear, the error occurred during a Dcache fill.
FILL_SYN<7:0>	Contains the syndrome associated with the lower quadword of the bad octaword.  A syndrome of 0 means there are no errors in this quadword.   List of syndromes (sorted by data bit).   List of syndromes (sorted by syndrome bit).
FILL_SYN<15:8>	Contains the syndrome associated with the higher quadword of the bad octaword. A syndrome of 0 means there are no errors in this quadword.
EI_ADDR	Physical address where the failure occurred.

Assuming the source is main memory (EI_STAT:<30>=1), the error is caused by bad data coming from the memory SIMMs.  The next question is, "Which SIMM is causing the trouble?"

Determine the system's memory configuration (the starting address and capacity of each bank).	From the AlphaBIOS boot screen, press F2 to enter AlphaBIOS Setup.  Select Display System Configuration..., then choose Memory.  The memory configuration is displayed. For example, Bank 0: 32MB (8MB/SIMM) Start at 0x00000000 Bank 1: 32MB (8MB/SIMM) Start at 0x02000000
Compare the failing address with the memory configuration to identify the failing bank. Now that we know which bank is failing, the next step is to identify which SIMM in the bank is bad.	Assuming that the EI_ADDR register contained 002B7BF8, this location would be located in bank 0.  Alpha XL 300 or 366 logical bank layout.
Use the FILL_SYN register to identify which octaword is failing.
FILL_SYN<7:0>=nonzero	The ECC error is in the low octaword (<63:00>) of the failing hexword.
FILL_SYN<15:8>=nonzero	The parity error is in the high octaword (<127:64>) of the failing hexword.   List of syndromes  (sorted by data bit).   List of syndromes (sorted by syndrome bit).
Assuming that FILL_SYN=008A, then the SM6 SIMM is suspect.	You have now isolated the failing SIMM.  Reseat or replace the SIMM in connector SM6.


Logical Memory Bank Layout


ECC Syndromes (Sorted by Data Bits)
ECC Syndrome Codes (Sorted by Data Bits)

Data Bit / Syn Code	Data Bit / Syn Code	Data Bit / Syn Code	Data Bit / Syn Code	Check Bit / Syn Code
0 / CE	16 / 0E	32 / 4F	48 / 8F	0 / 01
1 / CB	17 / 0B	33 / 4A	49 / 8A	1 / 02
2 / D3	18 / 13	34 / 52	50 / 92	2 / 04
3 / D5	19 / 15	35 / 54	51 / 94	3 / 08
4 / D6	20 / 16	36 / 57	52 / 97	4 / 10
5 / D9	21 / 19	37 / 58	53 / 98	5 / 20
6 / DA	22 / 1A	38 / 5B	54 / 9B	6 / 40
7 / DC	23 / 1C	39 / 5D	55 / 9D	7 / 80
8 / 23	24 / E3	40 / A2	56 / 62
9 / 25	25 / E5	41 / A4	57 / 64
10 / 26	26 / E6	42 / A7	58 / 67
11 / 29	27 / E9	43 / A8	59 / 68
12 / 2A	28 / EA	44 / AB	60 / 6B
13 / 2C	29 / EC	45 / AD	61 / 6D
14 / 31	30 / F1	46 / B0	62 / 70
15 / 34	31 / F4	47 / B5	63 / 75


ECC Syndromes (Sorted by Syndrome Bits)
ECC Syndrome Codes (Sorted by Syndrome Bits)

(CB = Check Bit)

Syn Code /  Data Bit	Syn Code /  Data Bit	Syn Code /  Data Bit	Syn Code /  Data Bit	Syn Code /  Data Bit
01 / 0 (CB)	26 / 10	64 / 57	A2 / 40	E3 / 24
02 / 1 (CB)	29 / 11	67 / 58	A4 / 41	E5 / 25
04 / 2 (CB)	2A / 12	68 / 59	A7 / 42	E6 / 26
08 / 3 (CB)	2C / 13	6B / 60	A8 / 43	E9 / 27
0B / 17	31 / 14	6D / 61	AB / 44	EA / 28
0E / 16	34 / 15	70 / 62	AD / 45	EC / 29
10 / 4 (CB)	40 / 6 (CB)	75 / 63	B0 / 46	F1 / 30
13 / 18	4A / 33	80 / 7 (CB)	B5 / 47	F4 / 31
15 / 19	4F / 32	8A / 49	CB / 1
16 / 20	52 / 34	8F / 48	CE / 0
19 / 21	54 / 35	92 / 50	D3 / 2
1A / 22	57 / 36	94 / 51	D5 / 3
1C / 23	58 / 37	97 / 52	D6 / 4
20 / 5 (CB)	5B / 38	98 / 53	D9 / 5
23 / 8	5D / 39	9B / 54	DA / 6
25 / 9	62 / 56	9D / 55	DC / 7


Disabling PCI Parity Checking


Digital Alpha XL
Disabling PCI Parity Checking

Digital Equipment systems are engineered to protect the customer's data.  Parity protection is one method to help accomplish this.  In the PC market, parity protection is relatively rare.  Even in the new world of PCI options, parity is not consistently implemented.  In fact, there are cases in which PCI devices have a parity-generating scheme in which the parity is incorrect.  The device functions properly as long as parity is not checked.

You might find yourself working on a system with one of these parity-challenged PCI devices.  Your customer might not appreciate the finer points of data security when the bad parity causes system problems.  In appreciation of this, the AlphaBIOS firmware has an option that allows you to turn off PCI parity checking.  Do not take this step lightly, however.

In the AlphaBIOS firmware, the PCI parity-checking option is located in the Advanced CMOS Setup screen.  You can reach it by taking the following path:

1.	From the Boot screen, press F2 to enter AlphaBIOS Setup.
2.	From AlphaBIOS Setup, select CMOS Setup.
3.	From CMOS Setup, press F6 to enter Advanced CMOS Setup.
4.	Choose the appropriate setting.


SCSI Controller Error Detection

The SCSI controller is an NCR 53C810 chip.  On the PCI side, if the SCSI controller detects an address parity error, it asserts SERR which results in a nonmaskable interrupt (NMI).

On the SCSI bus side, if the controller detects a parity error while receiving or sending SCSI data, and the appropriate interrupt enable bits in the controller are set, an interrupt will be asserted.


Non-Maskable Interrupts (NMI)
Nonmaskable Interrupts (NMI)

The nonmaskable interrupt (NMI) originates on the PCI/ISA bridge chip (Intel 82378).  NMI will be asserted for the following conditions:

	SERR#: An address parity error has been detected on the PCI bus.  The PCI/ISA bridge chip takes no action other than reporting the error to the CPU.  SERR# is also used to report catastrophic system errors, such as certain master or target aborts.
	IOCHK#: A parity error has been detected on an expansion module plugged into the ISA bus.


Troubleshooting Tools


Digital Alpha XL
Troubleshooting Tools

There are many tools available to assist you with troubleshooting.  Some tools help test and exercise the system, whereas others gather and format information.

The DEC Verifier and Exerciser Tool (DEC VET) falls into the first category.  DEC VET is an online tool for verifying system installations and acceptance.  It is also used to maintain and troubleshoot systems, and perform load and stress tests on single devices, systems, and networks.  There are versions of DEC VET for different operating systems.  For more information, see the DEC Verifier and Exerciser Tool User's Guide for Windows NT

Each operating system has a specific mechanism for capturing and logging error information.

Windows NT


Accessing the Windows NT Error Log

Windows NT maintains an event log file. The event logging service starts automatically when Windows NT is started. The Event Viewer is used to view and manage the event logs.

Start the Event Viewer by clicking on its icon. The icon is located in the Administrative Tools group in Program Manager. Windows NT uses three logs:

System log	Tracks events logged by Windows NT system components: for example, the failure of a driver to properly load.
Application log	Tracks events logged by applications.
Security log	Tracks changes to the security system and identifies possible security breaches.

Use the Log menu of the Event Viewer to select the log you need to view.

For more information, see the Event Viewer chapter in the Microsoft Windows NT System Guide or use online Help.


FRU Replacement

FRU Replacement Menu

Opening the Enclosure

Memory SIMMs

ISA and PCI Options

CPU Module

Storage Options

Motherboard

Media Access Unit

Power Supply

Speaker

System Fan

CAUTION: Remove the AC power cord and follow ESD procedures when working on the Alpha XL System.


Opening the Enclosure

Digital Alpha XL 300, 366, or 433 FRU Replacement

Opening the Enclosure

To open the Digital Alpha XL enclosure, follow these steps:
1.	Turn off the system.
2.	Turn off any external peripheral devices.
3.	Use the key to unlock the cover.
4.	Slide the left side cover back and remove it.


Memory SIMM Removal and Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Memory SIMM Removal and Replacement

Release the clips and remove the failing SIMM.  Keep in mind that you may have to remove other SIMMs to gain access to the bad one.  You can improve access to SIMMs by removing the CPU module.  Remember where the SIMMs were placed.  Make sure the SIMMs are seated and the clips have snapped in place.

  Memory configuration guidelines.


ISA and PCI Option Removal

Digital Alpha XL 300, 366, or 433 FRU Replacement

ISA and PCI Option Removal

To remove the ISA and PCI option boards, follow these steps:

1.	Disconnect any cables connected to the option board you are removing.
2.	Remove the screw at the rear end of the option card.
3.	Gently pull out the option card.
4.	Configure the option by checking and setting switches and jumpers according to the option documentation.
5.	Plug the replacement card into the appropriate slot.  Make sure the card is fully seated.
6.	Fasten the card in with the mounting screw.
7.	Connect previously removed cables to the replacement card.


Expansion Board R and R


CPU Module Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

CPU Module Replacement

To replace the CPU module, follow these steps:

1.	Power off the system and disconnect the power cord.
2.	Remove the side cover.
3.	Loosen the captive screw (1) in the middle of the CPU module bracket.
4.	Gently pull the two brackets outward to unseat the CPU module.
5.	Remove the CPU module and place it in an ESD-protected bag.
6.	Check that the 300-,  366-, or 433-MHz CPU jumpers are configured correctly.
7.	Remove the new CPU module from its ESD-protected bag and install it in the motherboard by inserting the front shield tab into the third groove of the fan/speaker assembly and the rear of the module into the pivot bracket.
8.	While ensuring that the CPU connector is aligned with the motherboard connector, firmly press the CPU module with both hands (one on each end) until it seats.  Hint: You may find this easier if you lay the system on its side.
9.	Replace the side cover.
10.	Connect the power cable and power on the system.


CPU Module Removal


Speaker Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Speaker Replacement

To replace the internal speaker, follow these steps:

1.	Remove the CPU module.
2.	Disconnect the speaker cable from J24 on the motherboard.
3.	Gently slide the thermal sensor out of the clip on the rear of the fan/speaker housing.
4.	Remove the fan/speaker housing by pressing in on the two snap clips at the front edge of the housing while pulling the housing to the rear.  Exercise caution because the fan power cable is still attached.
5.	Remove the faulty speaker by gently pulling it out of the housing.
6.	Install the replacement speaker into the housing and route its cable through the slot and the clip on the side of the housing.
7.	Mount the fan/speaker housing back into the enclosure by first putting the inside tabs in their respective slots and then snapping the housing in place.  Observe the cables while you are doing this.
8.	Connect the speaker cable to J24 on the motherboard.
9.	Reinsert the CPU module and replace the side panel.


Main Logic Board Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Motherboard Replacement

NOTE: The motherboard contains the time of year (TOY) chip and the NVRAM.  The TOY chip also contains 50 locations of battery supported RAM.  The RAM contains information used by the firmware.  Configuration information is stored in the NVRAM.  When the motherboard is replaced, the information is lost.  Keeping records of the configuration (IRQs, DMAs, I/O addresses, and so forth) will facilitate getting the system back into use.

To replace the motherboard, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cords at the rear of the system.
3.	At the rear of the system, disconnect the cables for the:   Keyboard   Mouse   Serial line units (2)   Printer   External SCSI bus   PCI or ISA options   MAU
4.	Remove the side cover.
5.	Remove the CPU module.
6.	Remove any PCI and ISA options and the memory SIMMs.
7.	Remove the MAU and ribbon cable.
8.	Disconnect cables plugged into the main logic board (MLB).
9.	Remove the fan/speaker assembly.
10.	Remove the motherboard-mounting screws (8).
11.	Gently slide the motherboard slightly to the front and remove the motherboard.  You can improve access by removing the lower-bay assembly first.
12.	Check the motherboard jumpers, then slide the new motherboard into the enclosure.  Adjust the motherboard so it is well seated on the eight locators and the ground is not bent at the I/O ports.
13.	Secure the motherboard with 8 screws.
14.	Replace the fan/speaker assembly.
15.	Attach the cables:   Front panel to J18.   Speaker to J24.   Power connectors P1 and P2 to J13.   Power connectors P3 to J14 and P10 to J6.   MAU ribbon cable to J20.   Floppy cable to J5    SCSI cable to J4.
16.	Insert the memory SIMMs.
17.	Insert the PCI and ISA options and the MAU.
18.	Insert and fasten the CPU module.
19.	Reinstall the side panel.
20.	Attach the cables to the rear connectors.
21.	Power up the system.


Media Access Unit (MAU) Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Media Access Unit (MAU) Replacement

To replace the MAU, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cord at the rear of the system.
3.	At the rear of the system disconnect the customer's network cable at the MAU.
4.	Remove the side cover.
5.	Remove the MAU mounting screw.
6.	Remove the MAU board.
7.	Disconnect the cable plugged into the MAU at J2.
8.	Connect the replacment MAU to the cable.
9.	Insert the MAU board into the rear bulkhead slot and secure it with the mounting screw.
10.	Replace the side cover.
11.	Reconnect the customer's Ethernet connection to the MAU.
12.	Reconnect the AC power cord.
13.	Power on the system.


Media Access Unit (MAU) Replacement


Storage Options Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Storage Options Replacement

There are two mass storage areas in the Alpha XL.  The upper bay can hold three 5.25-inch devices that are accessible from the front.  The lower area holds two 3.5-inch devices: one (typically, the floppy drive)accessible, and one (typically, the system disk) nonaccessible.

  Upper bay option replacement

  Lower bay option replacement


Upper Storage Bay Option Replacement
Upper Storage Bay


Upper Storage Bay

The upper storage bay may contain three 5.25-inch, half-height devices that can be either accessible or nonaccessible from the front of the system.  If you remove one set of rails, the lower two positions can accommodate a full-height option.  Typical upper-bay options include a CD-ROM or tape drive.  To replace an upper-bay option, follow these steps:

1.	Power off the system and disconnect the AC power cables.
2.	Remove both side panels.
3.	Remove the metal access plate.
4.	Remove the failing drive's mounting screws from both sides.
5.	Remove the drive through the front of the system box.
6.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
7.	Transfer the mounting bracket (if used) from the faulty option to the new option.
8.	Insert the new option through the front of the system box.
9.	Fasten the option with the mounting screws.
10.	Connect the cables, including power, data, and, possibly, audio.
11.	Replace the metal access plate.
12.	Replace both side covers.
13.	Connect the AC power and turn on the system.


Access Plate


Upper Bay Drive Removal


Lower Storage Bay Option Replacement
 Lower Storage Bay


Lower Storage Bay

The lower storage bay accommodates two 3.5-inch devices, one nonaccessible from the front.  The lower-bay devices are mounted in a drive-bracket assembly.  To replace drives in the lower bay, follow these steps:

1.	Turn off the system and disconnect the AC power cord.
2.	Unlock and remove the side panel.
3.	While supporting the bay assembly, lift the retaining clip at the top rear, and slide the assembly toward the rear.  Exercise care to avoid straining the cables.
4.	Remove the cables from the devices mounted in the lower bay bracket.
5.	Remove the faulty drive from the bracket by removing the screws on the sides.
6.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
7.	Insert and mount the new drive into the bracket assembly.
8.	Connect the cables to the drives.
9.	Reinstall the drive bracket assembly by lifting and sliding it forward until the retaining clip latches.
10.	Replace the side panel.
11.	Connect the AC power and turn on the system.


Lower Bay Assembly Removal


Power Supply Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

Power Supply Replacement

To replace the power supply, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cords at the rear of the system.
3.	Remove the side panels.
4.	Remove the metal access plates from both sides of the enclosure.
5.	Remove the barrier plate to allow access to the power supply's AC switch cable.  The barrier plate is located just below the right-access plate removed in step 4.
6.	Disconnect the power supply cables going to:   Motherboard (4)   Lower storage-bay options (floppy and hard drive)   Upper storage-bay options
7.	Unfasten the thermal sensor mounted in a clip on the rear of the fan/speaker housing.
8.	Carefully free the thermal sensor cable.
9.	Disconnect and free the fan cable.
10.	Remove the mounting screw for the power switch.
11.	Pull the power switch out from the rear.  As you are removing the switch, the plastic power button on the front will pop off.
12.	Remove the power supply mounting screws.
13.	Carefully slide the power supply out of the enclosure while ensuring that all the cables do not get caught.
14.	Install the replacement power supply by repeating the above steps in reverse order.


Left and Right Access Plates


System Fan Replacement

Digital Alpha XL 300, 366, or 433 FRU Replacement

System Fan Replacement

To replace the system fan, follow these steps:

1.	Remove the CPU module.
2.	Disconnect the speaker cable from J24 on the motherboard.
3.	Gently slide the thermal sensor out of the clip on the rear of the fan/speaker housing.
4.	Remove the fan/speaker housing by pressing in on the two snap clips at the front edge of the housing, while pulling the housing to the rear.  Exercise caution because the fan power cable is still attached.
5.	Disconnect the fan power cable.
6.	Remove the faulty fan by pressing the clips at the top and bottom and pulling the fan out of the housing.
7.	Install the replacement fan into the housing and route its cable through the slot and the clip on the side of the housing.
8.	Connect the fan power cable.
9.	Mount the fan/speaker housing back into the enclosure by first putting the inside tabs in their respective slots and then snapping the housing in place.  Keep an eye on the cables while you are doing this.
10.	Connect the speaker cable to J24 on the motherboard.
11.	Reinsert the CPU module and replace the side panel.


Part Numbers

Digital Alpha XL 300, 366, or 433

Part Numbers

Field Replaceable Units (FRUs)

300-MHz CPU assembly      300-MHz CPU module (with 2-MB cache)      CPU shield assembly      Fan pipe      Left ejector-bracket assembly      Right ejector-bracket assembly	70-32992-01      54-24693-01      70-32982-01      74-51166-01      70-32994-01      70-32993-01
366-MHz CPU assembly - includes the       366-MHz CPU module (with 2-MB cache)      with the same shield, air pipe, and brackets as      the 300-MHz CPU.	70-32992-02      54-24748-01
433-MHz CPU assembly - includes the       433-MHz CPU module (with 2-MB cache)      with the same shield, air pipe, and brackets as      the 300-MHz CPU.	70-32992-03      54-24748-03
Bracket, Left (drive-bay side metal cover)	74-48468-01
Bracket, Right (drive-bay side metal cover)	74-48469-01
Bracket, pivot (for catching the left CPU handle)	74-51283-01
Enclosure	70-31243-05
Exchange Bracket (3.5-in. drives in 5.25-in. bays)	74-48510-01
Fan	12-41569-01
Ferrite bead assembly	16-25105-16
Floppy diskette drive (3.5 in. 1.44 MB)	RX23L-AA
Front panel switch card	54-22088-02
Indicator and reset assembly (front panel)	70-30799-01
Medallion, Alpha XL 300	74-48976-68
Medallion, Alpha XL 366	74-48976-76
Medallion, Alpha XL 433
Medallion, Digital	74-48816-01
Media access unit (MAU)	54-24736-03
Memory (one 8 MB, 2M x 36-bit, 70ns)	54-21246-BA
Memory (one 16 MB, 4M x 36-bit, 70ns)	54-23170-AA
Memory (one 32 MB, 8M x 36-bit, 70ns)	54-21277-AA
Motherboard (Typically used with the 300 MHz CPU)	54-24725-01
Motherboard (Typically used with the 366 MHz CPU)	54-24807-01
Power supply (300-Watt)	30-41069-04
SCSI terminator (for internal portion of the bus)	12-41670-01
Speaker	12-39309-01

Digital Alpha XL 300, 366, or 433 Cable Part Numbers

SCSI (internal) - Motherboard to internal SCSI drives, 50-conductor, flat ribbon daisy-chained with three drive connectors	17-03923-03
Floppy - Motherboard to floppy drive, 34-conductor, slit flat ribbon with two FDD connectors	17-03460-03
Front panel - Motherboard to front panel, 6-conductor, twisted pair	17-03582-01
MAU - Motherboard to MAU, 20-conductor flat	17-04071-01


Connector Pinouts

Digital Alpha XL 300, 366, or 433

Connector Pinouts

Note: Systems using revision A01 of the 54-24725-01 motherboard (used with the 300-MHz CPU) have the keyboard and mouse connectors reversed.  A label was added to the rear of the system to properly identify these systems.  Newer motherboards have the connectors in the position identified by the icons.


Keyboard Port Pinouts


Digital Alpha XL 300, 366, or 433
Keyboard Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

Keyboard
1	KBData
2	N/C
3	Ground
4	+5 VDC
5	KBClock
6	N/C


Mouse Port Pinouts


Digital Alpha XL 300, 366, or 433
Mouse Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

Mouse
1	MSData
2	N/C
3	Ground
4	+5 VDC
5	MSClock
6	N/C


External SCSI
External SCSI Port Pinouts


Digital Alpha XL 300, 366, or 433
External SCSI Port Pinouts

50-pin high-density Honda-type receptacle

Pin	Signal		Pin	Signal/Meaning
1	Ground		26	DB(0) Data bus line 0
2	Ground		27	DB(1) Data bus line 1
3	Ground		28	DB(2) Data bus line 2
4	Ground		29	DB(3) Data bus line 3
5	Ground		30	DB(4) Data bus line 4
6	Ground		31	DB(5) Data bus line 5
7	Ground		32	DB(6) Data bus line 6
8	Ground		33	DB(7) Data bus line 7
9	Ground		34	DB(P) Data bus parity
10	Ground		35	Ground
11	Ground		36	Ground
12	Reserved		37	Reserved
13	Open		38	TERMPWR Terminator power
14	Reserved		39	Reserved
15	Ground		40	Ground
16	Ground		41	ATN Attention
17	Ground		42	Ground
18	Ground		43	BSY Busy
19	Ground		44	ACK Acknowledge
20	Ground		45	RST Reset
21	Ground		46	MSG Message
22	Ground		47	SEL Select
23	Ground		48	C/D Control/Data
24	Ground		49	REQ Request
25	Ground		50	I/O Input/Output


Communication Ports Pinouts


Digital Alpha XL 300, 366, or 433
Communication Ports Pinouts

9-Pin Sub D, plug, DB9  (Both serial line unit connectors have the same pinouts.)

	Pin	Signal	Meaning
	1 2 3 4 5 6 7 8 9	DCD RX TX DTR Ground DSR RTS CTS RI	Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal Ground Data Set Ready Request to Send Clear to Send Ring Indicator


Parallel Port Pinouts
Bidirectional Parallel Port Pinout


Digital Alpha XL 300, 366, or 433
Bidirectional Parallel Port Pinouts

25-position, Sub D, receptacle, DB25

Pin	Signal	Meaning
1		Strobe
2	PD0	Data bit 0
3	PD1	Data bit 1
4	PD2	Data bit 2
5	PD3	Data bit 3
6	PD4	Data bit 4
7	PD5	Data bit 5
8	PD6	Data bit 6
9	PD7	Data bit 7
10		Acknowledge
11	BUSY	Busy
12	PE	Paper End
13	SLCT	Select
14		Auto line feed
15		Error
16		Initialize printer
17		Select in
18-25	Ground	Ground


Jumpers (Motherboard and CPU Modules)

Digital Alpha XL 300, 366, or 433

Jumpers


Motherboard Jumpers


Digital Alpha XL 300, 366, or 433

Motherboard Jumpers

(D) = Default

Note: The orientation of J21 depends
on the version of the motherboard.

Jumper    Setting      Function              Description

J21	1 to 2 (D) 2 to 3	Autosense enabled Autosense and termination disabled	J21 controls the automatic SCSI bus terminator.   If an external SCSI cable is attached to the SCSI connector, the automatic SCSI terminator turns off.  The SCSI bus must be terminated at the end of the external bus. Disable sensing when attaching devices that modify the definition of the SCSI pin used for sensing.  For example,  Digital StorageWorks devices using the high-availability storage subsystem fault bus.
J22	1 to 2 (D) 2 to 3	Normal Clear CMOS	CMOS clear.  When 2 to 3 is jumpered and power is turned on, the memory located in the realtime clock is cleared.  NOTE: This jumper does not clear the contents of the NVRAM.


300 MHz CPU Module Jumpers
300-MHz CPU Module Jumpers


Digital Alpha XL 300, 366, or 433

300-MHz
CPU Module
Jumpers

(D) = Default

Jumper     Setting      Function               Description

J2 J3 J5 J6 J7 J9 J10 J11	Out Out Out Out Out Out Out In (D)	No Init mini-console MCHK mini-console Reserved Reserved MFG Memtest Failsafe floppy Mini-console Power up	SROM Program Select Jumpers.  Only one of these jumpers can be installed at any one time.
J15	1 to 2 2 to 3 (D)	Write disabled Write enabled	FlashROM write enabled.
J17	1 to 2 2 to 3 (D)	Alternate console Primary	Alternate console.
J18	1 to 2 2 to 3 (D)	Secure Not secure	Secure console.


366 MHz CPU Module Jumpers
366-MHz CPU Module Jumpers


Digital Alpha XL 300, 366, or 433

366- and 433-MHz
CPU Module
Jumpers and
Switches

(D) = Default

Jumper     Setting     Function                Description

J19 J17 J16 J15 J14 J13 J12 J11	Out Out Out Out Out Out Out In (D)	No Init mini-console MCHK mini-console Reserved Reserved MFG Memtest Failsafe floppy Mini-console Power up	SROM Program Select Jumpers.  Only one of these jumpers can be installed at any one time.
J18	1 to 2 2 to 3 (D)	Write disabled Write enabled	FlashROM write enabled.
J10	1 to 2 2 to 3 (D)	Alternate console Primary	Alternate console.
J9	1 to 2 2 to 3 (D)	Secure Not secure	Secure console.

Switches SW1 and SW2

Speed	SW1-1	SW1-2	SW1-3	SW1-4	SW2-1	SW2-2	SW2-3	SW2-4
366	OFF	ON	OFF	OFF	OFF	OFF	ON	OFF
433	OFF	OFF	ON	OFF	ON	OFF	OFF	ON


Watch This Space!

You just know that an Alpha XL motherboard is the foundation for the fastest CPUs in the world!  It's a safe bet that this button will soon point to another, even-higher-performing Alpha CPU module.


Powerup Status Codes

Digital Alpha XL 300, 366, or 433

Powerup Status Codes

Powerup status codes are available to a terminal connected to the SROM port.  The symptoms of an initialization problem are displayed on the monitor (if enough of the logic is functioning correctly) or heard as beep codes.  Since the speaker is driven from the ISA bridge chip, most of the system must be working to generate the beep codes.

  SROM Powerup Status Codes

  AlphaBIOS firmware initialization steps

  Beep codes


Registers
Digital Alpha XL 300, 366, or 433 - Registers


Machine Check Types


Machine Check Types

    CPU Detected Errors                            CIA Detected Errors

0x80 0x82 0x84 0x86 0x88 0x8A 0x90 0x96 0x98	Tag parity error Tag control error Hardware error Correctable ECC Uncorrectable ECC Bugcheck OS bugcheck Icache read error CPU detected error		0x201 0x203 0x205 0x207 0x209 0x20B 0x20D 0x20F 0x211 0x213 0x215 0x217 0x219 0x221	Correctable ECC error Uncorrectable ECC error CIA-detected parity error Nonexistent memory error PCI SERR detected PCI data parity error PCI address parity error PCI master abort error PCI target abort error S/G PTE invalid error FlashROM write error IOA timeout detected IOCHK on ISA bus Unexpected CPU IRQ3 int.


PAL Temp Registers

Digital Alpha XL 300, 366, or 433 Registers

PAL Temp Registers

There are 24 PAL temp registers made up of 64-bits each.  The PALcode uses the registers.


Exception Address Register (EXC_ADD)

Digital Alpha XL 300, 366, or 433 Registers

Exception Address Register (EXC_ADD)

Address: IPR Ibox, Index=10B

The exception address register is used to restart the machine after exceptions or interrupts.

Click on the Description button to display the bit fields.


EXC_ADD Bit Descriptions
EXC_ADD Register Bit Descriptions

PC	<63:2>RW	For precise exceptions, this is the address of the instruction that has not completed execution.  For imprecise exceptions, this is the PC value of the next instruction that would have issued if there were no exception/interrupt.  This address will be used to return from the exception or interrupt.
Ignore	<1>
PAL	<0>	This bit indicates PAL mode to the hardware.  When clear, the HW_REI instruction executes a jump to native (non-PAL) mode, enabling address translation.


Exception Summary Register (EXC_SUM)

Digital Alpha XL 300, 366, or 433 Registers

Exception Summary Register (EXC_SUM)

Address: IPR Ibox, Index=10C

This register contains various types of arithmetic traps that have occurred since the last time the register was written to (cleared).  Any write to the EXC_SUM register clears bits <08:02>.

Click on the Description button to display the bit fields.


EXC_SUM Bit Descriptions
EXC_SUM Register Bit Descriptions

IOV	<16>	If set, this bit indicates an F-box convert to integer overflow or integer arithmetic overflow.
INE	<15>	If set, this bit indicates a floating inexact error.
UNF	<14>	If set, this bit indicates a floating point underflow.
FOV	<13>	If set, this bit indicates a floating point overflow.
DZE	<12>	If set, this bit indicates a divide by zero.
INV	<11>	If set, this bit indicates an invalid operation.
SWC	<10>	If set, this bit indicates that software completion is possible.


Exception Mask Register (EXC_MASK)

Digital Alpha XL 300, 366, or 433 Registers

Exception Mask Register (EXC_MASK)

This register logs the destination register of an operation that has caused an arithmetic trap.  This will be valid on a machine check due to an arithmetic trap.


PAL Base Address Register (PAL_BASE)

Digital Alpha XL 300, 366, or 433 Registers

PAL Base Address Register (PAL_BASE)

Address: IPR Ibox, Index=10E

The PAL base address register is a read/write register containing the base address for the PALcode.


Interrupt Summary Register (ISR)

Digital Alpha XL 300, 366, or 433 Registers

Interrupt Summary Register (ISR)

Address: IPR Ibox, Index=100

The interrupt summary register is a read-only register that provides a record of all currently outstanding hardware, software, and asynchronous system trap (AST) interrupt requests and summary bits at the time of a read.

Click on the Description button to display the bit fields.


ISR Bit Descriptions
ISR Register Bit Descriptions

HLT	<34>R	External hardware interrupt - halt.
SLI	<33>R	Serial line interrupt request.
CRD	<32>R	Correctable read error interrupt request.
MCK	<31>R	External hardware interrupt - system machine check.
PFL	<30>R	External hardware interrupt - power fail.
PC2	<29>R	Performance counter 2 interrupt request.
PC1	<28>R	Performance counter 1 interrupt request.
PC0	<27>R	Performance counter 0 interrupt request.
I23	<23>R	External hardware interrupt - irq_h<3>.
I22	<22>R	External hardware interrupt - irq_h<2>.
I21	<21>R	External hardware interrupt - irq_h<1>.
I20	<20>R	External hardware interrupt - irq_h<0>.
ATR	<19>R	This bit is set if any AST request and corresponding enable is set.  This bit also requires that the processor mode is equal to or higher than the request mode.
SIRR<15:01>	<18:04>R	Corresponds to software interrupt requests 15 to 1.
ASTER and ASTRR	<03:00>R	Boolean AND of ASTRR<USEK> with ASTER<USEK> used to indicate enabled AST requests.


Instruction CSR (ICSR)

Digital Alpha XL 300, 366, or 433 Registers

Instruction Control and Status Register (ICSR)

Address: IPR Ibox-Index=118

This register contains various CPU instruction fetch/decode unit and branch unit (IDU) control and status information.

Click on the Description button to display the bit fields.


ICSR Bit Descriptions
ICSR Register Bit Descriptions

TST	<39>RW	Setting this bit asserts the test_status_h<1> signal.
ISTA	<38>RO	Reading this bit indicates Icache BIST status.  If set, the BIST was successful.
Reserved	<37>RW,1	Reserved to Digital. Must be one.
FBD	<36>RW	If set, forces bad Icache data parity.  MBZ in normal operation.
FBT	<35>RW	If set, forces bad Icache tag parity.  MBZ in normal operation.
FMS	<34>RW	If set, forces misses on Icache references.  MBZ in normal operation.
SLE	<33>RW	If set, enables serial line interrupts.
CRDE	<32>RW	If set, enables correctable error interrupts.
SDE	<30>RW	If set, enables the PAL shadow registers.
SPE<1:0>	<29:28>RW	If SPE<1> is set, it enables super-page mapping of I-stream virtual address VA<39:13> directly to physical PA<39:13>.  If SPE<0> is set (NT mode), it enables super-page mapping of Istream virtual addresses VA<42:30> = 1FFE directly to physical address PA<39:30> = 0.  VA<30:13> is mapped directly to PA<30:13>.
HWE	<27>RW	If set, allows PALRES instructions to be issued in kernel mode.
FPE	<26>RW	If set, floating point instructions may be issued.
TMD	<25>RW	If set, disables the IDU timeout counter.
TMM	<24>RW	If set, the timeout counter counts 5,000 cycles before asserting timeout reset.  If clear, the counter counts 1 billion cycles before asserting timeout reset.
IMSK<3:0>	<23:20>RW	If set, each IMSK<3:0> signal disables the corresponding irq_h<3:0> interrupt.
Reserved	<18>RW	Test mode bit, must be zero.
BSE	<17>RW	If set, enables support for byte and word data structures.
PME<1:0>	<09:08>RW	Performance counter master enable bits.  If both <1> and <0> are clear, all performance counters in the PMCTR IPR are disabled.  If either bit is set, the counter is enabled according to the settings of the PMCTR CTL fields.


Icache Parity Error Status Register (ICPERR_STAT)

Digital Alpha XL 300, 366, or 433 Registers

Icache Parity Error Status Register (IC_PERR_STAT)

Address: IPR Ibox, Index=11A

The Icache parity error status (ICPERR_STAT) register is a read/write register.  The Icache parity error status bits may be cleared by writing a 1 to the appropriate bits.

Click on the Description button to display the bit fields.


ICPERR_STAT Bit Descriptions
ICPERR_STAT Register Bit Descriptions

TMR	<13>RW	Timeout reset error.
TPE	<12>RW	Tag parity error.
DPE	<11>RW	Data parity error.


Dcache Parity Error Status Register (DC_PERR_STAT)

Digital Alpha XL 300, 366, or 433 Registers

Dcache Parity Error Status Register (DC_PERR_STAT)

Address: IPR Mbox, Index=212

The Dcache parity error status (DC_PERR_STAT) register is a read/write register.  If a Dcache parity error occurs while the DC_PERR_STAT is unlocked, the error status is loaded into <05:02>.  The lock bit is set and the register is locked against further updates (except for the SEO bit) until software writes a 1 to clear the lock bit.

Click on the Description button to display the bit fields.


DC_PERR_STAT Bit Descriptions
DC_PERR_STAT Register Bit Descriptions

TP1	<05>R	This bit indicates a tag parity error in Dcache bank 1.
TP0	<04>R	This bit indicates a tag parity error in Dcache bank 0.
DP1	<03>R	This bit indicates a data parity error in Dcache bank 1.
DP0	<02>R	This bit indicates a data parity error in Dcache bank 0.
LOCK	<01>RW	This bit is set if a parity error occurred in the Dcache.  Bits <05:02> are locked against further updates when this bit is set.
SEO	<00>RW	Second error occurred.  Set when an error that normally locks the DC_STAT register occurs while the DC_STAT register is locked already.


Virtual Address Register (VA)

Digital Alpha XL 300, 366, or 433 Registers

Virtual Address Register (VA)

Address: IPR Mbox, Index=206

The Virtual Address (VA) register latches the effective VA associated with D-stream faults, DTB misses, or Dcache parity errors.  The VA, VA_FORM, and MM_STAT are locked against further updates until the software reads the VA register.  The VA is a read-only register.


Dstream Memory Management Fault Status (MM_STAT)

Digital Alpha XL 300, 366, or 433 Registers

Dstream Memory Management Fault Status Register (MM_STAT)

Address: IPR Mbox, Index=205

The Dstream memory management fault status register is a read-only register that stores information about Dstream faults and Dcache parity errors.

Click on the Description button to display the bit fields.


MM_STAT Bit Descriptions
MM_STAT Register Bit Descriptions

OPCODE	<16:11>R	This field contains the opcode of the faulting instruction.
RA	<10:06>R	The RA field of the faulting instruction.
BAD_VA	<05>R	Set if reference had a bad virtual address.
DTB_MISS	<04>R	Set if reference resulted in a DTB miss.
FOW	<03>R	This bit is set if the reference was a write and the PTE's FOW bit was set.
FOR	<02>R	This bit is set if the reference was a read and the PTE's FOR bit was set.
ACV	<01>R	This bit is set if the reference caused an access violation.
WR	<00>R	This bit is set if a write reference caused the error.


SC_ADDR Register

Digital Alpha XL 300, 366, or 433 Registers

SC_ADDR Register

Address: IPR CBU, FF.FFF0.0188

The SC_ADDR register is a read-only register.  The address is loaded into this register every time the Scache is accessed if one of the bits in the SC_STAT register is not set.  If an Scache tag or data parity error is detected, then this register is locked until the SC_STAT is read.


Scache Status Register (SC_STAT)

Digital Alpha XL 300, 366, or 433 Registers

Scache Status Register (SC_STAT)

Address: IPR CBU, FF.FFF0.00E8

The Scache status (SC_STAT) register is a read-only register.  If an Scache tag or data parity error is detected during an Scache lookup, the SC_STAT is locked.  Any PALcode read of this register unlocks SC_ADDR and SC_STAT.

Click on the Description button to display the bit fields.


SC_STAT Bit Descriptions
SC_STAT Register Bit Descriptions

SC_SCND_ERR	<16>R	When set, this bit indicates that an Scache transaction resulted in a parity error while SC_TPERR or SC_DPERR was already set from an earlier transaction.
SC_CMD<4:0>	<15:11>R	This field indicates the Scache transaction that resulted in an Scache tag or data parity error. Source    Encoding <4:3>      <2:0>                Description   1x         110             Set shared from system.   1x         101             Read dirty from system.   1x         100             Invalidate from system.   1x         001             Scache victim.   00         001             Scache IREAD.   01         001             Scache DREAD.   01         011             Scache DWRITE.
SC_DPERR <7:0>	<10:03>R	When set, these bits indicate that an Scache read transaction resulted in a data parity error.  Each bit indicates that one or more bytes within a longword had the data parity error.
SC_TPERR <2:0>	<02:00>R	When set, these bits indicate that an Scache tag lookup resulted in a tag parity error, and they identify the set with the error.


Bcache Tag Address Register (BC_TAG_ADDR)

Digital Alpha XL 300, 366, or 433 Registers

Bcache Tag Address Register (BC_TAG_ADDR)

Address: IPR CBU, FF.FFF0.0108

The backup cache tag register is a read-only register.  Unless locked, the BC_TAG register is loaded with the results of every backup cache tag probe.  When a tag or tag control parity error occurs, this register is locked against further updates.  Software may read this register by using the 21164-specific I/O space address instruction.  The register is unlocked whenever the EI_STAT register is read, or the user enters BC_FHIT mode.  Unused tag bits in the TAG field of this register are always zero, based on the size of Bcache as determined by the BC_SIZE field in the BC_CONTROL register.

Click on the Description button to display the bit fields.


BC_TAG_ADDR Bit Descriptions
BC_TAG_ADDR Register Bit Descriptions

TAG<38:20>	<38:20>R	The backup cache tag field.
TAG_P	<17>R	Parity bit for the backup cache tag.
TAGCTL_V	<16>R	The tag valid bit.
TAGCTL_S	<15>R	The shared bit.  When clear, the entry is private.
TAGCTL_D	<14>R	The dirty bit.
TAGCTL_P	<13>R	Parity bit for the tag control bits.
HIT	<12>R	If set, the Bcache access resulted in a hit.


External Interface Address Register (EI_ADDR)

Digital Alpha XL 300, 366, or 433 Registers

External Interface Address Register (EI_ADDR)

Address: CBU, FF.FFF0.0148

The EI_ADDR register is a read-only register that contains the physical address associated with errors reported by EI_STAT.  The EI_ADDR register's contents are valid when one of the error bits is set.  A read of the EI_STAT register unlocks EI_ADDR.


Fill Syndrome Register (FILL_SYN)

Digital Alpha XL 300, 366, or 433 Registers

Fill Syndrome Register (FILL_SYN)

Address: IPR CBU, FF.FFF0.0068

FILL_SYN is a 16-bit read-only register.  It is loaded but not locked on a correctable ECC error, so that another correctable error does not reload it.  It is loaded and locked if an uncorrectable ECC error is detected during a fill from Bcache or main memory.  The FILL_SYN register is unlocked when the EI_STAT register is read.

If an ECC error is recognized during a cache fill operation, the syndrome bits associated with the bad quadword are loaded in the FILL_SYN register.  FILL_SYN<07:00> contains the syndrome associated with the lower quadword of the octaword.  FILL_SYN<15:08:> contains the syndrome associated with the higher quadword of the octaword.  A syndrome value of zero means that no errors were found in the associated quadword.

  Click here for a list of syndromes sorted by data bit.

  Click here for a list of syndromes sorted by syndrome bit.


External Interface Status Register (EI_STAT)

Digital Alpha XL 300, 366, or 433 Registers

External Interface Status Register (EI_STAT)

Address: IPR CBU, FF.FFF0.0168

The EI_STAT register is a read-only register.  Fill data from Bcache or main memory could have correctable or uncorrectable errors.  System address/command parity errors are treated as uncorrectable hard errors.  The register is locked on the first uncorrectable error.  The register bits are locked until the EI_STAT register is read.

Click on the Description button to display the bit fields.


EI_STAT Bit Descriptions
EI_STAT Register Bit Descriptions

SEO_HRD_ERR	<35>R	Set when an errors occurs while one of the error bits in this register is set already.
FIL_IRD	<34>R	When set, this bit indicates that the error occurred during an I-ref fill.  When clear, the error occurred during a D-ref fill.  This bit is meaningful only when an ECC error bit is set.
EI_PAR_ERR	<33>R	When set, an address/command received by the CPU had a parity error.
UNC_ECC_ERR	<32>R	When set, fill data received from outside the CPU contained an uncorrectable ECC error.
COR_ECC_ERR	<31>R	When set, fill data received from outside the CPU contained a correctable ECC error.
EI_ES	<30>R	When set, this bit indicates that the error source is fill data from main memory or a system address/command parity error. When clear, the error source is fill data from the Bcache.  This bit is meaningful only when COR_ECC_ERR, UNC_ECC_ERR, or EI_PAR_ERR is set.
BC_TC_PERR	<29>R	Indicates that a Bcache read transaction encountered bad parity in the tag control RAM.
BC_TPERR	<28>R	Indicates that a Bcache read transaction encountered bad parity in the tag address RAM.
CHIP_ID<3:0>	<27:24>R	Chip revision (currently, "4").


CIA Control Register (CIA_CTL)

Digital Alpha XL 300, 366, or 433 Registers

CIA Control Register (CIA_CTL)

Address: 87.4000.0100

The CIA Control register (CIA_CTRL) contains general control information for the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC).

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CIA_CTL Bit Descriptions
CIA_CTL Register Bit Descriptions

EN_DMA_ RD_PERF	<31>RW	When set to 1, the CIA enables the direct memory access (DMA) read performance logic.
Reserved	<30>R
RM_TYPE	<29:28>RW	This bit section controls the prefetch algorithm used for PCI-memory read-multiple commands. Value  Prefetch Algorithm 0 0       Short - fetch requested LW/QW and remainder              of cache block. 0 1       Medium - prefetch next block and no more. 1 0       Long - Keep prefetching until PCI transaction             completes. 1 1       Reserved
Reserved	<27:26>R
RL_TYPE	<25:24>RW	This bit section controls the prefetch algorithm used for PCI-memory read-line commands.  (See RM_TYPE field definition.)
Reserved	<23:22>R
RD_TYPE	<21:20>RW	This bit section controls the prefetch algorithm used for PCI-memory read commands.  (See RM_TYPE field definition.)
EN_ARB_LINK	<19>RW	When set to 1, CPU-memory read commands may link (share a common row-address select [RAS] strobe).
ARB_EV5_EN	<18>RW	When set to 1, the CIA enables the bypass path from CPU to the memory and I/O address queue.
IO_ FLUSHREQ_EN and CPU_ FLUSHREQ_EN	<17>RW <16>RW	Used in combination, this two-bit control determines the CIA's response to a PCI master signaling FLUSH_REQ. IO   CPU   Response  0      0      Assert MEM_ACK immediately.  0      1      Assert MEM_ACK immediately (don't                   allow new CPU commands to proceed.  1      0      Illegal  1      1      Wait until the IOA queue is empty,                    then assert MEM_ACK.
CSR_IOA_ BYPASS	<15>RW	When set to 1, the CIA bypasses the I/O address queue.
CON_IDLE_BC	<14>RW	When set to 1, the CIA verifies that unused B-cache (IDLE_BC) is contiguous.
ASSERT_ IDLE_BC	<13>RW	When set to 1, the CIA signals the IDLE_BC pin each time it signals the ADDR_BUS_REQ pin also.
ECC_CHK_EN	<12>RW	When set to 1, the CIA checks the input/output data (IOD).
MCHK_ERR_EN	<11>RW	When set to 1, signals the ERROR pin to report system machine-check conditions.
FILL_ERR_EN	<10>RW	When set to 1, the CIA issues FILL_ERROR if an error occurs during a CPU read-miss command.
PERR_EN	<09>RW	When set to 1, the CIA checks for PCI-data parity errors.
ADDR_PE_EN	<08>RW	When set to 1, the CIA checks for PCI-address parity errors.
PCI_ACK64_EN	<07>RW	When set to 1, the CIA accepts 64-bit PCI data transactions.
PCI_REQ64_EN	<06>RW	When set to 1, the CIA requests 64-bit PCI transactions.
PCI_MEM_EN	<05>RW	When set to 1, the CIA responds to PCI transactions.
PCI_MST_EN	<04>RW	When set to 1, the CIA initiates PCI transactions.
FST_BB_EN	<03>RW	When set to 1, the CIA initiates fast back-to-back PCI transactions.
PCI_LOOP_EN	<02>RW	When set to 1, the CIA responds as a target when it is the master.
PCI_LOCK_EN	<01>RW	When set to 1, this bit locks the CIA when specified by the PCI.
PCI_EN	<00>RW	When set to 0, CIA is resetting the PCI bus


Hardware Address Extension Register (HAE_MEM)

Digital Alpha XL 300, 366, or 433 Registers

Hardware Address Extension Register (HAE_MEM)

Address: 87.4000.0400

The Hardware Address Extension Sparse Memory register (HAE_MEM) allows the extension of a PCI sparse-space memory address up to the 32-bit PCI address limit.  The CPU address provides the low-order PCI address bits.  The high-order PCI address bits (31 through 26) are provided either by this register or by the CPU address, depending on the sparse-space region.  Initializing this register to 0000.2028 makes all three regions contiguous starting at PCI address 0.


Hardware Address Extension Register (HAE_IO)

Digital Alpha XL 300, 366, or 433 Registers

Hardware Address Extension Register (HAE_IO)

Address: 87.4000.0440

The Hardware Address Extension register (HAE_IO) is used to extend a PCI Sparse-space I/O address up to the full 32-bit PCI address limit.  In Sparse-space addressing mode, the CPU address provides the low-order PCI address bits (through bit 24).  The high-order PCI address bits (25 through 31) are provided by this register.  Setting this register to 0200.0000 Hex makes region A and region B consecutive in the lower 64 MB of PCI I/O space.


Configuration Type Register (CFG)

Digital Alpha XL 300, 366, or 433 Registers

Configuration Type Register (CFG)

Address: 87.4000.0480

The CFG field bits are used as the low two address bits when accessing the PCI configuration space.

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CFG Bit Descriptions
CFG Register Bit Descriptions

CFG<1:0>	<1:0>RW	PCI configuration space access type: CFG<1:0>    Meaning   0   0           Type 0 configuration cycle   0   1           Type 1 configuration cycle   1   x           Reserved
Reserved	<31:02>R


CIA Acknowledgement Control Register (CACK_EN)

Digital Alpha XL 300, 366, or 433 Registers

CIA Acknowledgement Control Register (CACK_EN)

Address: 87.4000.0600

The CIA acknowledgment enable register allows software to decide if the CIA will acknowledge receipt of any of four particular commands from the CPU or to ignore any of these commands.

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CACK_EN Bit Descriptions
CACK_EN Register Bit Descriptions

Reserved	<31:04>R
BC_VICTIM_EN	<03>RW	When set, enables the CIA to acknowledge receipt of a BC_VICTIM command from the CPU.
SET_DIRTY_EN	<02>RW	When set, enables the CIA to acknowledge receipt of a SET DIRTY command from the CPU.
MB_EN	<01>RW	When set, enables the CIA to acknowledge receipt of an MB command from the CPU.
LOCK_EN	<00>RW	When set, enables the CIA to acknowledge receipt of a lock command from the CPU.


CPU Error Information Register 0 (CPU_ERR0)

Digital Alpha XL 300, 366, or 433 Registers

CPU Error Information Register 0 (CPU_ERR0)

Address: 87.4000.8000

The low-order address bits of the sysBus are locked into this register when the CIA detects an error event.  Clearing all the error bits in CIA_ERR unlocks this register.  When CPU_ERR0 is not locked, its contents are undefined.  The information in this register and CPU_ERR1 is only related to sysBus parity errors detected by the CIA.

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CPU_ERR0 Bit Descriptions
CPU_ERR0 Register Bit Descriptions

ADDR_H<31:4>	<31:04>R	Contains address bits <31:4> of the current address on the sysBus when a sysBus error occurs.
Reserved	<3:0>R


CPU Error Information Register 1 (CPU_ERR1)

Digital Alpha XL 300, 366, or 433 Registers

CPU Error Information Register 1 (CPU_ERR1)

Address: 87.4000.8040

The mask and command field and the remaining address field on the sysBus are locked into CPU_ERR1 when the CIA detects an error event.  Clearing all the error bits in CIA_ERR unlocks this register.  When CPU_ERR1 is not locked, its contents are undefined.  The information in this register and CPU_ERR0 is only related to sysBus parity errors detected by the CIA.

Click on the Description button to display the bit fields.


CPU_ERR1 Bit Descriptions
CPU_ERR1 Register Bit Descriptions

CPU_PE	<31>R	When set, indicates that the CIA has logged a sysBus error.
FPE_2_CPU	<30>R	Contains a copy of the CSR bit to force bad parity on the sysBus.
Reserved	<29:22>R
ADDR_CMD_PAR	<21>R	Contains the parity bit from the sysBus.
Reserved	<20:16>R
INT4_VALID	<15:12>R	Contains int4_valid_h<3:0> from the sysBus.
CMD	<11:8>R	Contains the command from the sysBus.
ADDR<39>	<7>R	Contains addr_h<39> from the sysBus.
Reserved	<6:3>R
ADDR<34:32>	<2:0>R	Contains addr_h<34:32> from the sysBus.


CIA Error Register (CIA_ERR)

Digital Alpha XL 300, 366, or 433 Registers

CIA Error Register (CIA_ERR)

Address: 87.4000.8200

The CIA error register is used by the CIA to log information about an error condition detected in the CIA.  All bits of CIA_ERR, except the LOST bit, will be locked until the CIA_ERR register is cleared by a write transaction.  The LOST bit is set whenever an error is detected and CIA_ERR is already locked.

Click on the Description button to display the bit fields.


CIA_ERR Bit Descriptions
CIA_ERR Register Bit Descriptions

ERR_VALID	<31>R	An error has been detected, and the CIA_ERR register is locked.
Reserved	<30:28>R
LOST_IOA_TIMEOUT	<27>R	An I/O timeout occurred while the CIA_ERR was locked.
LOST_FROM_WRT_ERR	<26>R	A write transaction to flashROM was attempted with CIA_DIAG:<FROM_WRT_EN> clear while the CIA was locked.
LOST_PA_PTE_INV	<25>R	An invalid PTE on scatter/gather access occurred while the CIA was locked.
LOST_RCVD_TAR_ABT	<24>R	The PCI master state machine received a target abort while the CIA was locked.
LOST_RCVD_MAS_ABT	<23>R	The PCI master state machine generated a master abort while the CIA was locked.
LOST_PCI_ADDR_PE	<22>R	A PCI address parity error was detected while the CIA was locked.
LOST_PERR	<21>R	A PCI data parity error was detected while the CIA was locked.
Reserved	<20>R
LOST_MEM_NEM	<19>R	An access to nonexistent memory was detected while the CIA was locked.
LOST_CPU_PE	<18>R	A sysBus parity error was detected while the CIA was locked.
LOST_UN_COR_ERR	<17>R	An uncorrectable error was detected while the CIA was locked.
LOST_COR_ERR	<16>R	A corrected error was detected while the CIA was locked.
Reserved	<15:12>R
IOA_TIMEOUT	<11>RW1C	I/O timeout occurred (I/O read/write transaction failed to complete in one second).
FROM_WRT_ERR	<10>RW1C	Write to flashROM attempted without setting CIA_DIAG:<FROM_WRT_EN>.
PA_PTE_INV	<9>RW1C	Invalid PTE on scatter/gather access.
RCVD_TAR_ABT	<8>RW1C	PCI master state machine received a target abort.
RCVD_MAS_ABT	<7>RW1C	PCI master state machine generated a master abort.
PCI_ADDR_PE	<6>RW1C	PCI bus address parity error detected.
PERR	<5>RW1C	PCI bus data parity error (PERR) detected.
PCI_SERR	<4>RW1C	PCI bus system error (SERR) detected.
MEM_NEM	<3>RW1C	Access to nonexistent memory detected.
CPU_PE	<2>RW1C	A sysBus parity error was detected.
UN_COR_ERR	<1>RW1C	The CIA detected an uncorrectable error.  This error applies only to DMA transactions, scatter/gather TLB misses, or I/O writes from the CPU.  (This error does not apply to CPU-to-memory reads [the CPU detects such errors]; nor does it apply to CPU-to-memory writes because they are not checked.)
COR_ERR	<0>RW1C	The CIA detected a corrected error.  This error applies only to DMA transactions, scatter/gather TLB misses, or I/O writes from the CPU.  (This error does not apply to CPU-to-memory reads [the CPU detects such errors]; nor does it apply to CPU-to-memory writes, because they are not checked.)


CIA Status Register (CIA_STAT)

Digital Alpha XL 300, 366, or 433 Registers

CIA Status Register (CIA_STAT)

Address: 87.4000.8240

Click on the Description button to display the bit fields.


CIA_STAT Bit Descriptions
CIA Status Register Bit Descriptions

Reserved	<31:18>
PA_CPU_RES <1:0>	<17:16>	CPU responses for the DMA: 00 = No response 01 = NOACK 10 = Scache hit 11 = Bcache hit
DM_ST<3:0>	<15:12>	This field represents the state of the logic that moves data between the CIA and the data slices (DSW). DM_ST<3:0>    Definition     0000           Idle     0001           Restarting DSW IOW buffers     0010           I/O write to the 64-bit PCI bus     0110           DMA read or TLB miss     0111           DMA write     1010           I/O read to an internal CIA CSR     1011           I/O read to the PCI bus
TLB_MISS	<11>	When set, a TLB miss refill was in progress when the error occurred.
CPU_QUEUE <2:0>	<10:8>	Valid bits for the CPU command/address queue.
IOA_VALID <3:0>	<7:4>	Valid bits for the I/O command/address queue.
MEM_SOURCE	<3>	When set, the PCI is the source of the memory cycle.  When clear, the CPU is the source of the memory cycle.
Reserved	<2>
PCI_STATUS <1>	<1>	When set, the PCI master state machine is active.
PCI_STATUS <0>	<0>	When set, the PCI target state machine is active.


CIA Error Mask Register (ERR_MASK)

Digital Alpha XL 300, 366, or 433 Registers

CIA Error Mask Register (ERR_MASK)

Address: 87.4000.8280

ERR_MASK is used to disable the logging and reporting of errors.  A zero disables and a one enables the logging/reporting of errors.

Click on the Description button to display the bit fields.


ERR_MASK Register Bit Descriptions
CIA Error Mask Register Bit Descriptions

Reserved	<31:12>R
IOA_TIMEOUT	<11>RW	Disable/enable error logging/reporting for I/O timeout errors.
FROM_WRT_ERR	<10>RW	Disable/enable error logging/reporting for flashROM write errors.
PA_PTE_INV	<9>RW	Disable/enable error logging/reporting for invalid PTE errors.
RCVD_TAR_ABT	<8>RW	Disable/enable error logging/reporting for PCI target abort errors.
RCVD_MAS_ABT	<7>RW	Disable/enable error logging/reporting for PCI master abort errors.
PCI_ADDR_PE	<6>RW	Disable/enable error logging/reporting for PCI bus address parity errors.
PERR	<5>RW	Disable/enable error logging/reporting for PCI bus data parity errors.
PCI_SERR	<4>RW	Disable/enable error logging/reporting for PCI bus system errors.
MEM_NEM	<3>RW	Disable/enable error logging/reporting for nonexistent memory errors.
CPU_PE	<2>RW	Disable/enable error logging/reporting for sysBus parity errors.
UN_COR_ERR	<1>RW	Disable/enable error logging/reporting for uncorrectable errors.
COR_ERR	<0>RW	Disable/enable error logging/reporting for corrected errors.


CIA Error Syndrome Register (CIA_SYN)

Digital Alpha XL 300, 366, or 433 Registers

CIA Error Syndrome Register (CIA_SYN)

Address: 87.4000.8300

The CIA uses CIA_SYN to log syndrome information about an error detected by the ECC checkers.  The syndrome information is locked into CIA_SYN when a CIA error occurs.  Clearing all the error bits in CIA_ERR unlocks this register.  When CIA_SYN is not locked, its contents are undefined.

  Click here for a list of syndromes sorted by data bit.

  Click here for a list of syndromes sorted by syndrome bit.


CIA Memory Port Status Register 0 (MEM_ERR0)

Digital Alpha XL 300, 366, or 433 Registers

CIA Memory Port Status Register 0 (MEM_ERR0)

Address: 87.4000.8400

The low-order address bits (MEM_PORT_ADDR<31:4>) of the current memory port address locked into MEM_ERR0 when the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are undefined.


CIA Memory Port Status Register 1 (MEM_ERR1)

Digital Alpha XL 300, 366, or 433 Registers

CIA Memory Port Status Register 1 (MEM_ERR1)

Address: 87.4000.8440

The command memory mask (int4_valid<3:0> from the CPU), memory sequencer state, the source of the command, encoded set select field, and the remaining bits of the address field are locked into MEM_ERR1 when the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are undefined.

Click on the Description button to display the bit fields.


MEM_ERR1 Bit Descriptions
MEM_ERR1 Register Bit Descriptions

Reserved	<31:29>R
SET_SEL_ENC	<28:24>RW	Encoded set select indicates which memory set was active when the error occurred. 00000-01111 Set 0-F selected 10000              No set selected 11111              Refresh cycle All other codes reserved.
Reserved	<23:21>R
MEM_PORT_SOURCE	<20>RW	Source of the memory command: 1 = CPU, 0 = DMA
SEQ_ST	<19:16>RW	The memory sequencer state when the error occurred. SEQ_ST              Description 0000                        Idle 0001                        DMA read or write 0010,0011             CPU read miss with victim 0100,0101,0110    CPU read miss (no victim) 0111,1000,1001    Refresh 1100                      Idle (waiting for DMA                                pending read) 1110,1111             Idle, ras_h precharge
MEM_PORT_MASK	<15:12>RW	The mask bits when the error occurred.
MEM_PORT_CMD	<11:8>R	Contains the command field of the memory port when the CIA detected an error. SOURCE COMMAND    Description   <20>        <11:8>     0        011x     CPU Write block (or lock)     0        10xx     CPU read miss (or modify)     0        1100     CPU BC_VICTIM     0        111x     CPU Read miss modify     1        10xx     DMA read or read modify     1        001x     DMA write
MEM_PORT_ADDR <39>	<7>RW	Captures memory port address bit <39> when the CIA detects an error.
Reserved	<6:2>R
MEM_PORT_ADDR <33:32>	<1:0>R	Captures memory port address bits <33:32> when the CIA detects an error.


PCI Error Address Register 0 (PCI_ERR0)

Digital Alpha XL 300, 366, or 433 Registers

PCI Error Register 0 (PCI_ERR0)

Address: 87.4000.8800

PCI_ERR0 is used by the CIA to log information about the state of the PCI interface when an error is detected by the CIA.  PCI_ERR0 is locked when the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are undefined.

The data in the WINDOW, DMA_DAC, and DMA_CMD fields is associated with the address stored in PCI_ERR1.  This group and PCI_ERR1 hold information related to memory errors that occurred while the CIA is handling a DMA transaction.

Click on the Description button to display the bit fields.


PCI_ERR0 Bit Descriptions
PCI_ERR0 Register Bit Descriptions

Reserved	<31:29>R
PCI_DAC	<28>R	If set, the current PCI command is a dual address cycle (DAC) command.
PCI_CMD	<27:24>R	The current PCI command.
Reserved	<23>R
TARGET_STATE	<22:20>R	0 = Idle                                       4 = Read stop cycle 1 = Busy                                     5 = Write stop cycle 2 = Read data cycle              6 = Read turnaround 3 = Write data cycle               7 = Write turnaround
MASTER_STATE	<19:16>R	0 = Idle                                         7 = Read stop cycle 1 = Drive bus                             8 = Write stop cycle 2 = Address step cycle         9 = Read turnaround 3 = Address cycle                  A = Write turnaround 4 = Data cycle                          B - E = Reserved 5 = Last read data cycle        F = Unknown state 6 = Last write data cycle
Reserved	<15:12>R
WINDOW	<11:8>R	Indicate which window, if any, was selected by a PCI address. WINDOW<3:0>        Window Selected 0000                               No window active 0001                               Window 0 hit 0010                               Window 1 hit 0100                               Window 2 hit 1000                               Window 3 hit
Reserved	<7:6>R
DMA_DAC	<5>R	If set, the error occurred during a PCI dual address cycle (DAC).
LOCK_STATE	<4>R	If set, the CIA was locked when the error was detected.
DMA_CMD	<3:0>R	The current DMA command on the PCI.


PCI Error Address Register 1 (PCI_ERR1)

Digital Alpha XL 300, 366, or 433 Registers

PCI Error Register 1 (PCI_ERR1)

Address: 87.4000.8840

This register always captures ad_h<31:0>, even for a DMA DAC cycle.  This register is locked whenever the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are unpredictable.

PCI_ERR1 and some fields in PCI_ERR0 (WINDOW, DMA_DAC, and DMA_CMD) hold information related to memory errors that occurred while the CIA is handling a DMA transaction.

The CIA uses PCI_ERR1 to log DMA ad_h<31:0> when an error condition is logged in PCI_ERR0.  This register always captures ad_h<31:0>, even for a DMA DAC cycle.  This register is locked whenever the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are unpredictable.

PCI_ERR1 and some fields in PCI_ERR0 (WINDOW, DMA_DAC, and DMA_CMD) hold information related to memory errors that occurred while the CIA is handling a DMA transaction.


PCI Error Address Register 2 (PCI_ERR2)

Digital Alpha XL 300, 366, or 433 Registers

PCI Error Register 2 (PCI_ERR2)

Address: 87.4000.8880

The CIA uses PCI_ERR2 to log ad_h<31:0> when an error condition is logged into PCI_ERR0.  This register always captures ad_h<31:0>, even for a DMA DAC cycle.  This register is locked whenever the CIA detects an error.  Clearing all the error bits in CIA_ERR unlocks this register.  If the register is not locked, the contents are unpredictable.

PCI_ERR2 and some fields in PCI_ERR0 (PCI_DAC, PCI_CMD, TARGET_STATE, and MASTER_STATE) hold information related to parity errors, master and target aborts, and IOA timeouts that are associated with the PCI bus.


Memory Configuration Register (MCR)

Digital Alpha XL 300, 366, or 433 Registers

Memory Configuration Register (MCR)

Address: 87.5000.0000

The MCR register defines the system Bcache and memory configuration.  The register contents are used to configure the CIA memory controller.

Click on the Description button to display the bit fields.


MCR Register Bit Descriptions

Reserved	<31:30>R
EARLY_IDLE_BC	<29>RW	Write only a one to this bit.  (A zero may cause upredictable behavior.)
Reserved	<28>R
DLY_IDLE_BC	<27:26>RW	Write only 00 to this field.  (Any other value may cause upredictable behavior.)
Reserved	<25:23>R
LONG_CBR_CAS	<22>RW	Refresh (cas_h before ras_h) cas_h pulse width: 0 - pulse width = 60ns. 1 - pulse width = 90ns.
TMG_R0	<21:20>RW	Controls the row address nominal setup time. 00 - 15ns. 01 - 30ns. 10 - 45ns. 11 - 60ns.
REF_BURST	<19:18>RW	The refresh state machine can be set up to perform all or half the SIMMs at once and also to do one or two refreshes when the REF_RATE counter rolls over. 00 - ras_h to all SIMMs at once, single refresh 01 - ras_h to all SIMMs at once, double refresh 10 - ras_h to half of SIMMs at once, single refresh 11 - ras_h to half of SIMMs at once, double refresh
REF_RATE	<17:8>RW	This field controls the memory refresh rate. A 10-bit free-running counter, starting at zero, counts up to the REF_RATE and resets to zero.  Memory is refreshed every time the REF_RATE value is reached.  Setting this field to zero disables refresh cycles.
Reserved	<7>R
CACHE_SIZE	<6:4>RW	SROM code determines the cache size and writes these bits before any memory cycles are started. 000          No cache present 001          Reserved 010          128K * X, 2 MB - complete cache 011          256K * X, 4 MB or larger - complete cache 100-111  Reserved
Reserved	<3:1>R
MEM_SIZE	<0>RW	If clear, the memory port is configured to a 128-bit data path.  If set, the memory port is configured to a 256-bit data path


Memory Base Address Registers (MBA0 and MBA2)

Digital Alpha XL 300, 366, or 433 Registers

Memory Base Address Registers (MBA0/2)

Bank 0 Address: MBA0 - 87.5000.0600
Bank 1 Address: MBA2 - 87.5000.0680

There are eight memory base registers.  Two are used in the Alpha XL 300 and 366 system.  The bits within the MBA register provide a pattern that is compared with the incoming address to determine which bank is being accessed.  The minimum bank size for an MBA register is 16 MB.

Click on the Description button to display the bit fields.


MBA0/2 Registers Bit Descriptions
MBA0/2 Register Bit Descriptions

Reserved	<31:30>R
TMG_SEL	<29:28>RW	Timing register select. 00    Use TMG0 (for 50 and 60ns SIMMs) 01    Use TMG1 (for 70ns SIMMs) 10    Use TMG2 (for 80ns SIMMs) 11    Reserved
Reserved	<27:26>R
PATTERN	<25:16>RW	The pattern is compared with the incoming sysBus address addr_h<33:24> and then ORed with MASK<8:4> to determine if the bank corresponding to this MBA is being accessed.  PATTERN indicates the base address of the memory bank whereas MASK indicates the size of the bank.
S1_VALID	<15>RW	If set, this bit indicates that side 1 for the bank is valid.  Side 1 cannot be valid unless side 0 is also valid.
Reserved	<14:9>R
MASK	<8:4>RW	Indicates the bits to use when comparing MBAn:<PATTERN> with the physical address.  The MASK field implicitly indicates the size of the memory SIMMs in the bank corresponding to the MBA register
Reserved	<3>R
ROW_TYPE	<2:1>RW	Specifies the row and column configuration of the physical bank being referenced.  ROW_TYPE is used for generating the memory address map. 00    10 row/10 column 01    12 row/10 column or 11 x 11 10    13 row/11 column or 12 x 12 11    Reserved
S0_VALID	<0>RW	If set, this bit indicates that side 0 for the bank is valid.


Memory Timing Registers (TMG0, TMG1, TMG2)

Digital Alpha XL 300, 366, or 433 Registers

Memory Timing Registers (TMG0/2)

TMG0 Address: 87.5000.0B00

TMG1 Address: 87.5000.0B40

TMG2 Address: 87.5000.0B80

There are three memory-timing information registers.  The memory-timing registers contain the system parameters that control the operation of the CIA sequencer.  The MBA0/2:<29:28> selects the TMG register to be used.

Click on the Description button to display the bit fields.


Scatter/Gather Translation Buffer Invalidate Register (TBIA)

Digital Alpha XL 300, 366, or 433 Registers

Scatter/Gather Translation Buffer Invalidate Register (TBIA)

Address: 87.6000.0100

The TBIA register is a write-only register.  A write to this register causes the specified group of scatter/gather TLB tags to be unlocked and marked invalid.


TBIA Register Bit Descriptions

Reserved	<31:2>R
TBIA<1:0>	<1:0>W	00    No operation. 01    Invalidate and unlock the TLB tags that           are currently locked. 10    Invalidate the TLB tags that are currently          unlocked. 11    Invalidate and unlock all TLK tags.


Window Base Registers 0, 1, 2 and 3 (Wx_BASE, x=0-3)

Digital Alpha XL 300, 366, or 433 Registers

Window Base Registers 0-3 (Wx_BASE, x-0-3)

0. Address: 87.6000.0400

1. Address: 87.6000.0500

2. Address: 87.6000.0600

3. Address: 87.6000.0700

There are four window base registers, each providing the base address for a particular target window.  The incoming PCI address bits <31:20> are compared with each of the four window base registers to determine if a hit occurs in the target window.  The window mask register contents determine which bits are involved in the comparison.

The target window is hit when the masked addresses match a valid window base register.

Click on the Description button to display the bit fields.


Wx_BASE Register Bit Descriptions
Wx_BASE (x=0-3) Register Bit Descriptions

W_BASE	<31:20>RW	Specifies the PCI base address of the PCI target window and is used to determine a hit in the target window.
Reserved	<19:4>R
DAC_ENABLE	<3>RW	Only in W3_BASE.  If set, W_DAC is compared with the PCI address bits <39:32> for a PCI DAC cycle.  If the compare is a hit and the 32-bit portion of the PCI address is also hit, then a DAC cycle hit occurs.
MEMCS_ENABLE	<2>RW	Only in W0_BASE.  If set, the MEMCS signal from the PCI-to-ISA bridge is ANDed with the normal window hit.
Wn_BASE_SG	<1>RW	If clear, the PCI target window uses direct mapping to translate a PCI address to a CPU address. If set, the PCI target window uses scatter/gather mapping to translate a PCI address to a physical memory address.
W_EN	<0>RW	If clear, the PCI target window is disabled and will not be used to respond to PCI_initiated transfers. If set, the PCI target window is enabled and is used to respond to PCI-initiated transfers that hit in the address range of the target window.


Window Mask Registers 0, 1, 2, and 3 (Wx_MASK, 0-3)

Digital Alpha XL 300, 366, or 433 Registers

Window Mask Registers 0, 1, 2, and 3 (Wx_MASK, x=0-3)

0. Address: 87.6000.0440

1. Address: 87.6000.0540

2. Address: 87.6000.0640

3. Address: 87.6000.0740

The window mask registers provide a mask corresponding to ad<31:20> of an incoming PCI address.  The size of each window can be programmed to be from 1 MB to 4 GB in powers of 2 by masking bits.

There are four window mask registers.  The incoming PCI address bits <31:20> are compared with each of the four window base registers to determine a hit in the target window.  The window mask register contents determine which bits are involved in the comparision.  The target window is hit when the masked addresses match a valid window base register.

Click on the Description button to display the bit fields.


Wx_MASK Register Bit Descriptions
Wx_MASK (x=0-3) Register Bit Descriptions

W_MASK	<31:20>RW	This field specifies the size of the PCI target window.  It is also used to mask out address bits not used when determining a PCI target window hit. 0000 0000 0000            1 MB 0000 0000 0001            2 MB 0000 0000 0011            4 MB 0000 0000 0111            8 MB 0000 0000 1111            16 MB 0000 0001 1111            32 MB 0000 0011 1111            64 MB 0000 0111 1111            128 MB 0000 1111 1111            256 MB 0001 1111 1111            512 MB 0011 1111 1111            1 GB 0111 1111 1111            2 GB 1111 1111 1111            4 GB Other combinations   Not supported
Reserved	<19:0>R


Translated Base Registers 0, 1, 2, and 3 (Tx_BASE, x=0-3)

Digital Alpha XL 300, 366, or 433 Registers

Translated Base Registers 0, 1, 2, and 3 (Tx_BASE, x=0-3)

0. Address: 87.6000.0480

1. Address: 87.6000.0580

2. Address: 87.6000.0680

3. Address: 87.6000.0780

There are four translated base registers, one for each window.  They are used to map PCI addresses into memory addresses.  If the scatter/gather bit of the window base register is set, the Tx_BASE provides the base address of the scatter/gather map for this window.  If the scatter/gather bit is clear, the Tx_BASE provides the physical address of this window.


Window DAC Base Register (W_DAC)

Digital Alpha XL 300, 366, or 433 Registers

Window DAC Base Register (W_DAC)

Address: 87.6000.07C0

W_DAC provides DAC_BASE<7:0> for comparision against PCI address bits <39:32> during a DAC cycle.  PCI address bits <63:40> must be zero for a PCI window hit.  This register is used with W3_BASE.


Console Commands

Digital Alpha XL 300, 366, or 433

AlphaBIOS Firmware

The Digital Alpha XL system contains the AlphaBIOS console firmware.  AlphaBIOS supports the Microsoft Windows NT operating system.

The console firmware resides in 512 KB of flashROM on the CPU module.  The firmware flashROMs can be updated in the field.

AlphaBIOS firmware console

Updating the Firmware

Preparing the disk for a Windows NT Installation

Starting a Windows NT Version 3.51 Installation

Starting a Windows NT Version 4.0 Installation


AlphaBIOS Commands

Digital Alpha XL 300, 366, or 433 ARC Firmware Console

AlphaBIOS Commands

AlphaBIOS features an easy-to-use menu interface.  It is intuitively designed and straightforward to use.
When the system is powered on and POST successfully completes, AlphaBIOS is loaded from the flashROM and started.

Several initialization tasks are performed.

Click on the operating system list for boot information.
Click on Press <F2> to enter SETUP for AlphaBIOS Setup information.


AlphaBIOS Initialization Tasks

The initialization tasks performed by AlphaBIOS include:

  Initialize the keyboard and video devices.

  Test memory.

  Detect and initialize the SCSI disk controllers.

After the video device is initialized, subsequent steps are displayed on the monitor in an initialization window.  When the SCSI initialization is complete, AlphaBIOS leaves the initialization window and displays the boot screen shown here.


Booting the Operating System

The boot screen lists each Windows NT operating system that has been set up on the system.  Use the OS Selection Setup utility to modify the list.  Start OS Selection by selecting it from the Utilities menu in the AlphaBIOS Setup screen.

When a particular copy of Windows NT is selected, AlphaBIOS starts the two-stage boot process:

First stage - AlphaBIOS reads the OS Loader program (OSLOADER.EXE in Windows NT 3.51) from the path described by the selection.  The OS Loader program must be located in a FAT-formatted partition.

Second stage - the OS Loader program starts.  It uses AlphaBIOS services to load the operating system components.  Once the components are loaded, the OS Loader starts the operating system.


AlphaBIOS Setup Screen

Digital Alpha XL Console Commands

AlphaBIOS Setup Screen

AlphaBIOS Setup is used to perform several system configurations tasks.
Click on the screen for task descriptions.
Click on ESC=Exit for the AlphaBIOS boot screen.


Display System Configuration

The Display System Configuration screen provides detailed information about the CPU, memory, attached devices, and option boards.  The information is divided into six configuration categories:

Category	Contents
System board	System type, processor, CPU speed, cache, memory size, floppy drives, keyboard, and AlphaBIOS version.
Memory	Memory size and starting address by bank.
Hard disk	Physical disk ID, controller, controller ID, raw disk size, SCSI ID, and partition maps.
PCI	Device names and types, revision levels, and slots.  Press Enter for PCI device detail.
SCSI	SCSI controller information and a list of SCSI devices.
Integrated peripherals	I/O address and IRQ information about COM1, COM2, and the parallel port.


Upgrading AlphaBIOS

The Upgrade AlphaBIOS selection is used to install newer releases of the AlphaBIOS firmware into the system flashROM.

Prior to selecting this choice, insert the firmware update media into the appropriate device (typically, a floppy or CD-ROM drive).

CAUTION: Check the revision level of the currently installed firmware and the firmware on the update media before selecting this command.  An unexpected firmware downgrade may introduce compatibility problems.


Hard Disk Setup

The Hard Disk Setup selection is used to create and delete disk partitions and format the disks.

An Express option is available to set up the first hard disk with the recommended default partition arrangement.

Partition 1 is the drive size minus 6 MB.  This partition typically is NTFS-formatted during the Windows NT installation.

Partition 2 is 6 MB, FAT-formatted.  This is the system partition.

NOTE:  You can convert a FAT formatted disk to NTFS from the DOS Command Window with the following command:  CONVERT drive:/FS:NTFS where drive is not the current drive.


AlphaBIOS CMOS Setup Screen

Digital Alpha XL Console Commands

CMOS Setup Screen

The CMOS Setup screen is used to perform basic system configurations tasks.
Click on the screen for task descriptions.
Click on ESC=Discard Changes for the AlphaBIOS Setup screen.


Install Windows NT

Prior to selecting this choice, insert the Windows NT distribution CD-ROM into the CD drive.  When selected, the AlphaBIOS firmware will start installing the Windows NT system.  Screen displays will appear to guide you through the installation.

If this is the first time Windows NT is being installed on the system, use CMOS Setup to set the system date and time before starting the installation and Hard Disk Setup to partition and format a disk.


Utilities

The Utilities submenu contains two choices:

OS System Selection - used to set up the operating system selections.  The utility provides an interface to enter, modify, and validate the various pointers to a particular operating system's directory path and the disk and partition containing OSLOADER.EXE.

Run a maintenance program - allows the running of programs such as RAID configuration utilities.


About AlphaBIOS

This About AlphaBIOS selection displays version information.


F1 Help

There are two levels of keyboard help available.  Pressing F1 once displays explanations of the keystrokes available for the specific part of AlphaBIOS currently displayed.

Pressing F1 twice displays explanations of the keystrokes available for navigating the AlphaBIOS interface.


Set System Time
Set System Date and Time

Selecting this choice allows you to enter the date and time.  Use a 24-hour format for the time.


Set Floppy Drive and Keyboard Configuration

Selecting these choices allows you to enter configuration information about the floppy drive(s) and the keyboard.

The keyboard setting makes it possible to use keyboards for different languages.  To ensure correct character mappings, the language of the keyboard, the Windows NT system, and the keyboard language selection should all match.


Context Help Display

This message box displays information pertaining to the currently selected operation.


Setting the Display Color

Pressing the F3 key repeatedly cycles through the available AlphaBIOS color schemes.


CMOS Setup Defaults

Pressing the F7 key restores the standard CMOS setup default values.  The advanced CMOS setup values are not affected.


Save CMOS Setup Changes

Pressing the F10 key saves the changes made in both the standard and advanced modes of CMOS setup.

Pressing the Escape key restores the settings in effect when CMOS Setup was started.  This option also discards any changes made in advanced CMOS setup.


Advanced CMOS Setup Screen

Digital Alpha XL Console Commands

Advanced CMOS Setup Screen

Advanced CMOS Setup is used to set system-specific parameters and password protection.

Click on the ESC key to return to the CMOS Setup screen.


Setting up Auto Start
Auto Start

Auto Start determines whether the primary operating system is  started automatically after the system is reset or power cycled.  The Auto Start Count setting is the delay in seconds from the time the boot screen is displayed until the system is booted.  To stop the countdown, press a down arrow to stay at the boot screen or press the F2 key to enter CMOS Setup.


PCI Parity Checking

The PCI Parity Checking setting controls parity testing at the PCI bridge chip.  Use caution when making this selection.  It allows you to turn PCI parity checking on and off.  The new value becomes effective after an init or power cycle. See Disabling PCI Parity for more information.


Power-up Memory Test

Use this feature to enable or disable the power-up memory test.  When enabled, the memory test writes and reads patterns of data to main memory.


Password Setup

Use this feature to enable and disable two levels of security: setup protection and startup protection.

Setup:  When enabled, a password is required to start AlphaBIOS Setup.

Startup: When enabled, a password is required before the system initializes.

Startup protection provides more comprehensive protection than setup protection because the system cannot be used at all until you enter the correct password.

If the user forgets the password, there is no easy method to erase the password.  After all, that would defeat the idea of having a password.  The motherboard must be replaced to get around the forgotten password.


SCSI Termination

The SCSI termination feature is not supported on the Alpha XL sysyem.  The SCSI bus must be  properly terminated internally, and if the automatic termination sensing is disabled, externally with the appropriate terminator plugs.  If the automatic termination feature is enabled and no external SCSI devices are present, the bus will be terminated.  If external devices are present, proper termination must be provided by the last external device.


Updating the AlphaBIOS Firmware

Digital Alpha XL 300, 366, or 433 ARC Firmware Console

Updating the AlphaBIOS Firmware

The following procedure describes how to update the AlphaBIOS Firmware.  The AlphaBIOS Firmware can use either a FAT-formatted update floppy or the Alpha Systems Firmware Update CD-ROM.

Firmware updates for the Alpha XL system can be obtained from:

  Alpha Systems Firmware Update CD-ROM (part number AG-PTMWU-BS in kit QZ-003AA-E8).

  FTP access with a browser.  Open the URL:
    http://ftp.digital.com/pub/Digital/Alpha/firmware.

  FTP access.  Open gatekeeper.dec.com, user = anonymous,
    password = "your internet mail address."  At the ftp prompt, type:
    cd /pub/Digital/Alpha/firmware.  Read readme.txt.

  World Wide Web (WWW)  Open the URL:
    http://www.windowsnt.digital.com.
    Go to Services and Support; Firmware and Drivers; Alpha-based Systems.

  Compuserve.  Go to the DEC4WNT forum in Library Section [4],
    Hardware Support.

	Action	Response
1.	If an update floppy is needed, copy the firmware from one of the Internet sites, unzip the files, if necessary, and copy xltab.rom to a FAT-formatted floppy; otherwise go to step 2.	A FAT-formatted floppy containing xltab.rom is prepared.
2.	Make sure the flashROM write enable jumper (J15 on the 300-MHz CPU or J18 on the 366- or 433-MHz CPU) is inserted across pins 2 and 3.  This is the default position.	None.
3.	Shut down the Windows NT operating system using the Shutdown and Restart option.	Once the shutdown process is completed, AlphaBIOS restarts.  If the autoboot timer is counting down, use an up or down arrow to change the selection.  This stops the countdown.
4.	Insert the update floppy or the Firmware Update CD-ROM.	None.
5.	From the AlphaBIOS boot screen, press the F2 key to enter AlphaBIOS Setup	The AlphaBIOS Setup screen displays
6.	Select Upgrade AlphaBIOS.	The upgrade utility starts and the following is displayed: apu-version 959328854  ** Firmware Update Utility VX.X ** ** System Type: Alpha XL ** Update Verify List Show Dump Verbose Nverbose Debug Ndebug ? Apu->
7.	Start the firmware update by typing: Apu-> update	The currently loaded firmware will be updated once you are ready. APU-I *** ROM Contents will be destroyed APU-I Are you ready to Program Device? (y/n)
8.	If you are ready, enter: y	APU-I Programming device APU-I Programming device completed APU-I Programming device APU-I Programming device completed Apu->
9.	Apu-> quit	All done.
10.	Turn off the system's power.	None.
11.	Wait at least 10 seconds, and then turn the power back on.	The system starts with the updated firmware.
NOTE: Commands such as Dump, List, Show, and Verify must have verbose mode enabled for the output to be displayed.  Type the Verbose command at the Apu-> prompt to enter verbose mode.


Preparing the disk for a Windows NT Installation

Digital Alpha XL 300, 366, or 433 ARC Firmware Console

Preparing the Disk for a Windows NT Installation

The following procedures describe how to prepare the disk for a Windows NT installation.

Digital partitions and formats disk 0 on the first SCSI controller in non-RAID Windows NT Workstation systems.  The partitions are set up as follows:

  Partition 1 (typically, the "C" drive) is the size of the disk less 6 MB
    and formatted FAT.  Normally, you select "convert to NTFS" during the
    Windows NT installation.

  Partition 2 (typically, the "D" drive) is 6 MB, formatted FAT,
    and identified as the system partition.

NOTE:  You can convert a FAT formatted disk to NTFS from the DOS Command Window with the following command:  CONVERT drive:/FS:NTFS, where drive is not the current drive.

If you are installing the operating system on a disk that has not been partitioned and formatted, use this procedure to prepare the disk.

	Action	Response
1.	Power on the system.	AlphaBIOS performs system initialization and displays the AlphaBIOS boot screen.
2.	From the AlphaBIOS boot screen, press the F2 key.	AlphaBIOS setup screen displays.
3.	Select Hard Disk Setup... Press the Enter key.	If disk 0 is partitioned, proceed to Step 4 to delete the partitions. If the message "No partitions were found on disk 0." displays, go to Step 8.
4.	Press the Delete key.	Confirmation message displays.
5.	Press the F10 key.	The partition is deleted and the space is marked unused.
6.	Use the down-arrow key to select the next partition on disk 0 and repeat Steps 4 and 5 until all disk 0 space is marked unused.	All partitions on disk 0 are deleted.
7.	Press the F7 key.	Express Hard Disk Setup confirmation message displays.
8.	Press the F10 key to continue.	Express Setup Complete message displays.
9.	Press the Enter key.	A list of disks, including partitions, displays.
10.	Press the Escape key.	AlphaBIOS setup screen displays.
11.	Press the Escape key.	AlphaBIOS boot screen displays.


Starting a Windows NT Version 3.51 Installation

Digital Alpha XL 300, 366, or 433 ARC Firmware Console

Starting a Windows NT Version 3.51 Installation

The Microsoft Windows NT Version 3.51 CD-ROM does not include the hardware abstraction layer (HAL) used on the Alpha XL 300, 366, or 433 system.  The driver for the video controller also may not be on the V 3.51 CD-ROM (depending which controller is in the system).  If the Windows NT operating system was factory installed, the Alpha XL 300/366/433 HAL was installed at the same time.  However, if Windows NT is reinstalled, the HAL needs to be reinstalled, too.

Use these procedures to ensure that the appropriate HAL and display driver are used during the Windows NT installation.

Before starting to install the Microsoft Windows NT operating system, disk 0 (or the target disk) should be partitioned as follows:

  Partition 1 (typically, the "C" drive) is the size of the disk less 6 MB and formatted FAT.  Normally, you select "convert to NTFS" during the Windows NT installation.

  Partition 2 (typically, the "D" drive) is 6 MB, formatted FAT, and identified as the system partition.

Use the following steps to install the Windows NT Workstation operating system and the appropriate HAL and display controller driver:

	Action	Response
1.	Insert the Microsoft® Windows NT™ Workstation (Version 3.51) CD-ROM into the CD drive.	CD-ROM drive is ready.
2.	From the AlphaBIOS boot screen, press the [F2] key.	AlphaBIOS setup screen displays.
3.	Select Install Windows NT. Press the [Enter] key.	Windows NT Setup displays the message, "Windows NT Setup could not determine what type of computer you have."
4.	Select  Other. Press the [Enter] key.	Insert the Manufacturer-supplied hardware support disk into Drive A:.
5.	Insert the manufacturer-supplied hardware support disk. Press [Enter] key when ready.	You have chosen to change your computer type to one supported by a disk provided by a hardware manufacturer.  A list of systems is displayed.
6.	Select the Alpha XL 300/366 Family system type. Press the [Enter] key.	The Windows NT Workstation Setup screen displays.
7.	Press the [Enter] key.	You may now continue the installation process.
8.	Select Custom Setup by pressing C.	Setup has recognized the following mass storage devices in your computer: NCR PCI (53c810)
9.	Press the [Enter] key to continue.	Setup has determined that your computer contains the following hardware and software components: Computer:  Alpha XL 300/366 Family Display:      VGA Compatible Keyboard:   XT, AT, or Enhanced (83-102 keys) Keyboard Layout:  US Pointing Device: Mouse Port Mouse No Changes: The above list matches my computer.
10.	Select Display: (to load a display driver).  Press [Enter] key.	You have asked to change the type of display to be installed.
11.	If your display controller type is not listed, select Other.  Press the [Enter] key.	Please insert the disk labeled Manufacturer-supplied hardware support disk into drive A:.
12.	Insert the provided display driver diskette.  Press [Enter] key.	A list of display types appears.
13.	Select the appropriate display.  Press the [Enter] key.	The list of hardware and software components is displayed.
14.	Select The above list matches my computer. Press the [Enter] key.	"The list below shows existing partitions and spaces available for creating new partitions."
15.	Select the target disk for the Windows NT installation. Press the [Enter] key.	Follow the on-screen instructions and continue the installation. For more information, refer to the Microsoft Windows NT Workstation System Guide.


Starting a Windows NT Version 4.0 Installation

Digital Alpha XL 300, 366, or 433 ARC Firmware Console

Starting a Windows NT Version 4.0 Installation

The Microsoft Windows NT Version 4.0 CD-ROM includes the hardware abstraction layer (HAL) used on the Alpha XL 300, 366, or 433 system.  Use these procedures to install Windows NT V4.0 and add the proper display driver, if necessary.

Before starting to install the Microsoft Windows NT operating system, disk 0 (or the target disk) should be partitioned as follows:

  Partition 1 (typically, the "C" drive) is the size of the disk less 6 MB and formatted FAT.  Normally, you select "convert to NTFS" during the Windows NT installation.

  Partition 2 (typically, the "D" drive) is 6 MB, formatted FAT, and identified as the system partition.

Use the following steps to install the Windows NT Workstation operating system and the appropriate HAL and display controller driver:

	Action	Response
1.	Insert the Microsoft® Windows NT™ Workstation (Version 4.0) CD-ROM into the CD drive.	CD-ROM drive is ready.
2.	From the AlphaBIOS Boot screen, Press [F2]	AlphaBIOS Setup screen appears.
3.	Select Install Windows NT, press [Enter]	Windows NT Setup screen appears and files are loaded.  After loading, the Windows NT Workstation Setup screen displays.
4.	Press [Enter] to continue.	Setup has recognized the following mass storage devices in your computer: Symbios Logic C810 PCI  SCSI Host Adapter.
5.	Press [Enter] to continue.	Windows NT Licensing Agreement is displayed.  Use the [Page Down] key to display the remaining pages of the agreement.
6.	Press [F8] to agree.	Setup searches for previous versions of Windows NT.  If none are found, setup displays the following: Setup has determined that your computer contains the following hardware and software components: Computer:  Alpha XL 300/366 Family Display:      VGA Compatible Keyboard:   XT, AT, or Enhanced (83-104 keys) Keyboard Layout:  US Pointing Device: Mouse Port Mouse No Changes: The above list matches my computer.
7.	If no changes are required, go to Step 12; to change the display, go to Step 8.	None.
8.	Select Display: (to load a display driver).  Press [Enter].	You have asked to change the type of display to be installed.
9.	If your display controller type is not listed, select  Other.  Press [Enter].	Please insert the disk labeled Manufacturer-supplied hardware support disk into drive A:.
10.	Insert the appropriate display driver diskette.  Press [Enter].	A list of display types appears.
11.	Select the appropriate display.  Press [Enter].	The list of hardware and software components is displayed.
12.	Select The above list matches my computer. Press [Enter].	"The list below shows existing partitions and spaces available for creating new partitions."
13.	Select the target partition, then press [Enter].	The partition you have chosen is recognized by Windows NT but is unformatted or damaged.
14.	Press [C] to continue.	You have asked to install Windows NT on the partition...
15.	Select the format, then  Press [Enter].	Follow the on-screen instructions and continue the installation.