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Copyright

The information used in this document is subject to change without notice and should not be construed as a commitment from Digital Equipment Corporation.  Digital Equipment Corporation assumes no responsibility for any errors that appear in this document.

Possession, use, duplication, or dissemination of the software described in this documentation is authorized only pursuant to a valid written license from Digital or the third-party owner of the software copyright.

Copyright © Digital Equipment Corporation 1995.  All rights reserved.

The following are trademarks of Digital Equipment Corporation:  AlphaGeneration, AlphaStation, DECchip, DEC, DECstation, DECsystem, DECWORLD, OpenVMS, VAX, VAXstation, Digital, and the DIGITAL logo.

Windows NT is a registered trademark of Microsoft Corporation.  OSF/1 is a registered trademark of Open Software Foundation, Inc.

For information about the documentation team


+ main02$ Service Information Team
AlphaStation 500 Series Service Information Team

We welcome your comments.

Writing Manager	Bob Decosta
Project Leader 	Clark Burrows
Writer  	Clark Burrows
Writer  	Art Johnson
Illustrators	Phil Barrett
Andrea Thurber

Engineering Design
Manager	Rick Hagen
Engineer	Mike Rolla


AlphaStation 500 Series Overview
Digital AlphaStation 500 Series System Overview
Click on the appropriate picture to view the area of interest.

Features
The Digital AlphaStation 500 Series system offers the following features:
Choice of operating system: Windows NT,
Digital UNIX, or OpenVMS
EV5 CPU with a 128-KB serial-boot ROM
I/O subsystem Ethernet/small computer
system interface (SCSI) peripheral component interconnect
(PCI) module
From 32 to 512 megabytes (MB) of system memory
Three-year warranty

Technical Specifications
For technical specifications, click on one of the specification types.
  Mechanical
  Electrical
  Environmental


Mechanical
Mechanical Specifications

Note:  It is important to leave adequate room for ventilation at the front, sides, and rear of an AlphaStation 500 Series system.

Height:	13 cm (5 in)
Width:	43 cm (17 in)
Depth:	46 cm (18 in)
Weight (fully loaded):	14.5 kg (32 lbs)


Electrical Specifications

Power supply:	Rated at 320 watts (maximum) output, this power supply supports -12.0, +3.43, +5.0, +12.0V  DC output voltages.
	DC Outputs	Maximum     Load	Maximum     Power
	-12.0 V	0.5 amp	6 W
	+3.43 V	35 amp	119 W
	+5.0 V	45 amp	225 W
	+12.0 V	4.6 amp	55 W
Note:	The maximum power from any combination of +3.3V DC and +5.0V DC does not exceed 260 watts.


Environmental Specifications

Storage temperature range:	-40 [image] C to 66 [image] C  (-40 [image] F to 151 [image] F)
Operating temperature range:	10 [image] C to 40 [image] C (50 [image] F to 104 [image] F)
Maximum rate of change:	11 [image] C (20 [image] F) per hour
Storage humidity range   (noncondensing):	10% to 90% relative humidity;  maximum wet bulb 65 [image] C (149 [image] F)
Operating humidity range (noncondensing):	10% to 90% relative humidity (without removable media) or 20% to 80% relative humidity (with removable media); maximum wet bulb 2 [image] C (36 [image] F)
Maximum altitude:	Nonoperating--4867 meters (16000 feet); Operating--2400 meters (8000 feet)
Acoustic power:	Nonoperating--5.1 B LWAd; Operating--5.2 B LWAd
Acoustic pressure:	Nonoperating--33 dBA LpAm; Operating--34 dBA LpAm
Shipping vibration:	IAW Federal Standard 101, method 5019
Nonoperating shock:	30 G, 25 ms halfsine


Front View of the System
System Overview
Front View of the System

1.  Diskette drive
2.  Diskette eject button
3.  CD-ROM drive
4.  CD-ROM Disc eject button
5.  Halt/Reset button
6.  LED Indicator light (DC on)
7.  LED Indicator light (SCSI activity)
8.  Louvered air intake


Rear View of the System
System Overview
Rear View of the System

 1.  Power switch
 2.  Voltage selection switch
 3.  Lock slot
 4.  System lock
 5.  Sound card stereo LINE OUT connector
 6.  Sound card stereo headphone jack
 7.  Top cover screw
 8.  Sound card microphone jack
 9.  Sound card stereo LINE IN connector
10.  Twisted pair Ethernet connector
11.  ThinWire Ethernet connector
12.  64-bit PCI expansion slot
13,14,15.  32-bit PCI expansion slots
16.  Enhanced bidirectional parallel port
17.  68-pin (wide) SCSI connector
18.  Keyboard connector
19.  Mouse connector
20.  Serial port connector (COM1)
21.  Serial port connector (COM2)
22.  AC power connector


Internal View of the System
System Overview
Internal View of the System

Callout Number	Component(s)
1	PCI riser card (Peripheral Component Interconnect Option card)
2	MAU Ethernet card (Media Adapter Unit card)
3	Audio card
4	Memory modules; two banks of four DIMMS
5	Power supply and fan
6	CD-ROM in upper slot of the right-hand storage bay area
7	Customer configuration label
8	Lower right-hand storage bay area slots.  May contain:   only one 3.5-inch x 1.6-inch mass storage device, or    up to two 3.5-inch x 1-inch mass storage devices.
9	Floppy diskette drive in upper slot of the left-hand storage bay area
10	Lower left-hand storage bay area slot for one 3.5-inch x1-inch mass storage device
11	System cooling fan
12	System board
13	PCI expansion slots (three 32-bit slots)
14	PCI expansion slot (one 64-bit slot)

Note:  The cache cooling fan is under the lower left-hand storage bay area, as is the speaker;

they do not show in this view.


+ ov:0040$ Block Diagram
Block Diagram
For more information, click on specific blocks and buses.


Block Diagram - SROM
Serial ROM

The serial read-only memory (SROM) and the SROM bus are necessary for initial program load and diagnosis of DECchip 21164-AA.  The 128-KB SROM contains code to perform power-up initialization and configuration of the central processing unit (CPU) and the input/output (I/O) system.


Block Diagram Cache
Cache

The secondary cache (B-cache) is mounted directly on the system board, and has the following features:

	2-MB third-level, direct-mapped, write-back allocate on read and write transactions
	132 bits wide (128 data bits plus 4 parity bits)
	64-byte block size
	24-K tag storage containing 8-bit tag address, 2-bit control, and 2-bit parity


Block Diagram FlashROM
FlashROM

The AlphaStation 500 Series system stores firmware in flashROM.  Four 256-KB flashROMs yield a total size of 1 MB.  The flashROM contains the power-on self-test (POST) code.  Following successful completion of POSTs, the flashROM starts the appropriate (ARC or SRM) console firmware.

Certain conditions permit writing to the flashROMs, allowing field updates to the firmware.


Memory DIMMs

The memory sub-system uses 8-byte Dual In-line Memory Modules (DIMMs) which plug directly into the system board.  The DIMMS are organized into two banks, A and B, each consisting of four DIMMs.  The system capacity is 32 to 512 MB.

Note:  Always fill at least one bank completely (A or B).  Use the same DIMMS within a bank, i.e. the same vendor, and the same memory size.

  DIMM banks configuration on the system board


Real Time Clock (TOY)
Time-of-Year (TOY) Real-Time Clock

The real-time clock is a DS1287 chip.  The chip contains date and time information and has a provision to periodically interrupt the CPU.  The chip also contains 50 bytes of nonvolatile RAM (NVRAM).


Keyboard Controller
EISA Bus (Hidden)

The extended industry-standard architecture (EISA) bus originates at the PCI-to-EISA bridge.  Note that the EISA bus is hidden, that is, it is merely a conduit for access to EISA signals; no EISA/ISA option slots are available.

The hidden EISA bus connects to:

	The adapter for the diskette drive, two serial lines, and the parallel port (the PC87312 "combo" chip, sometimes called the super I/O chip)
	The audio card
	The adapter for the time-of-year (TOY) real-time clock (the DS1287 chip)
	The adapter for the keyboard-and-mouse controller (the 8242 chip)


Audio Card

The audio card is a 16-bit ISA bus compliant device with external jacks for headphones, a microphone, and stereo input and output, and an internal speaker connector.


Keyboard Controller
Keyboard-and-Mouse Controller

The keyboard-and-mouse controller (chip 8242) connects the keyboard and mouse to the extended industry-standard architecture (EISA) bus.


Non_Volatile RAM
Nonvolatile Random-Access Memory (NVRAM)

The nonvolatile RAM (NVRAM) is an 8-KB device.  The NVRAM retains its contents, even while the system is turned off.  The NVRAM stores setup information for the console firmware--either advanced RISC computing (ARC) or system reference manual (SRM).  The system uses the ROM interface to access the NVRAM from the main memory data bus.


Memory Bus

The memory bus connects the data switch portion of the core logic chip set to main memory.  The data portion of the memory bus is 288 bits wide, including 256 bits of data and 32 bits of longword parity.


SCSI Bus

The AlphaStation 500 has an embedded fast-wide SCSI bus which supports up to four internal SCSI devices and an external connector.


MAU Ethernet Card
Ethernet and MAU Ethernet Card

The AlphaStation 500 has an embedded ethernet with both a twisted pair and a thinwire connector through jacks on the MAU ethernet card, located on the rear of the system enclosure.


PCI Bus

The peripheral component interconnect (PCI) bus provides the AlphaStation 500 Series system with its primary I/O interconnect.  The PCI bus originates in the PCI bridge portion of the core-logic chipset.  There are four PCI slots on the riser:

•	One (1) 64-bit slot, full length.

•	Three (3) 32-bit slots (1 full length, 2 half length).


PCI-ISA Bridge
PCI-to-EISA Bridge

The PCI-to-EISA bridge manages traffic flow between the PCI bus and the hidden EISA bus.  The bridge uses two chips--a controller chip (82374EB) and a bridge chip (82375EB).  The bridge also provides a utility bus interface to the mouse-and-keyboard controller and the time-of-year (TOY) real-time clock.

The PCI Arbiter sets the priority of the PCI-to-EISA bridge.


PCI Expansion Slots

The AlphaStation 500 Series system offers four peripheral component interconnect (PCI) expansion slots located on a riser card.  The slots accomodate full-sized options requiring +5V and/or +3.3V DC.

One 64-bit PCI (full length)

  	Three 32-bit PCI (one full length, two half length)

Slot #	Type
0	PCI 64-bit
1	PCI 32-bit
2	PCI 32-bit
3	PCI 32-bit


Memory Control

The memory control is part of the core logic.  Its major features include:


Data Switches
DSW (Data Switches)

The data switches (DSW) are part of the core logic.  They provide memory and data addressing information that allows control logic for most read/write operations.  The major components of the data switches are the following application-specific integrated circuits (ASICs):

  Control, I/O, and Addressing (CIA)

  Data Switch (DSW)

  GRU


Memory Address
Memory Address Bus

The memory-control portion of the core logic uses the memory address bus to supply the memory address to the dual inline memory modules (DIMMs).  Besides 12 address bits, the memory controller sends row-address select (RAS) and column-address select (CAS) signals to the DIMMs.


System Data Bus

The system data bus connects the CPU, B-cache, memory control, and data switches.  The bus is 64 bits wide.


System Address Bus

The system address bus connects the CPU to CIA.  The bus is 36 bits wide.


X-Bus

The X-bus connects the real-time clock, keyboard, mouse, and NVRAM  to the hidden EISA bus.


IOD bus
Input/Output Data (IOD) Bus

The IOD bus connects the DSW, CIA ASIC, GRU ASIC, and the flashROM.


CIA

The CIA functions as a bridge between the PCI and the CPU, B-cache, and memory.  This logic offers the following features:

	Scatter/gather mapping from the 32-bit PCI address to the 34-bit physical address
	Sparse and dense space addressing
	Storage for address information (used by the direct memory access [DMA] write buffer and the I/O write buffer)
	Filling the B-cache and extracting victims on CPU-initiated transactions
	Probing the B-cache on direct memory access (DMA) transactions and invalidating transactions on DMA write hits
	Arbitrating the sysBus
	Storing addresses for the four cache-line deep memory write buffer
	Loading the I/O write buffer and the DMA read buffer

Click on the button to see more about CIA ASIC.
  CIA ASIC


Scatter/Gather

When scatter/gather mapping is enabled, the PCI address indicates the address of a page table entry that contains the physical address of that page.  The actual scatter/gather map is stored in memory.  To improve scatter/gather operation performance, the PCI bridge (CIA) incorporates an thirty two-entry translation lookaside buffer (TLB) that increases address translation speed.


GRU ASIC
GRU

The GRU chip (DC7560A) contains system operation logic for:

  The flashROM interface

  The Cache and Memory Configuration register

  Interrupts

  System reset

The input/output data (IOD) bus provides an interface for the GRU ASIC and the CIA ASIC (using the control signals GRU_SEL and GRU_ACK).  A GRU_SEL signal passes a command from the CIA (on the IOD bus) to the GRU; a GRU_ACK signal informs the CIA that the GRU is returning data.

The type of command sent to the GRU depends on the address provided by a control and status register (CSR_ADDR, from the EV5 chip).  The type of transaction--read or write--also determines the command type.  The command format is:

Bit<7>	Bit<6>	Bits<5:0>
CSR/FlashROM	Read/Write	Address
1 = CSR    0 = FlashROM	1 = Read    0 = Write	Address of an internal control and status register (CSR) or partial address of the flashROM

  Information about GRU addressing


FlashROM Interface

The GRU data bus (GRU_DAT) attaches to 1024 KB of flashROM (divided into four 256-KB banks).  The flashROM addressing scheme is shown below.

  Information about GRU addressing


GRU Interrupt Logic

The following primary interrupt inputs control the GRU interrupt logic:

  Peripheral component interconnect (PCI) interrupts

  Control, I/O, and addressing (CIA) interrupts

  CIA error interrupts

  Nonmaskable interrupts (NMIs)

  Time-of-year (TOY) real-time clock interrupts

  Values contained in the following interrupt registers:

-  Interrupt Request register

-  Interrupt Mask register

-  Interrupt Level/Edge Select register

-  Interrupt High/Low Select register

-  Interrupt Clear register


System Reset

The system reset signal (SYS_RST_L) resets all the chips on the module.  Activate system reset asynchronously by using the primary inputs DC_OK_L or OCP_RESET_L or synchronously by writing the X'0000DEAD' value into the Reset register of the GRU.


GRU Addressing Information

The AlphaStation 500 Series system uses physical address region 87.8000.00000 to 87.FFFF.FFFF to access the GRU on the IOD bus.  The system also uses this address region to access a number of control and status registers (CSRs) as well as the external flashROM.

CPU Address	Selected Region	Mnemonic
87.8000.0000	Interrupt Request register	INT_REQ
87.8000.0040	Interrupt Mask register	INT_MASK
87.8000.0080	Interrupt Level/Edge Select register	INT_EDGE
87.8000.00C0	Interrupt High/Low Select register	INT_HILO
87.8000.0100	Interrupt Clear register	INT_CLEAR
87.8000.0140 to 87.8000.01C0	Reserved
87.8000.0340 to 87.8000.07C0	Reserved
87.8000.0800	Reserved for LEDs (currently not used in 500 Series system)	LED
87.8000.0840 to 87.8000.08C0	Reserved
87.8000.0900	Reset register	RESET
87.8000.0940 to 87.8000.0BC0	Reserved

FlashROM

87.8000.0Cxx to 87.BFFF.FCxx	256-KB flashROM bank 0  Byte-addressed by CPU address <29:12>
87.8000.0Dxx to 87.BFFF.FDxx	256-KB flashROM bank 1  Byte-addressed by CPU address <29:12>
87.8000.0Exx to 87.BFFF.FExx	256-KB flashROM bank 2  Byte-addressed by CPU address <29:12>
87.8000.0Fxx to 87.BFFF.FFxx	256-KB flashROM bank 3  Byte-addressed by CPU address <29:12>


PCI Arbiter

The PCI arbiter sets the priority of the PCI-to-EISA bridge.  POST code sets the priority to be round-robin.  The PCI-to-EISA bridge does not have enough request/grant pins to support the four slots, CIA, SCSI, and Ethernet.  The module has a sub-arbiter (2 PALS) to expand the arbitration.


CIA
Control, I/O, and Addressing (CIA)
For more information, click on specific blocks and buses.


Data Switch (DSW)
For more information, click on specific blocks and buses.


CPU Victim Path


CPU Read Miss Path


I/O Write Buffers


Buffer Select Muliplexer


DMA Buffer 0

This channel DMA buffer contains a PCI write, MEM, and B-cache buffer.


DMA Buffer 1

This channel DMA buffer contains a PCI write, MEM, and B-cache buffer.


DMA Read/Write Buffers

This section of the DSW contains the DMA buffers 0 and 1.


I/O Read Buffer


I/O Read Path


DMA Read Data Path


DMA Write Path
DMA Write Data Path


Quadword Select Multiplexer


Flip-Flop


EV5 Instruction and Address Region
EV5 Instruction and Address Logic

The EV5 instruction and address logic accepts EV5 commands and directs the instruction either to the memory port or to the I/O port.  The read/write address on a direct memory access (DMA) transaction also has access to the memory port through a multiplexer.


PCI Data Path Region
Peripheral Component Interconnect (PCI) Data-Path Logic

The PCI data-path logic acts as a PCI host bridge by generating and decoding the PCI addresses, performing error-correction code (ECC) generation and logic checks, and supplying and receiving data to and from the data switch (DSW) ASIC.


CIA PCI Commands
Control, I/O, and Addressing (CIA) PCI Commands

The CIA application-specific integrated circuit (ASIC) sends and responds to the PCI commands listed below.

PCI Command	Command Type	CIA Slave	CIA Master
0000	Interrupt Acknowledgment	No	Yes
0001	Special Cycle	No	Yes
0010	I/O Read	No	Yes
0011	I/O Write	No	Yes
0100	Reserved
0101	Reserved
0110	Memory Read	Yes	Yes
1001	Memory Write	Yes	Yes
1000	Reserved
1001	Reserved
1010	Configuration Read	No	Yes
1011	Configuration Write	No	Yes
1100	Memory Read (Multiple Lines)	Yes	No
1101	Dual Address Cycle	Yes	No
1110	Memory Read (Single Line)	Yes	No
1111	Memory Write and Inventory	Yes (*)	No

* Aliased to Memory Write


Memory Logic

In the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) of the AlphaStation 500 Series system, the memory logic provides the row and column addresses for the memory banks, as well as for the following control signals:

  Row-address select (RAS)

  Column-address select (CAS)

  Write enable

  Memory enable


I/O Address Logic

In the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) of the AlphaStation 500 Series system, the I/O address logic handles I/O read/write addressing by extracting the peripheral component interconnect (PCI) address from the CPU-encoded dense/sparse space.  To allow for a PCI retry, as well as to provide a pointer to the next data item, the I/O address logic region also increments the current address for each data cycle.


DMA Addressing Logic
Direct Memory Access (DMA) Address Logic

In the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) of the AlphaStation 500 Series system, the DMA address logic converts the peripheral component interconnect (PCI) address information to the CPU memory address space using the following conversion methods:

	A direct path where the base offset is linked with the PCI address
	A scatter/gather map path that maps an 8-KB PCI page to any 8-KB memory space page


{bmrgoback.shg}Configuring the Digital Alphastation 500 Series System Basic Configuration Information
Configuring the Digital AlphaStation 500 Series System
Basic Configuration Information

All Digital AlphaStation 500 Series systems include:

	An EV5 CPU module (with DECchip 21164-AA) that determines clock rates and secondary cache sizes
	Four PCI expansion slots (three 32-bit and one 64-bit) on the riser card
	Eight DIMM sockets and parity-protected system memory
	PCI-to-EISA bridge chip set (82374EB and 82375EB)
	1024-KB flashROM and 128-KB serial ROM
	Factory-installed operating systems--Digital UNIX  and OpenVMS
	1.44-MB, 3.5-inch diskette drive
	Two serial ports and one bidirectional enhanced parallel port
	5.25-inch CD-ROM drive
	External fast-wide SCSI port
	Ethernet port
	Audio card
	PS/2-style keyboard and mouse ports
	Keyboard and three-button mouse.

  Click here for an internal cut-away view of the system


Configuration Menu
AlphaStation 500 Series Internal System Configuration Menu
Click on the appropriate button for configuration information.

      Basic Configuration Overview


Factory-Installed Operating Systems

Digital UNIX and OpenVMS are installed on each AlphaStation 500 at the factory.  Windows NT is an available option, but is not preloaded at the factory.


Internal Mass Storage Bays
Configuring the Digital AlphaStation 500 Series System
Storage Bay Devices

The AlphaStation 500 Series system enclosure contains:

	Two accessible removable media device slots.  One slot, at the top of the left-hand storage bay area, accomodates a 3.5x1.0-inch floppy diskette drive (1), the other slot, at the top of the right-hand storage bay area, holds a .5.25x1.6-inch CD-ROM drive (4).
	Three non-accessible internal storage slots.   The left-hand internal storage bay area ((2) under the floppy drive) can hold one 3.5-inch x 1.0-inch hard disk. The right-hand internal storage bay area ((3) under the CD-ROM) contains a drive tray which accomodates up to two hard drives: either one 3.5-inch x 1.0-inch hard disk, or one 3.5-inch x 1.6-inch hard disk, or  two 3.5-inch x 1.0-inch hard disks.  Due to thermal considerations, you cannot install a 3.5-inch x 1.6-inch hard disk and a 3.5-inch x 1.0-inch hard disk simultaneously in this bay.


Expansion Card Configuration
Configuring the Digital AlphaStation 500 Series System
Expansion Options

The AlphaStation 500 Series system supports PCI bus (an industry-standard I/O bus, that is the preferred bus for high-performance I/O options)  One 64-bit peripheral component interconnect (PCI) slot and three 32-bit PCI slots are available on the PCI bus.

PCI option modules require no additional configuration procedures; the system recognizes the modules automatically and assigns the appropriate system resources.

Note:  Moving a PCI option after the operating system has been installed and configured may affect performance and require reconfiguration of the operating system.


Memory Configuration

Configuring the Digital AlphaStation 500 Series System
System-Memory Configurations

The AlphaStation 500 Series system memory uses one or two banks of on-board 8 byte Dual In-line Memory Modules (DIMMS), each bank consisting of four DIMMS, and 2 MB of cache on the system board.

DIMMs

Note:  Always fill at least one bank completely (A or B).  Use the same DIMMS within a bank, i.e. the same vendor, and the same memory size.

   System capacity 32 to 512 MB

   Data path is 256 bits plus ECC

   Latency from EV5 Read Miss is 180 ns


Cache

The AlphaStation 500 system has 2MB of cache mounted directly on the system board.  The cache read/write loop is 26.25 ns.


Console Configuration
Configuring the Digital AlphaStation 500 Series System
Console Configuration

The Digital AlphaStation 500 Series system flashROMs contain the firmware for two consoles:

	Advanced RISC computing (ARC), which supports the Windows NT operating system
	System reference manual (SRM), which supports the Digital UNIX and OpenVMS operating systems
To display or specify an operating system from the SRM console, use the os_type environment variable.  Use the SRM set command to choose one of the following values: NT, UNIX, or OpenVMS.

Note:	The SRM console can use either the COM1 serial port or the graphics controller as the console device.  The console environment variable determines the device (Serial or Graphics).  Before selecting Serial, connect a terminal to the COM1 port.

If you are using the ARC console and want to switch to the SRM console, select the Switch to OpenVMS or UNIX console command from the Setup menu.


PCI Device Configuration
Configuring the Digital AlphaStation 500 Series System
Peripheral Component Interconnect (PCI) Device Configuration

At system startup, the console firmware performs the following PCI configuration tasks:

Task		Action
Determine which PCI devices are present.		Reads the ID registers.
After locating a device, determine its address space requirements.		Writes all 1's to its base address register. (The device returns only the address bits it uses; they are set to 1.  All others are set to 0.)
Initialize the base registers.		Sets up all base address registers in sequence--from largest to smallest.
Determine interrupt assignments.		The SRM console uses the configuration database to first identify ISA bus IRQ assignments.  It then assigns open IRQs to the PCI devices. The ARC console assigns the following IRQs to the PCI devices:    IRQ10 to PCI slot 0    IRQ15 to PCI slot 1    IRQ9 to PCI slot 2    IRQ11 to the embedded SCSI.

The PCI specification defines three physical address spaces; besides the usual memory space and I/O space, there is configuration address space.  Configuration address space allows initialization and configuration of the devices by software firmware.  In addition to these PCI address spaces, uncached CPU space generates PCI interrupt acknowledgment cycles and PCI special cycles.

PCI devices have 256 bytes of configuration register information.  Of the 256 bytes, 64 bytes are the predefined header region..  The remaining 192 bytes are device-specific.

At every system startup, the PCI bus is initialized using configuration cycles (accesses to CPU addresses 87.0000.0000 through 87.1FFF.FFFF.  The initialization device select (IDSEL) input selects a PCI device during configuration read and write transactions.  The following table shows the address bits associated with the PCI devices in the AlphaStation 600 Series system.

Device	PCI Address Used as IDSEL	PCI Base Address	CPU Base Address
PCI slot 0    (graphics card)	<18>	0040.0000	87 0007.0000
PCI slot 1	<23>	0080.0000	87 000C.0000
PCI slot 2	<22>	0100.0000	87 000B.0000
PCI slot 3    (I/O subsystem module)	<19>	0200.0000	87 0008.0000
PCI slot 4	<20>	0400.0000	87 0009.0000
PCI-to-EISA bridge	<21>	0800.0000	87 000A.0000

CPU base address <20:16> represents the encoded value of the IDSEL bit to be used.  (IDSEL bits range from PCI address <31:11>.)  For example, for a CPU base address of 87 0007.0000, the encoded IDSEL value is 06.  Starting at PCI address <11> and counting up eight bits (0-7) yields a pointer to PCI address <18>, which is hardwired as an IDSEL line to the graphics controller.


PCI Configuration Space Header
PCI Predefined Header Region

PCI devices have 256 bytes of configuration register information.  Of the 256 bytes, 64 bytes are the predefined header region.  (The remaining 192 bytes are device-specific.)


SCSI Bus;configuration
Configuring the Digital AlphaStation 500 Series System
SCSI Bus Configurations

The AlphaStation 500 Series systems contain an embedded SCSI bus that is used to connect both the internal and external SCSI devices.

Note:	The SCSI bus supports up to seven devices.  Take care not to duplicate any SCSI IDs.

Both ends (and only the ends) of the SCSI bus must be terminated.  The internal end of the bus is terminated by the internal SCSI cable; therefore no internal SCSI devices should have their termination enabled.  The other end of the bus is the external SCSI connector located on the rear of the enclosure.  This connector must be terminated if no devices are attached; if external SCSI devices are attached, the last device must be terminated properly.

The default setting of jumper 31 on the system mother board is to enable auto-sense (pins 2-3).  Moving the jumper to pins 1-2 of J31 will disable the auto-sense feature and disable the termination at the external port end of the SCSI bus.

To see information on the system board jumpers, click here.


ISA Bus Configurations
Configuring the Digital AlphaStation 500 Series System
Extended Industry-Standard Architecture (EISA) Bus Configurations

The AlphaStation 500 Series system has a built-in hidden EISA (ISA) bus.  The bus is merely a conduit for the combo chip and audio card; no EISA/ISA slots are available.

A combo chip (PC87312, sometimes called the super I/O chip) provides controllers for the diskette bus, two serial lines, and the bidirectional enhanced parallel port.

A plug in sound card (ISA based, but does not use an ISA connector.

XBUS

1.  Keyboard and mouse controller

2.  Real time clock


Interrupts
Configuring the Digital AlphaStation 500 Series System
Interrupts
Click on specific blocks for descriptions.


CPU Interrupts

Interrupt Pin	IPL	Usage
IRQ<0>	20	Corrected errors detected by CIA
IRQ<1>	21	PCI and EISA interrupts
IRQ<2>	22	TOY IRQ pin
IRQ<3>	23	Reserved
SYS_MCH_CHK_IRQ	31	PCI/EISA nonmaskable interrupts (NMIs); most CIA-detected errors
MCH_HLT_IRQ		Halt button


Main Interrupt Logic Interrupts

The Interrupt assignments for INT_IRQ, IRQ<1>, IRQ<2>, and IRQ<3> are as follows:

Output	IRQ	Interrupt	Usage
EV5 IRQ<1>	0	A	PCI riser slot 2 - 32 bit
	1	B	J4
	2	C	PCI slot 11
	3	D
	4	A	PCI riser slot 1 - 32 bit
	5	B	J3
	6	C	PCI slot 12
	7	D
	8	A	PCI riser slot 0 - 64 bit
	9	B	J1
	10	C	PCI slot 7
	11	D
	12		SCSI controller, PCI slot 9
	13		Ethernet controller, PCI slot 6
	14		Reserved
	15		Reserved
	16	A	PCI riser slot 3 - 32 bit
	17	B	J5
	18	C	PCI slot 8
	19	D
	20		Alternate console
	21		Secure console
	23-22		Reserved
	27-24		Module REV
	30-28		Reserved
	31	EISA_INT	8259 chip INT output
EV5 IRQ<2>			Timer interrupt
EV5 IRQ<3>			Reserved

Note:  All unmasked IRQ inputs have equal priority.


IRQ Assignments

The timer, keyboard, and mouse are hardwired to IRQs 0, 1, and 12, respectively.  The parallel port (LPT1) is assigned to IRQ 7, although it is possible to use IRQ 5.

IRQ 8, normally the interval timer interrupt, is not connected in the AlphaStation 600 Series system.  This interrupt is routed directly to the CPU instead.

IRQ 13, normally used to signal either a coprocessor error or the end of a DMA scatter/gather operation, is not connected in the AlphaStation 500 Series system.


Main Interrupt Logic Assignments

This separate interrupt logic is provided for PCI interrupts.  EISA interrupt signals pass through this logic block after the two 8259 chips in the PCI-to-EISA bridge handle the EISA interrupt information.


ISA IRQ Assignments
EISA IRQ Assignments

IRQ	Interrupt Source
0	Internal timer (1 counter; 0 out)
1	Keyboard
2	Interrupt from controller 2
8	Reserved (normally TOY)
9	Reserved
10	Reserved
11	Reserved
12	Reserved
13	Reserved
14	Reserved
15	Reserved
3	Reserved
4	Reserved
5	Reserved
6	Reserved
7	Reserved


IRQ Controller

The interrupt controller is the functional equivalent of two 82C59 controllers and is located in the PCI-to-EISA bridge chip.  IRQ 2 on the master controller is used to cascade the controllers together.  This means that IRQs 8-15 have a higher priority than IRQs 3-7 have.


DMA Channel Assignments
Configuring the Digital AlphaStation 600 Series System
Direct Memory Access (DMA) Channel Assignments

The EISA interface uses eight DMA channels.  DMA channel 4 is used to cascade the two four-channel controllers together and therefore is unavailable.

Note:	Any DMA channel may be programmed for 8-bit or 16-bit transfers.

Avoid conflicts.  For example, if the audio card is using channel 0, keep in mind that the channel is no longer available to the EISA option slots.

Channel	Device
0	Available to EISA option slots
1	Available to EISA option slots
2	Diskette Controller
3	Available to EISA option slots and the parallel port
4	Unavailable (Channels 0-3 are cascaded to this channel)
5	Available to EISA option slots
6	Available to EISA option slots
7	Available to EISA option slots


Address Space Map
Configuration
Address Space Map

Cacheable
0 0000.0000 to 0 1FFF.FFFF	Main memory
Noncacheable
87 5000.0000 to 87 5FFF.FFFF	Memory-control registers
87 6000.0000 to 87 6FFF.FFFF	PCI [host] bridge registers
87 2000.0000 to 87 3FFF.FFFF	PCI interrupt cycle
85 8000.0000 to 85 FFFF.FFFF	PCI sparse I/O space
87 0000.0000 to 87 1FFF.FFFF	PCI configuration
PCI Sparse Memory
80 0000.0000 to 85 7FFF.FFFF	PCI
PCI Dense Memory
86 0000.0000 to 86 FFFF.FFFF	PCI


Clock Rates and Secondary Cache Sizes

Because the AlphaStation 500 Series system is synchronized to the EV5 clock speed and the PCI clock, the cache and memory timing can be different, depending on the CPU speed.  The following table outlines the cache and memory timings based on the CPU frequency.

CPU Speed		B-Cache Timing		System Timing
MHz	ns		ns	CPU Cycles		ns	CPU Cycles
266.6	3.75		26.2	7		30	8
300	3.33		26.67	8		30	9
333	3.00		27.0	9		30	10


EV5 CPU

The Digital EV5 chip is the central processing unit (CPU) for the AlphaStation 500 Series system.  This processor chip runs at either 266 Mhz or 333 MHz with a 128-K serial boot ROM.  Features of the EV5 chip include:

Cycle time:	3.2 to 4.4 nanoseconds
Address size:	43-bit virtual address, 40-bit physical address, and  8-KB page size
Pipeline depth:	7-stage integer, 9-stage floating point
I-cache:	8-KB, virtual, direct-mapped
D-cache:	8-KB, physical, direct-mapped
Secondary cache:	96-KB, physical, 3-way set-associative
Translation lookaside buffer (TLB):	64-entry ITB and 48-entry DTB, 128 address-space numbers
Write buffer:	Six 320-byte entries
Issue rate:	Four instructions/cycle (2 integer, 2 floating point)

Plus:

	Private set of address lines (INDEX) for the external cache so that the cache does not have to share loading with other system components
	A maximum 16-MB third-level external cache system (S-cache) divided into three sets, with a total capacity of 93 KB

  Information about EV5 CPU addressing


PCI-EISA bridge
PCI-to-EISA Bridge

The PCI-to-EISA bridge chip set contains a number of peripheral chip designs (for example, interrupt logic, timers, DMA control, and so forth).  These designs are located on the following chips:

  PCI to EISA bridge chip (PCEB)

  EISA system controller (ESC 82374EB)


PCI to EISA bridge chip (PCEB 82375EB)
PCI-to-EISA Bridge Chip (PCEB 82375EB)

For certain EISA devices to respond to memory addresses that cannot be changed, the main memory must be made inaccessible for that memory address range.  This inaccessible region is called a PC compatibility hole.

The PCI-to-EISA bridge provides access to main memory by partitioning the lower 512 MB of the EISA address range into subsegments that can be enabled by the following registers:

  MCSTOM

  MCSTOH

  MCSBOH

  EADC1

  EDAC2


EISA System Contoller (ESC 82374EB)
EISA System Controller (ESC 82374EB)

The AlphaStation 500 Series system uses the standard (A-2) version of this chip.  Some of the features are:

Keyboard controller:	Based on the 8242 standard.  The mouse interrupt signal (ABFULL#) is not wired to the ABFULL# input.
Soft error (SERR) and parity error (PERR):	Software must not access these inputs.
Interrupt logic:	The ESC should disable the connection of ABFULL to IRQ 12.  In addition, the real-time time-of-year (TOY) clock is not wired to this interrupt; instead, it is connected to an EV5 interrupt pin.
Time-of-year (TOY) real-time clock:	Dallas 1287 chip connected to the X-bus.
Configuration RAM:	The X-bus provides 8 KB nonvolatile RAM for EISA configuration space.
Basic input/output system (BIOS):	The X-bus provides no BIOS; the Lemmon bus provides flashROM instead.
Speaker:	Provided in addition to the supplied audio card.


SROM

The serial ROM (SROM) and the SROM bus are necessary for initial program load and diagnosis of the EV5 chip. The SROM is 128 KB and contains code to perform power-up initialization and configurations of the CPU and I/O system.


FlashROM

FlashROM stores firmware.  There are four 256-KB flashROMs for a total size of 1 MB.  Under certain conditions, the flashROMs may be written, which allows field updates to the firmware.


Ethernet/SCSI controller
Ethernet Controller

The AlphaStation 500 Series supports Ethernet connections, and provides thin-wire and twisted-pair Ethernet operation.


Super I/O Chip
Combo Chip

A PC87312 "combo" chip (sometimes called the super I/O chip) connects the hidden EISA bus to the following:

  Diskette drive controller

  Backup tape drive

  Two serial lines (UARTs)

  Bidirectional parallel port


EV5 CPU Addressing Information
Configuring the Digital AlphaStation 500 Series System
EV5 CPU Addressing Information

CPU Address	Size (GB)	Selection
00.0000.0000 to 01.FFFF.FFFF	8	Main memory
80.0000.0000 to 83.FFFF.FFFF	16	PCI memory (512 MB) sparse space--Region 0
84.0000.0000 to 84.FFFF.FFFF	4	PCI memory (128 MB) sparse space--Region 1
85.0000.0000 to 85.7FFF.FFFF	2	PCI memory (64 MB) sparse space--Region 2
85.8000.0000 to 85.BFFF.FFFF	1	PCI I/O (32 MB) sparse space--Region A
85.C000.0000 to 85.FFFF.FFFF	1	PCI I/O (32 MB) sparse space--Region B
86.0000.0000 to 86.FFFF.FFFF	4	PCI memory (4 GB) dense space
87.0000.0000 to 87.1FFF.FFFF	0.5	PCI configuration sparse space
87.2000.0000 to 87.3FFF.FFFF	0.5	PCI special/interrupt acknowledgment, sparse space
87.4000.0000 to 87.4FFF.FFFF	0.25	General control, I/O, and addressing (CIA) CSRs (*)
87.5000.0000 to 87.5FFF.FFFF	0.25	CIA memory-control CSRs (*)
87.6000.0000 to 87.6FFF.FFFF	0.25	CIA PCI address translation
87.7000.0000 to 87.7FFF.FFFF	0.25	Reserved
87.8000.0000 to 87.FFFF.FFFF	2	FlashROM GRU CSRs (*)

(*) indicates a hardware-specific, restricted version of sparse space.


Main Memory

All accesses are 64-byte cache aligned and cached by the EV5.


PCI Memory (512MB) Region 0
PCI Memory (512 MB) Sparse Space--Region 0

The PCI memory region 0 allows uncached EV5 access, byte, word, triple-byte, longword, and quadword read/write statements.

Note:	Read prefetching is not allowed in this region.


PCI Memory (128MB) Region 1
PCI Memory (128 MB Sparse Space--Region 1


PCI Memory (64MB) Region 2
PCI Memory (64 MB) Sparse Space--Region 2


PCI I/O (32MB) Sparse Space - Region A
PCI I/O (32 MB) Sparse Space--Region A

The PCI I/O region A allows uncached EV5 access, byte, word, triple-byte, longword, and quadword read/write statements, used for the lower 32 MB of PCI I/O space.

Note:	Read prefetching is not allowed in this region.


PCI I/O (32MB) Sparse Space - Region B
PCI I/O (32 MB) Sparse Space--Region B

This region is relocatable via HAE I/O CSR to any 32MB region in the PCI I/O space.


PCI Dense Memory Space (4GB)
PCI Memory (4 GB) Dense Space


PCI Configuration Sparse Space

The PCI configuration space allows uncached EV5 access to byte, word, triple-byte, longword, and quadword read/write statements.

Note:	No read prefetching is allowed in this region.


PCI Interrupt Acknowledge/Special Cycles Sparse Space


CIA CSRs (with FlashROM)


Console Commands
Digital AlphaStation 500 Series System Console Commands

The Digital AlphaStation 500 Series system contains two functional consoles:

	One, the advanced RISC computing (ARC) console, supports the Microsoft Windows NT operating system.
	The other, the system reference manual (SRM) console, supports the DEC OSF/1 and OpenVMS operating systems.

The console firmware resides in 1 MB of flashROM on the CPU module.  (Firmware can be updated in the field.)

  ARC console commands

  SRM console commands

  Firmware update procedure

  Default console setting (ARC or SRM)


ARC Commands
Digital AlphaStation 500 Series System
Console Commands

ARC Console Commands

The ARC console uses a menu interface.  After initialization, the Boot menu (shown below) displays.  For command information, click on any command.

ARC Multiboot Alpha AXP Version 4.xx
Copyright (c) 1993-1995 Microsoft Corporation
Copyright (c) 1993-1995 Digital Equipment Corporation

Boot menu:

Boot Windows NT
Boot an alternate operating system
Run a program
Supplementary menu...

Use the arrow keys to select, then press Enter.

During initialization, the firmware checks the information stored in the nonvolatile random-access memory (NVRAM).  If the information is unreadable or inconsistent, a warning message displays identifying the areas that must be fixed prior to booting the Windows NT operating system.

NVRAM may be loaded from the console, if it corrupted, using the command:
fix_eisa_config

Note:  Once ARC is selected you must go to the supplementary menu to return to SRM.


Boot Windows NT

Selecting Boot Windows NT starts the default operating system.  The boot-selection identifier, Windows NT in this case, uses values already set up in the Manage boot selections menu.  The identifier at the top of the identifier list is the default boot-selection identifier.


Boot an Alternate Operating System

Select Boot an alternate operating system to start a system other than the default.  Use this command, for example, to select another version of Windows NT that uses a different boot-selection identifier.


Run a Program

Select Run a program to specify a program to run.  The selected program runs on top of the Windows NT firmware and must be linked in a special manner.  For example, the formatting and partitioning program, ARCINST, is started in this manner.


ARC Console Supplementary Menu
Digital AlphaStation 500 Series System
Console Commands
Supplementary Menu

Select Supplementary menu for access to commands that supplement the Boot menu.  For command information, click on any command in the Supplementary menu shown below.

ARC Multiboot Alpha AXP Version 4.xx
Copyright (c) 1993-1995 Microsoft Corporation
Copyright (c) 1993-1995 Digital Equipment Corporation

Supplementary menu:

Install new firmware
Install Windows NT from CD-ROM
Set up the system...
Display hardware configuration
Boot menu...

Use the arrow keys to select, then press Enter.


Install New Firmware

Select Install new firmware to install firmware upgrades.  When selected, the system checks the diskette drive and CD-ROM drive for the firmware update tool.  Prior to selecting Install new firmware, insert the firmware update media into the appropriate device; otherwise, a timeout occurs if the proper media is not present.  Check the literature packaged with the firmware upgrade for further instructions.


Install Windows NT from CD-ROM

Prior to selecting Install Windows NT from CD-ROM, insert the Windows NT compact disc into the CD drive.  For more information, refer to the release notes provided with the Windows NT software.


Set up the system...
 Digital AlphaStation 500 Series System
Console Commands
Set Up the System

Selecting Set up the system presents a Setup menu.  Use the Setup menu to specify such items as variables, configurations, boot selections, machine-specific setups, and switches to the DEC OSF/1 and OpenVMS console.  For command information, click on any command in the Setup menu shown below.

ARC Multiboot Alpha AXP Version 4.xx
Copyright (c) 1993-1995 Microsoft Corporation
Copyright (c) 1993-1995 Digital Equipment Corporation

Setup menu:

Set system time
Set default environment variables
Set default configuration
Manage boot selection menu...
Setup autoboot
Machine specific setup...

Edit environment variables
Reset system to factory defaults

Help
Switch to OpenVMS or OSF console
Supplementary menu and do not save changes

Supplementary menu and save changes

Use the arrow keys to select, then press Enter.


Set System Time

Select Set system time to enter date and time information.


Set Default Environment Variables

Select Set default environment variables to specify the location of the default system partition.

Enter location of default system partition:

   Select media:
SCSI Hard Disk
Floppy Disk
CD-ROM

After you select the media, ARC prompts you for default environment variables.  For example, a selection of SCSI Hard Disk prompts you for such information as SCSI bus number, SCSI ID, and partition number.  Press Esc to return to the previous menu.


Set Default Configuration

Selecting Set default configuration prompts you to enter default configuration information for:

  Monitor resolution

  Diskette-drive capacity

  Keyboard language

  SCSI controller (host) ID (typically 7)

  Extended industry-standard architecture (EISA) bus configuration


Managing Boot Selection Menu...
Digital AlphaStation 500 Series System
Console Commands

Manage Boot Selection Menu

Selecting Manage Boot Selection Menu presents a Boot Selection menu.  Use it to perform tasks associated with maintaining the list of boot-selection identifiers.  For command information, click on any command in the Boot Selection menu shown below.

ARC Multiboot Alpha AXP Version 4.xx
Copyright (c) 1993-1995 Microsoft Corporation
Copyright (c) 1993-1995 Digital Equipment Corporation

Boot selection menu:

Add a boot selection
Change a boot selection
Check boot selections
Delete a boot selection
Dump boot selections
Rearrange boot selections
Setup menu...

Use the arrow keys to select, then press Enter.


Add Boot Selections
Add a Boot Selection

Select Add a boot selection to add a boot-selection identifier.  The system then prompts you to specify:

	A system partition for this boot selection (The partition defined by the Set default environment variables command should be one of the choices.)
	The directory and name for the operating-system loader (osloader)
	Whether the operating system is in the same partition as its loader
	The operating-system root directory
	A name (identifier) for this boot selection
	Whether to initialize the debugger at startup

After adding a boot selection, select Check boot selections to perform verification testing of the selection.


Changing a Boot Selection
Change a Boot Selection

Selecting Change a boot selection allows you to edit a boot selection, using the following procedure:

1.  Choose the boot-selection identifier that you wish to edit.

2.  Use the up and down arrow keys to bring up the environment variable to be changed.

3.  Press Enter to access the current setting for the selected environment variable.

4.  Press Enter and then Esc to return to the previous menu.


Checking Boot Selections
Check Boot Selections

Selecting Check boot selections performs a validity test on the available boot selections.  If the system detects a problem, it prompts you with choices to ignore the problem, delete the selection, or change the selection.


Deleting Boot Selections
Delete a Boot Selection

Selecting Delete a boot selection displays a list of boot-selection identifiers.  Use the up and down arrow keys to choose the boot-selection identifier you wish to delete.  Press Enter.  Press Esc to return to the previous menu without deleting a selection.


Dumping Boot Selections
Dump Boot Selections

Selecting Dump boot selections displays a list all of boot-selection identifiers.


Rearrange Boot Selections

Select Rearrange boot selections to resequence the list of boot-selection identifiers.  Use the up and down arrow keys to choose an identifier.  Press Enter to move that identifier to the top of the list.  (The boot-selection identifier that appears at the top of the list is the default boot selection.)


Setting up Autoboot
Set Up Autoboot

For automatic initialization of the system at startup, select Setup autoboot, then select Yes.  The ARC console uses the countdown value specified here as a waiting period before initializing the system.  Enter a countdown value here if you wish to override the 10-second default.


Machine Specific Setup
Machine-Specific Setup

Selecting Machine specific setup displays the current status of the PCI parity-checking controls.  A menu is displayed below the status lines that allows you to change the control settings.  For example:

	PCI parity checking	Use caution when making this selection.  It allows you to enable and disable PCI parity checking.  By default, PCI parity checking is set to on, but is disabled on the AlphaStation 500 Series system.


Editing Enviroment Variables
Edit Environment Variables

Selecting Edit environment variables displays a list of environment variables, which you can select using the up and down arrow keys.  After selecting a variable, press Return to open the variable for editing.  When you finish editing the variable, press Return again.  Press Esc to return to the previous menu.


Reset System to Factory Defaults

Selecting Reset system to factory defaults overwrites the environment, configuration, and boot selections with default information.  Before exiting, you are asked to confirm this action.


Help

Selecting Help displays a single-screen aid that shows the steps necessary to set up the system.


Switch to OpenVMS or OSF Console
Digital AlphaStation 500 Series System
Console Commands

Switch to OpenVMS or OSF Console

Selecting Switch to OpenVMS or OSF console allows for a change to the SRM console on the next power-on cycle.

Which operating system should be launched at the next power cycle?

Boot selection is currently NT.

Switch to NT
Switch to OpenVMS
Switch to OSF
Setup menu...

Use the arrow keys to select, then press Enter.


Supplementary Menu and Save Changes

The Supplementary menu and save changes selection is available only after configuration information has been changed.  Selecting this command reinitializes the console firmware.

Alternatively, should you wish to change configuration information and not save those changes, select the Supplementary menu and do not save changes command.


List Available Boot Devices
Display Hardware Configuration

Selecting Display hardware configuration displays a list of available hardware devices on the system.  The list shows the controller, unit numbers, device type, processor information, video option data, and PCI slot information.


SRM Console
Digital AlphaStation 500 Series System
Console Commands
SRM Console

  SRM Console Conventions

  SRM Console Shortcut Keys

SRM Console Commands

The SRM console firmware supports many commands.  Type Help at the SRM prompt (>>>) for a list of all the commands.  The console commands listed below are those you are most likely to use.  (Click on any command for more information.)

  Boot

  Examine

  Deposit

  Set

  Show


SRM Console Conventions

The following list shows SRM console conventions.

Item	Convention
Console prompt	>>>
Line-continuation prompt	_>
Maximum command length	255 characters
Several contiguous spaces or tabs	Treated as a single space.
Command abbreviations	Allowed, if not ambiguous.
Command qualifiers or options	Prefix with a space and a dash:  " -"
Numbers	Hexadecimal, unless otherwise specified. Note that registers (such as R0-R31) are shown in decimal notation.


SRM Console Special Characters
SRM Console Shortcut Keys

The following list shows SRM console shortcut keys and their actions.

Shortcut Key	Action
Return	Ends input on the command line.
Backspace	Deletes the most recently typed character.
Ctrl+A	Toggles between insert and overstrike mode.   (Overstrike is the default.)
Ctrl+B, , or	Recalls the most recent command.  (The console stores the 16 most recent commands.)
Ctrl+C	Terminates the foreground process.
Ctrl+D or	Moves the cursor left one position.
Ctrl+E	Moves the cursor to the end of the line.
Ctrl+F or	Moves the cursor right one position.
Ctrl+H	Moves the cursor to the beginning of the line.
Ctrl+O	Suppresses console output.
Ctrl+S	Stops the flow of data to the console (XON).
Ctrl+Q	Resumes the flow of data to the console (XOFF).
Ctrl+U	Deletes the entire line.
Ctrl+R	Retypes the current command line.
Ctrl+P	Halts the running software and restarts the console firmware--if enabled and in program mode.  (Ignored in console mode.)


SRM Boot Command
Digital AlphaStation 500 Series
SRM Console Commands

Boot

The boot command:

  Initializes the processor

  Loads a program image from the specified boot device

  Transfers control to the loaded image

The syntax for the boot command is:

boot [-file filename] [-flags longword[,longword]] [-protocols <enet_protocol>] [-halt] [boot_device]

Where:

-file filename	Specifies the name of a file to load into the system.  For booting from Ethernet, this name is limited to 15 characters.  Use the set boot_file command to set an environment variable that specifies a default boot file.
-flags longword[,longword]	Specifies additional information for the operating system.  In the case of OpenVMS, specify root number and boot flags here.  Use the set boot_osflags command to set an environment variable that specifies a default boot flag value.
-protocols enet_protocol	Specifies an Ethernet protocol(s) that will be used for a network boot.  Values may be mop or bootp.
-halt	Forces the bootstrap operation to halt and invokes the console program after loading the image and setting up the page tables and other data structures.
boot_device	Specifies a device path or list of devices that the firmware will attempt to boot.  Use the set bootdef_dev command to set an environment variable that specifies a default boot device.


Boot Command Examples

>>>boot	Boots the system from the default boot device.
>>>boot eza0	Boots the system from Ethernet port eza0.
>>>boot -file dec2.sys mke0	Boots the file named dec2.sys from Ethernet port mke0.
>>>boot -protocol bootp eza0	Boots using TCP/IP BOOTP protocol from Ethernet port eza0.
>>>boot -flags 0,1	Boots the system from the default boot device using flag settings 0,1.
>>>boot -halt dka0	Loads the image from disk dka0, but remains in console mode.


SRM Examine Command
Digital AlphaStation 500 Series System
SRM Console Commands

Examine

The examine command displays the contents of an address you specify.  The address can be a memory location, register, device, or file.

The syntax for the examine command is:

examine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address

Where:

-b	Byte of data
-w	Word of data
-l	Longword of data
-q	Quadword of data
-o	Octaword of data
-h	Hexword of data
-d	Display data as a decoded macro instruction
-physical	Reference physical address space
-virtual	Reference virtual address space
-gpr	Reference general-purpose register address space
-fpr	Reference floating-point register address space
-ipr	Reference internal-processor register address space
-n count	Specifies the number of consecutive locations to examine
-s step	Specifies the address increment as a hexadecimal value, allowing an override of the increment normally derived from the data size
[device:]	Selects the device to access
address	Specifies the address of the first location to examine within the current device


SRM Examine Examples
Examine Command Examples

>>>e r0 gpr: 0 (R0) 0000000000000002	Examines R0 using a symbolic address.
>>>e -g 0 gpr: 0 (R0) 0000000000000002	Examines R0 using address space.
>>>e gpr:0 gpr: 0 (R0) 0000000000000002	Examines R0 using device name.
>>>examine pc PC psr: 0(PC) FFFFFFFF80072954	Examines the program counter.
>>>examine -n 5 r7 gpr:  38 (R7)  0000000000000000 gpr:  40 (R8)  0000000000000000 gpr:  48 (R9)  0000000000000000 gpr:  50 (R10) 000000007FFBF800 gpr:  58 (R11) 000000007FF781A2 gpr:  60 (R12) 0000000000000000	Examines R7 and the next five registers.
>>>examine ipr:11 ipr: 11 (KSP) FFFFFFFF8228DFD0	Examines internal-processor register 11.


SRM Deposit Command
Digital AlphaStation 500 Series System
SRM Console Commands

Deposit

The deposit command writes data to an address that you specify.  The address can be a memory location, register, device, or file.

The syntax for the deposit command is:

deposit [-{b,w,l,q,o,h}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address data

Where:

-b	Byte of data
-w	Word of data
-l	Longword of data
-q	Quadword of data
-o	Octaword of data
-h	Hexword of data
-physical	Reference physical address space
-virtual	Reference virtual address space
-gpr	Reference general-purpose register address space
-fpr	Reference floating-point register address space
-ipr	Reference internal-processor register address space
-n count	Specifies the number of consecutive locations to examine
-s step	Specifies the address increment as a hexadecimal value, allowing an override of the increment normally derived from the data size
[device:]	Selects the device to access (with access and protection checking):     pmem--physical memory   vmem--virtual memory
address	An address that specifies the offset within a device into which data is deposited or one of the following symbolic addresses:     gpr-name, a general-purpose register   ipr-name, an internal-processor register   PC, the program counter   +, the location immediately following the last location referenced      by an examine or deposit command   -, the location immediately preceding the last location referenced      by an examine or deposit command   *, the location last referenced by an examine or deposit      command   @, the address last referenced by an examine or deposit      command
data	The data to be deposited.


SRM Deposit Command Examples
Deposit Command Examples

>>>d -n 1FF pmem:0 0	Clears the first 512 bytes of physical memory.
>>>d -l -n 3 pmem:1234 5	Deposits 5 into four longwords starting at physical memory address 1234.
>>>d -n 8 R0 FFFFFFFF	Loads general-purpose registers R0 through R8 with -1.
>>>d -l -n 10 -s 200 pmem:0 8	Deposits 8 in the first longword of the first 17 pages in physical memory.


SRM Set Command
Digital AlphaStation 500 Series System
SRM Console Commands

Set

Use the set command to set or modify the value of an environment variable.  Use environment variables to pass configuration information between the console and the operating system.

The syntax for the set command is:

set envar value [-default] [-integer] [-string]

Where:

envar	Specifies the environment variable to be assigned a new value   List of environment variables
value	Specifies the value assigned to the environment variable (either numeric or ASCII-text string)
-default	Restores the environment variable to its default value
-integer	Indicates a numeric value for the environment variable
-string	Indicates a textual value for the environment variable


SRM Set Command Examples
Set Command Examples

>>>set bootdef_dev eza0	Specifies that eza0 is the default boot device.
>>>set auto_action boot	Indicates that the console will attempt to boot following an error, halt, or power-on cycle.
>>>set boot_osflags 0,1	Sets the default boot flags to 0,1.
>>>set -default tta1_baud	Sets the baud rate for tta1 back to its default value.
>>>set foobar 5	Creates an environment variable called "foobar" and assigns it a value of 5.


Environment Variables

The following list shows environment variables and their descriptions.  (Typing show * at the SRM prompt also displays the list of environment variables.)

auto_action	Specifies the action taken by the console after an error, halt, or power-on cycleeither halt (the default), boot, or restart.
boot_file	Sets the file name to be used when a bootstrap requires a file name.  The default setting is null.
boot_osflags	Sets additional parameters to be passed to system software.  When using OpenVMS software, these parameters are the system root number and boot flags.  The default setting is 0,0.
bootdef_dev	Sets the default device or device list from which the system will attempt to boot.  If the system shipped to the customer with preloaded software, this variable is preset to point to the device containing the preloaded software.  Otherwise, the default value is null.
console	Routes the console output either to the serial line port or to the graphics controller.
control_disfd	Specifies whether the diskette drive permits write transactions.  When set to enable, this variable write-protects the diskette drive.  When set to disable, writes are permitted.
control_idema	Specifies whether the system will accept requests from IDE devices.  When set to enable, requests from IDE devices are allowed; when set to disable, requests from IDE devices are blocked.
control_irq11	Controls the source of IRQ11.  When set to irq11, the interrupt is from an ISA IRQ11 device.  When set to scsi, the SCSI controller is the source.
control_irq12	Controls the source of IRQ12.  When set to irq12, the interrupt is from an ISA IRQ12 device.  When set to mouse, the mouse controller is the source.
control_scsi_term	Specifies the termination of the SCSI bus.  When set to internal (the default), the SCSI bus terminates internally at both ends, preventing the addition of external devices.  When set to external, the SCSI bus terminates internally at only one end; the other end of the SCSI bus must terminate externally at the last external device in the SCSI chain.
os_type	Specifies the operating system in use and, therefore, which console firmware to load at startup:  nt for Windows NT and ARC firmware, osf for DEC OSF/1 and SRM firmware, or vms for OpenVMS and SRM firmware.
pci_parity	Specifies whether PCI parity checking occurs at the PCI bridge chip, effective at the next initialization or power-on cycle.  When set to on, parity checking is performed.  When set to off, parity checking is disabled.  When set to sniff, parity checking occurs only for SCSI controllers (53C810) at rev 2; otherwise, parity checking is disabled.
tga_ecl	Specifies whether the emitter-coupled logic (ECL) clock is enabled or disabled.  For use with TGA 8-plane modules only, valid values are on and off.
tga_sync_on_green	Controls the composite video signal for monitors that cannot detect the presence of composite video or v/h signals.  The possible values are: 1 - Composite video on PCI slot 0. 2 - Composite video on PCI slot 1. 4 - Composite video on PCI slot 2. 7 - Composite video on slots 0, 1, and 2.


SRM Show Command
Digital AlphaStation 500 Series System
SRM Console Commands

Show

The show command displays the current value of a specified environment variable. The show command also displays information about the system, according to the arguments entered.

The syntax for the show command is:

show [{config, device, hwrpb, memory, pal, version,...}] [envar]

Where:

config	Displays the current system configuration, including memory, PCI expansion slots, and EISA expansion slots (based on input from the configuration utility).
device [device_name]	Displays the devices and controllers in the system.  Specifying a device name returns information only on that device.
memory	Displays the memory module configuration.
pal	Displays the PALcode version for DEC OSF/1 or OpenVMS.
version	Displays the version of the console firmware.
map	Displays the system virtual memory map.
envar	Displays the value of the environment variable specified.


SRM Show Command Examples
Show Command Examples

>>>show device	dka0.0.0.6.0    DKA0   RZ25L          0006 dka400.4.0.6.0  DKA400 RRD43          3213 dva0.0.0.0.1    DVA0 era0.0.0.0.1    ERA0   08-00-2B-E2-1C-25 pka0.7.0.6.0    PKA0   SCSI Bus ID 7
>>>show memory	Memory Size = 288Mb Bank   Size   Base Addr   Speed 00     128Mb  000000000   Fast 01     128Mb  008000000   Fast 06     032Mb  010000000   Slow BCache Size = 4Mb Tested Memory = 33Mbytes


FlashROM Update Procedure
Digital AlphaStation 500 Series System
Console Commands

Firmware Update Procedure

The AlphaStation 500 Series system contains four flashROMs--two with ARC console firmware (for the Windows NT operating system) and two with SRM console firmware (for the DEC OSF/1 and OpenVMS operating systems).  To update this firmware, use the update utility.

The update utility contains three images:  the update utility itself, the SRM image, and the ARC image.  During an update, the utility uses the existing console port (either the serial-line port or the graphics port).

To update the firmware from the SRM console:

	Action	Response
1.	Verify that the flashROM enable jumper (W13) is in the write-enabled position (the default position).	None.
2.	Insert the CD-ROM that contains the update.	None.
3.	Initialize the system: >>>boot dva0	The following information displays while the update utility loads: *** Alpha Firmware Update Utility V1.0 *** *** System Type: Digital AlphaStation 600 *** Update Verify List Show Dump ? Apu->
4.	Use the update command to invoke the update utility:   Apu-> update	Information similar to that shown below displays as the firmware updates.  (The actual information may change between versions.) Apu-> update Version = 3.5.a Vendor = DEC Product = Digital AlphaStation 500 Firmware = ARC Length = 0x2f5c6 Rom Set = 1 (ROMs 2,3) APU-I VERIFY LOADED ROM IMAGE 0x2f5c6 APU-I VERIFY LOADED ROM IMAGE DONE Rom 2 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8 Rom 3 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8 Version = bl4 Vendor = DEC Product = Digital AlphaStation 500 Firmware = SRM  Length = 0x5dc00  Rom Set = 0 (ROM's 0,1)  APU-I VERIFY LOADED ROM IMAGE  0x5dc40 APU-I VERIFY LOADED ROM IMAGE DONE  APU-I *** ROMS 0,1 CONTENTS WILL BE DESTROYED ***  APU-I ARE YOU READY TO PROGRAM DEVICE ? (Y/N ) y  Rom 0 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8  Rom 1 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8  APU-I ROM SET NOT ERASED  APU-I PRECHARGING DEVICE  0x80000  APU-I ERASING ROM DEVICE  0x80000  APU-I PROGRAMMING DEVICE  0x5DC40  APU-I ROM 0 VERIFYING ROM IMAGE  0x5DC40  APU-I PROGRAMMING COMPLETED  0x5DC40  0x5DC40  SRM Rom Update Successful  Version = 3.5.a  Vendor = DEC  Product = Digital AlphaStation 500  Firmware = ARC  Length = 0x2f586  Rom Set = 1 (ROM's 2,3)  APU-I VERIFY LOADED ROM IMAGE  0x2f5c6  APU-I VERIFY LOADED ROM IMAGE DONE  Rom 2 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8  Rom 3 Manufacturer = Amd (0x01) 28F020 (0x2a) 256K x 8  APU-I ROM SET NOT ERASED  APU-I PRECHARGING DEVICE  0x80000  APU-I ERASING ROM DEVICE  0x80000  APU-I PROGRAMMING DEVICE  0x2f5c6  APU-I ROM 1 VERIFYING ROM IMAGE  0x 2f5c6 APU-I PROGRAMMING COMPLETED  0x 2f5c6 0x31e65  ARC Rom Update Successful  Apu->
5.	Use the verify SRM command to verify the integrity of the SRM firmware:   Apu-> ver srm	Information similar to that shown below displays during the verification.  (The actual information may change between versions.) Apu-> ver srm  Version = bl4  Vendor = DEC  Product = Digital AlphaStation 600   Firmware = SRM  Length = 0x62a00  Rom Set = 0 (ROM's 0,1)  APU-I VERIFY LOADED ROM IMAGE  x5dc40  APU-I VERIFY LOADED ROM IMAGE DONE  0x5dc40 0x5dc40  Rom Checksum 0xd0  Rom Verify Successful Apu->
6.	Use the quit command to exit the utility:   Apu-> quit


Setting the Default Console
Digital AlphaStation 500 Series System
Console Commands
Setting the Default Console

The default console can be switched from SRM (for the DEC OSF/1 and OpenVMS operating systems) to ARC (for the Windows NT operating system) or back using one of the following two procedures:

From SRM to ARC:

	Action	Response
1.	At the SRM prompt, type: >>>set os_type nt	>>>
2.	Turn off the system.
3.	Turn on the system.	The Boot menu appears on the ARC console.

From ARC to SRM:

	Action	Response
1.	Turn on the system.	The Boot menu appears on the ARC console.
2.	Select Supplementary menu.	The Supplementary menu appears.
3.	Select Set up the system.	The Setup menu appears.
4.	Select Switch to OpenVMS or OSF console.	The following text appears: Which operating system should be launched at the next power cycle? Boot selection is currently NT. Switch to NT Switch to OpenVMS Switch to OSF Setup menu... Use the arrow keys to select, then press Enter.
5.	After making your selection, return to the Setup menu.
6.	Select Supplementary menu and save changes.
7.	Turn off the system.
8.	Turn on the system.	>>>


Part Numbers
Digital AlphaStation 500 Series System
FRU Part Numbers

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

Kernal	Field-Replaceable Units
Part Numbers	(FRUs)
30-45491-01	320W power supply
54-24327-01	266 Mhz System board
54-24358-01	PCI riser card
54-23178-02	Audio card
54-24736-01	MAU Ethernet card
17-03970-03	Floppy (FDI) cable, 34 pos
17-04071-02	MAU Ethernet cable
17-04272-01	CD-ROM/audio cable
17-04245-01	68 pin wide internal SCSI cable
17-04009-01	68 to 50 pin SCSI cable adapter
PBXRD-CB	RRD45 CD-ROM, 4x speed, 600 MB, frost white
PBXRX-AB	RX23L 1.44 MB floppy drive, frost white
AVH01-AA	Headphones/microphone
PBXWS-WA	3 button mouse, frost white
12-41768-01	68-pin wide SCSI terminator
Packaged Systems	Field-Replaceable Units
Part Numbers	(FRUs)
PBXRW-EB	RZ26N-W 1 GB SCSI disk
PBXRW-JB	RZ28D-W 2.1 GB SCSI disk
MSP01-FA	32 MB DIMM (4-8MB boards)
MSP01-FB	64 MB DIMM (4-16MB boards)
MSP01-FC	128 MB DIMM (4-32MB boards)
MSP01-FD	256 MB DIMM (4-64MB boards)
PBXGB-AA	TGA2 8 plane ZLXp-EN2
PBXGC-BN	PV-PCI ZLXp-L2 graphics
Enclosure	Field-Replaceable Units
Part Numbers	(FRUs)
70-32022-01	Chassis assembly
70-32026-01	Cover assembly
70-32036-01	Bezel assembly
70-32053-01	Top cover assembly
74-50598-01	Panel, right
70-32037-01	Panel assembly, left
74-50598-01	Fan guard
74-50610-01	Floppy tray
74-50611-01	Floppy shield
74-50628-01	Hard drive tray
70-32021-01	CD-ROM tray assembly
70-32775-01	LED and reset assembly
12-37977-03	Lock assembly with master key
74-50613-01	Lock pawl
74-51196-01	Latch pin
70-32774-01	Speaker assembly

Note:  For additional Information, see the AlphaStation 500 Systems and Options Catalog


Connector Pinouts
Digital AlphaStation 500 Series System
Connector Pinouts

Pinout descriptions are shown below.

1.	COM2 serial port connector pinouts
2.	COM1 serail port connector pinouts
3.	Mouse connector pinouts
4.	Keyboard connector pinouts
5.	Wide SCSI connector pinouts
6.	Enhanced bi-directional parallel port pinouts


Keyboard Port Pinouts
Digital AlphaStation 500 Series
Keyboard Connector Pinouts

The keyboard connector is a miniature, six-position, circular DIN receptacle.

Pin	Signal
1	KBData
2	N/C
3	Ground
4	+5V DC
5	KBClock
6	N/C


Mouse Port Pinouts
Digital AlphaStation 500 Series System
Mouse Connector Pinouts

The mouse connector is a miniature, six-position, circular DIN receptacle.

Pin	Signal
1	MSData
2	N/C
3	Ground
4	+5V DC
5	MSClock
6	N/C


68-Pin High-Density SCSI Port
Digital AlphaStation 500 Series System
SCSI Connector Pinouts

The 68-pin high-density port (a single-ended P-cable) uses the following connector contact assignments:

Pin	Signal	Description		Pin	Signal	Description
1	Ground			35	DB(12)*	Data-bus line 12
2	Ground			36	DB(13)*	Data-bus line 13
3	Ground			37	DB(14)*	Data-bus line 14
4	Ground			38	DB(15)*	Data-bus line 15
5	Ground			39	DB(P1)*	Data-bus parity
6	Ground			40	DB(0)*	Data-bus line 0
7	Ground			41	DB(1)*	Data-bus line 1
8	Ground			42	DB(2)*	Data-bus line 2
9	Ground			43	DB(3)*	Data-bus line 3
10	Ground			44	DB(4)*	Data-bus line 4
11	Ground			45	DB(5)*	Data-bus line 5
12	Ground			46	DB(6)*	Data-bus line 6
13	Ground			47	DB(7)*	Data-bus line 7
14	Ground			48	DB(P)*	Data-bus parity
15	Ground			49	Ground
16	TERMPWR	Terminate Power		50	Ground
17	TERMPWR	Terminate Power		51	TERMPWR	Terminate Power
18	Reserved			52	TERMPWR	Terminate Power
19	Ground			53	Reserved
20	Ground			54	Ground
21	Ground			55	ATN*	Attention
22	Ground			56	Ground
23	Ground			57	BSY*	Busy
24	Ground			58	ACK*	Acknowledge
25	Ground			59	RST*	Reset
26	Ground			60	MSG*	Message
27	Ground			61	SEL*	Select
28	Ground			62	C/D*	Control/Data
29	Ground			63	REQ*	Request
30	Ground			64	I/O*	Input/Output
31	Ground			65	DB(8)*	Data-bus line 8
32	Ground			66	DB(9)*	Data-bus line 9
33	Ground			67	DB(10)*	Data-bus line 10
34	Ground			68	DB(11)*	Data-bus line 11
Notes:	An asterisk (*) following a signal name indicates an active-low signal.   Reserved lines are open in the bus-terminator assemblies and in SCSI devices on the SCSI bus; they have continuity from one end of the SCSI bus to the other.


Communications Port Pinouts
Digital AlphaStation 500 Series System
Communications Port Pinouts

The AlphaStation 500 Series system uses two identical nine-position subminiature-D serial-line male connectors for communications.  These serial ports support baud rates of 300, 1200, 2400, 4800, 9600, 19 200, and 38 4000 and use the following connector contact assignments:

Pin	Signal	Description
1	DCD	Data carrier detect
2	RXD	Receive data
3	TXD	Transmit data
4	DTR	Data terminal ready
5	GND	Signal ground
6	DSR	Data set ready
7	RTS	Request to send
8	CTS	Clear to send
9	RI	Ring indicator


Parallel Port Pinouts
Digital AlphaStation 500 Series System
Bidirectional Parallel Port Pinouts

A 25-position subminiature-D parallel-port female connector provides an interface to a printer (or other parallel devices) and uses the following connector contact assignments:

Pin	Signal	Description
1	STB-R*	Strobe
2	PRTD0	Printer data bit 0
3	PRTD1	Printer data bit 1
4	PRTD2	Printer data bit 2
5	PRTD3	Printer data bit 3
6	PRTD4	Printer data bit 4
7	PRTD5	Printer data bit 5
8	PRTD6	Printer data bit 6
9	PRTD7	Printer data bit 7
10	ACK*	Acknowledge
11	BUSY	Busy
12	PE	Paper end
13	SLCT	Select
14	AUTOFDXT*	Autofeed
15	ERR*	Error
16	INIT*	Initialize printer
17	SLCTIN*	Select input
18 to 25	GND	Ground
Note:	An asterisk (*) following a signal name indicates an active-low signal.


Jumpers
Digital AlphaStation 500 Series System
Jumpers

For information about specific jumpers, click on one of the following system components:

 System board

 System board SROM


System Board Jumpers
Digital AlphaStation 500 Series System

System Board Jumpers

The system board jumper pins allow you to set specific parameters by changing the pin location on the jumper blocks.

To set a jumper, remove it from its current location using either your fingers or a pair of small needlenose pliers.  Place the jumper over the pin or pins designated for the desired settings.  Press the jumper evenly onto the pins; be careful not to bend the pins.

Jumper	Pins 1 to 2	Pins 2 to 3	Function
J6	Reset*	Halt	Sets front panel button for Reset or Halt
J9	Secure console enabled	Disabled*	Secures the console
J10	Alternate console enabled	Primary console enabled*	Alternate console
J18	FlashROM write protect	Write enabled*	Permits write transactions to flashROM
J2, J20, J33, J35			Ground reference jumpers for debug
Note:	An asterisk (*) indicates a factory-set default.


SROM Selection Jumpers
Digital AlphaStation 500 Series System
SROM Selection Jumpers

There are eight loadable images in the SROM device.  Use one jumper to select the SROM output desired.

Note:	Only one jumper may be used at any one time.
Jumper	Jumper Position	Description
J11	0	Powerup (default)
J12	1	Mini-console
J13	2	Floppy loader
J14	3	Mfg memtest
J15	4	Reserved
J16	5	Reserved
J17	6	MCHK mini-console
J19	7	No Init mini-console


System Clock
Digital AlphaStation 500 Series System
System Clock Frequency

A DIP switch is provided on the system board to set the frequency of the system clock during manufacture and upgrades.  Check to ensure it is set properly for the clock speed you are running at on this system.

The speed is set in Hexadecimal using the four sliding switches.

System Frequency	Set Switches	Binary Number
(MHz)	#  3  2  1  0  to:	in Hexadecimal
266	1  0  0  0	8
300	1  0  0  1	9
333	1  0  1  0	10


Understanding Error Codes
Digital AlphaStation 500 Series System
Understanding SROM Error Codes

The AlphaStation 500 Series displays the following categories of SROM error codes for power-up, mini-console, and failsafe programs:

 Status codes

 Non-fatal error codes

 Fatal error codes


SROM Status Codes
Digital AlphaStation 500 Series System
SROM Status Codes

The AlphaStation 500 Series systems use the following status codes:

Status Codes	Executing Code
DF	Power is on
DE	Init CPU/system interface
DD	Sizing CPU speed
DC	Sizing and initing the scache
DB	Init PCI and test PCI bus data path
DA	Bcache sizing in process
D9	Memory sizing in process
D8	Memory configuration in process
D7	Memory test initialization
D6	Bcache bits test in process
D5	Memory bits test in process
D4	Bcache address test in process
D3	Memory addr test in process
D2	Bcache cell test in process
D1	Memory cell test in process
D0	Initialize all of memory
CF	FlashROM code loading
CE	Re-init CPU/system interface
CD	Code execution complete


SROM Nonfatal Error Codes
Digital AlphaStation 500 Series System
SROM Nonfatal Error Codes

Non-fatal errors do not impair the basic operation of the system.  When a non-fatal error occurs on an AlphaStation 500 Series system, execution continues.  These errors range from 0xEF through 0xE0 (or E[rror]F through E[rror]0).

Status Codes	Status
EF	No bcache bits detected
EB	CPU_speed detect failure
E9	No real- time clock (TOY); the system will default to 300 Mhz, providing the most relaxed operating parameters.
E5	Memory data path error; the offending bank will be mapped-out and memory will then be reconfigured.  If there is no more memory to reconfigure after the offending bank has been mapped-out, error code FA will be displayed.
E4	Memory address line error; the offending bank will be mapped-out and memory will then be reconfigured.  If there is no more memory to reconfigure after the offending bank has been mapped-out, error code FA will be displayed.
E3	Memory cell error; the offending bank will be mapped-out and memory will then be reconfigured.  If there is no more memory to reconfigure after the offending bank has been mapped-out, error code FA will be displayed.
E0	ROM checksum error

Status codes will not be visible at the SROM port until completion of CPU sizing   Therefore, the first code visible at the SROM port is DC.  (These programs provide more extensive reporting, including the address of data miscompares, the data expected, the data received and XOR differences.)

Note: The AlphaStation 500 Series systems send all status codes to the Diagnostic port (J4) on the system board.  A Flamingo lights and switches cable/module is required (36-24502-01.B01 / 54-21145-01).

Note:  The LED and Halt/Reset cable must be removed from J5 when J4 is used.  J5 and J4 can not be used simultaneously.


SROM Fatal Error Codes
Digital AlphaStation 500 Series System
SROM Fatal Error Codes

Fatal errors are those from which a process can not recover. When a fatal error occurs on an AlphaStation 500 Series system, execution halts.  These errors range from 0xFF through 0xF0 (or F[atal]F through F[atal]0).

Status Codes	Status
FF	No scache bits set in sc_ctl register
FD	Floppy drive error
FC	No MMBs or MMB mismatch
FB	Reserved
FA	No usable memory detected, or all detected memory has failed memory test
F9	Sys init failure - read/write miscompare in one of the control/status registers
F8	PCI data path error
F7	Pceb init failure
F6	A bad CIA memory CSR was found.
F5	Bcache data path error
F4	Bcache address line error
F3	Bcache cell error
F2	Reserved
F1	ROM data path read error
F0	Reserved


Digital AlphaStation 800 Series Machine Check Registers
Digital AlphaStation 500 Series System
Control and Status Registers

The AlphaStation 500 Series system typically reports hardware problems in a machine-check frame.  Occasionally, however, you must determine the contents of a register before you can identify the failing unit.  The AlphaStation 500 Series system uses several types of control and status registers (CSRs) during read/write transactions.  Click on one of the categories below for more information.

	General control, I/O, and addressing (CIA) CSRs
	Diagnostic CSRs
	Performance-monitoring CSRs
	Error-reporting CSRs
	Memory-control CSRs
	Peripheral component interconnect (PCI) address-related CSRs
	Scatter/gather address-translation CSRs
	GRU-related CSRs
	EV5 system-specific configuration CSRs


General CIA Registers
Control and Status Registers
General CIA Registers

General CIA registers contain general information about the application-specific integrated circuit (ASIC) for control, I/O, and addressing (CIA).  Click on any general CIA register in the list that follows for information about the contents of that register.

	CIA Revision (CIA_REV)
	PCI Latency (PCI_LAT)
	CIA Control (CIA_CTRL)
	Hardware Address Extension Sparse Memory (HAE_MEM)
	Hardware Address Extension Sparse I/O Space (HAE_IO)
	Configuration Type (CFG)
	CIA Acknowledgment Control (CACK_EN)


PCI Revision Register
General CIA Control and Status Registers
CIA Revision Register

Note:  The register differs for various revisions of CIA

For Reads:

CIA Revision 1 (AlphaStation 500/266)

CIA Revision 2 (AlphaStation 500 Series Systems Other than /266)

The CIA Revision register (CIA_REV) contains the revision level for the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC).

Click on the Description button to display the bit fields.


PCI_REV Register Bit Descriptions
CIA_REV Register Bit Descriptions

CIA Revision 1 (AlphaStation 500/266)

CIA_REV	<7:0>	R-O	CIA ASIC revision number
Reserved	<31:8>	R-O	N/A

CIA Revision 2 (AlphaStation 500 Series Systems Other than /266)

CIA_REV	<7:0>	R-O	CIA ASIC revision number
ALT_MEM	<8>	R-O	0    High asserted RAS and CAS, SET_SELECTS 1    Low asserted RAS and CAS
Reserved	<31:9>	R-O	N/A


PCI Latency Register
General CIA Control and Status Registers
PCI Latency Register

Note:  The register differs for various revisions of CIA

For Reads/Writes:

CIA Revision 1 (AlphaStation 500)

CIA Revision 2 (AlphaStation 500)

The PCI Latency register (PCI_LAT) contains the PCI master latency-timer value for PCI clock cycles.

Click on the Description button to display the bit fields.


PCI_LAT Register Bit Descriptions

CIA Revision 1 (AlphaStation 500)

Reserved	<7:0>	R-O	N/A
LATENCY	<15:8>	R/W	PCI master latency-timer value for PCI clock cycles
Reserved	<31:16>	R-O	N/A

CIA Revision 2 (AlphaStation 500)

Re-try Wait     Count	<3:0>	R/W	0 = Default  1 = Wait one cycle  2 = Wait two cycles  .  = .     three  .  = .  .  = . 14 =   F = Wait forever
Master    Re-try   Count	<7:4>	R/W	0 = Wait two cycles  1 = Wait 2 + 4 x value of the register cycles  .  = .  .  = . 14 =   F = Wait a random value between 2-63 cycles
LATENCY	<15:8>	R/W	PCI master latency-timer value for PCI clock cycles
Reserved	<31:16>	R-O	N/A


CIA Control Register
General CIA Control and Status Registers
CIA Control Register

For Reads/Writes:

The CIA Control register (CIA_CTRL) contains general control information for the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC).

Because this register contains more data than can be displayed here, click on the Description button to display the bit fields and access a more thorough explanation.


CIA_CTRL Register Bit Descriptions

Descriptions of the CIA control register bits follow:

PCI_EN	<0>	R/W	When set to 0, CIA is resetting the PCI bus
PCI_LOCK_EN	<1>	R/W	When set to 1, this bit locks the CIA when specified by the PCI.
PCI_LOOP_EN	<2>	R/W	When set to 1, the CIA responds as a target when it is the master.
FST_BB_EN	<3>	R/W	When set to 1, the CIA initiates fast back-to-back PCI transactions.
PCI_MST_EN	<4>	R/W	When set to 1, the CIA initiates PCI transactions.
PCI_MEM_EN	<5>	R/W	When set to 1, the CIA responds to PCI transactions.
PCI_REQ64_EN	<6>	R/W	When set to 1, the CIA requests 64-bit PCI transactions.
PCI_ACK64_EN	<7>	R/W	When set to 1, the CIA accepts 64-bit PCI data transactions.
ADDR_PE_EN	<8>	R/W	When set to 1, the CIA checks for PCI-address parity errors.
PERR_EN	<9>	R/W	When set to 1, the CIA checks for PCI-data parity errors.
FILL_ERR_EN	<10>	R/W	When set to 1, the CIA issues FILL_ERROR if an error occurs during an EV5 read-miss command.
MCHK_ERR_EN	<11>	R/W	When set to 1, signals the ERROR pin to report system machine-check conditions.
ECC_CHK_EN	<12>	R/W	When set to 1, the CIA checks the input/output data (IOD).
ASSERT_IDLE_BC	<13>	R/W	When set to 1, the CIA signals the IDLE_BC pin each time it also signals the ADDR_BUS_REQ pin.
CON_IDLE_BC	<14>	R/W	When set to 1, the CIA verifies that unused B-cache (IDLE_BC) is contiguous.
CSR_IOA_BYPASS	<15>	R/W	When set to 1, the CIA bypasses the I/O address queue.
IO_FLUSHREQ_EN and CPU_FLUSHREQ_EN	<16> and <17>	R/W R/W	Used in combination, this two-bit control determines the CIA's response to a PCI master signaling FLUSH_REQ. Bit combinations allowed and responses that result
ARB_EV5_EN	<18>	R/W	When set to 1, the CIA enables the bypass path from EV5 to the memory and I/O address queue.
EN_ARB_LINK	<19>	R/W	When set to 1, CPU-memory read commands may link (share a common row-address select [RAS] strobe).
RD_TYPE	<21:20>	R/W	This bit section controls the prefetch algorithm used for PCI-memory read commands. Bit combinations allowed and responses that result
Reserved	<23:22>	R-O	N/A
RL_TYPE	<25:24>	R/W	This bit section controls the prefetch algorithm used for PCI-memory read-line commands. Bit combinations allowed and responses that result
Reserved	<27:26>	R-O	N/A
RM_TYPE	<29:28>	R/W	This bit section controls the prefetch algorithm used for PCI-memory read-multiple commands. Bit combinations allowed and responses that result
Reserved	<30>	R-O	N/A
EN_DMA_RD_PERF	<31>	R/W	When set to 1, the CIA enables the direct memory access (DMA) read performance logic.


FLUSH_REQ Control Table

When a master peripheral control interconnect (PCI) signals a FLUSH_REQ to the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC), the setting for two bits--IO_FLUSHREQ_EN and CPU_FLUSHREQ_EN--controls the response from the CIA.

IO_FLUSHREQ_EN	CPU_FLUSHREQ_EN	CIA Response
0	0	Signals an immediate memory acknowledgment (MEM_ACK)
0	1	Signals an immediate memory acknowledgment (MEM_ACK) and prohibits any new CPU commands
1	0	Not allowed
1	1	Waits for empty I/O address queue, then signals a memory acknowledgment (MEM_ACK) and prohibits any new CPU commands


PCI Read Prefecth algorithm Values
PCI Read Prefetch Algorithm Values

Two-bit settings in the CIA Control register (CIA_CTRL) serve as prefetch algorithms for the following PCI read commands:

	PCI-memory read (RD_TYPE at <21:20>)
	PCI-memory read-line (RL_TYPE at <25:24>)
	PCI-memory read-multiple (RM_TYPE at <29:28>)
Prefetch Bit Combination		Fetch Response
00	(Short)	Locates and loads the longword (or quadword) and the remainder of the cache block
01	(Medium)	Locates and loads only the next block (within the 8-KB page boundary)
10	(Long)	Continues locating and loading until the PCI transaction completes (within the 8-KB page boundary)
11	Reserved	N/A


CIA Configuration Register
General CIA Control and Status Registers
CIA Configuration Register

Note:  This register is only applicable to AlphaStation 500 Series systems other than the 500/266.

For Reads/Writes:

The CIA Configuration Register (CIA_CONFIG) enables CIA support characteristics for CIA Revision 2.  The PCI Target Monster Window gives direct access to all memory from the PCI whenever adevice is issuing a dual address cycle when address bit 40 = 1.  When PCI I/O Write Chaining is enabled, CIA will link consecutive writes to a single PCI transaction.


CIA_CONFIG Register Bit Descriptions

IOA_BWEN	<0>	R/W	EV56 Byte/Word support 0           Disabled (default) 1           Enabled
Reserved	<3:1>	R-O	N/A
PCI_MWEN	<4>	R/W	PCI Monster Window 0           Disabled 1           Enabled
PCI_DWEN	<5>	R/W	PCI second DMA Write Buffer 0           Disabled 1           Enabled
Reserved	<7:6>	R-O	N/A
PCI_WLEN	<8>	R/W	PCI Write Chaining 0           Disabled 1           Enabled
Reserved	<31:9>	R-O	N/A


Hardware Address Extension Register
General CIA Control and Status Registers
Hardware Address Extension Sparse Memory Register

For Reads/Writes:

The Hardware Address Extension Sparse Memory register (HAE_MEM) allows the extension of a PCI sparse-space memory address up to the 32-bit PCI address limit.  The CPU address provides the low-order PCI address bits.  The high-order PCI address bits (31 through 26) are provided either by this register or by the CPU address, depending on the sparse-space region.

Note:	Initializing this register to 00000.2028 makes all three regions contiguous starting at PCI address 0.

Click on the Description button to display the bit fields.


HAE_MEM Register Bit Descriptions

Region 1	<31:29>	R/W
Reserved	<28:16>	R-O
Region 2	<15:11>	R/W
Reserved	<10:8>	R-O
Region 3	<7:2>	R/W
Reserved	<1:0>	R-O

Descriptions of high-order sparse-space bits


High-Order Sparse Space Bit Descriptions
High-Order Sparse-Space Bit Descriptions

				PCI Address
CPU Address	Region	31	30	29	28	27	26
80.0000.0000 -   83.FFFF.FFFF	1	HAE_MEM at <31>	HAE_MEM at <30>	HAE_MEM at <29>	CPU at <33>	CPU at <32>	CPU  at <31>
84.0000.0000 -   84FFFF.FFFF	2	HAE_MEM at <15>	HAE_MEM at <14>	HAE_MEM at <13>	HAE_MEM at <12>	HAE_MEM at <11>	CPU at <31>
85.0000.0000 -   85.7FFF.FFF	3	HAE_MEM at <7>	HAE_MEM at <6>	HAE_MEM at <5>	HAE_MEM at <4>	HAE_MEM at <3>	HAE_MEM at <2>


Hardware Address Extension I/O Register
General CIA Control and Status Registers
Hardware Address Extension Sparse I/O Space Register

For Reads/Writes:

The Hardware Address Extension Sparse I/O Space register (HAE_IO) allows the extension of a PCI sparse-space I/O address up to the 32-bit PCI address limit.  The CPU address provides the  low-order PCI address bits (through bit 24).  The high-order PCI address bits (25 through 31) are provided by this register.

Note:	Setting this register to 200 Hex makes region A and region B consecutive in the lower 64 MB of PCI I/O space.

Click on the Description button to display the bit fields.


HAE_IO Register Bit Descriptions

Reserved	<24:0>	R-O	N/A
HAE_IO	<31:25>	R/W	At system startup, this register is set to 0.  When set to 1, a PCI sparse-space I/O address may extend to the 32-bit limit.


Configuration Type Register
General CIA Control and Status Registers
Configuration Type Register

For Reads/Writes:

The Configuration Type register (CFG) is used as the low two address bits when accessing the PCI configuration space.

Click on the Description button to display the bit fields.


CFG Register Bit Descriptions

CFG	<1:0>	R/W	00            Type 0 configuration cycle (initial state) 01            Type 1 configuration cycle 1x            Reserved
Reserved	<31:2>	R-O	N/A


CIA Acknowledgement Control Register
General CIA Control and Status Registers
CIA Acknowledgment Control Register

For Reads/Writes:

The CIA Acknowledgment Control register (CACK_EN) enables the CIA's response to EV5 commands.

Click on the Description button to display the bit fields.


CACK_EN Register Bit Descriptions

CACK_EN	<3:0>	R/W	When set to 1, this bit region enables the CIA to send an acknowledgment (CACK) to the EV5.  When set to 0, the CIA ignores the corresponding EV5 command.   Setting   Controls   xxx1     LOCK enable   xx1x     MB (memory barrier) enable   x1xx     SET_DIRTY enable   1xxx     BC_VICTIM enable
Reserved	<31:4>	R-O	N/A


Diagnostic Registers
Control and Status Registers
Diagnostic Registers

The AlphaStation 500 Series system uses two diagnostic registers for error-related information.  Together, they contain information for testing and correcting errors.  Click on either diagnostic register in the list that follows for information about the contents of that register.

	CIA Diagnostic Control (CIA_DIAG)
	Diagnostic Check (DIAG_CHECK)


CIA Diagnostic Control Register
Diagnostic Registers
CIA Diagnostic Control Register

For Reads/Writes:

The CIA Diagnostic Control register (CIA_DIAG) forces errors so that those errors can be tested.

Click on the Description button to display the bit fields.


CIA_DIAG Register Bit Descriptions

FROM_WRT_EN	<0>	R/W	When set to 1, flashROM may be programmed.  When set to 0, writes to flashROM generate system machine checks.
USE_CHECK	<1>	R/W	When set to 1, direct memory access (DMA) write cycles can use the error-correction code contained in the Diagnostic Check register (DIAG_CHECK).
Reserved	<27:2>	R-O	N/A
FPE_PCI	<29:28>	R/W	Varies depending on the setting: 00     Outputs normal parity to the PCI. 01     Forces a parity error on the low 32 bits of the          PCI during data cycles. 10     Forces a parity error on the high 32 bits of the          PCI during data cycles. 11     Forces a parity error on the low and high 32 bits          of the PCI during address and data cycles.
Reserved	<30>	R-O	N/A
FPE_TO_EV5	<31>	R/W	When set to 1, forces a parity error on the CPU address/command bus when the CIA is the bus master.


Diagnostic Check Register
Diagnostic Registers
Diagnostic Check Register

For Reads/Writes:

The Diagnostic Check register (DIAG_CHECK) writes an error-correction code (ECC) pattern into memory during diagnostic direct memory access (DMA) write cycles.  (This register provides the ECC used by the USE_CHECK bit in the CIA Diagnostic Control register [CIA_DIAG].)

Click on the Description button to display the bit fields.


DIAG_CHECK Register Bit Descriptions

DIAG_CHECK	<7:0>	R/W	The ECC quadword used for diagnostic DMA write cycles
Reserved	<31:8>	R-O	N/A


Performance-Montoring
Control and Status Registers
Performance-Monitoring Registers

The AlphaStation 500 Series system uses two registers for monitoring system performance.  Together, they count and record various input/output activities.  Click on either performance-monitoring register in the list that follows for information about the contents of that register.

	Performance Monitor (PERF_MONITOR)
	Performance Monitor Control (PERF_CONTROL)


CIA Performance Control Register
Performance-Monitoring Registers
Performance Monitor Register

For Reads:

The Performance Monitor register (PERF_MONITOR) contains two 16-bit counters.  Programmable through the Performance Monitor Control register (PERF_CONTROL), each counter can count such events as EV5 read misses received by the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) and direct memory access (DMA) write transactions.

Note:	By specifying that HIGH_COUNT count the LOW_COUNT overflow, this register may be programmed as a single 32-bit counter.

Click on the Description button to display the bit fields.


PERF_MONITOR Register Bit Descriptions

LOW_COUNT	<15:0>	R-O	Value of the low counter
HIGH_COUNT	<31:16>	R-O	Value of the high counter


CIA Performance Control Register
Performance-Monitoring Registers
Performance Monitor Control Register

For Reads/Writes:

The Performance Monitor Control register (PERF_CONTROL) programs the counting activities for the Performance Monitor register (PERF_MONITOR).  It controls two different counter sequences--LOW_SELECT (bits 7 through 0) and HIGH_SELECT (bits 23 through 16).

Click on the Description button to display the bit fields.


PERF_CONTROL Register Bit Descriptions

LOW_SELECT	<7:0>	R/W	Encoding table for this byte
Reserved	<12:8>	R-O	N/A
LOW_COUNT_CLR	<13>	W-O	When set to 1, clears the low counter.
LOW_ERR_STOP	<14>	R/W	When set to 1, the low counter stops if the CIA detects an error.
LOW_COUNT_START	<15>	R/W	Initially set to 0 (does not count and keeps current values); when set to 1, starts the low counter.
HIGH_COUNT	<23:16>	R/W	Encoding table for this byte
Reserved	<28:24>	R-O	N/A
HIGH_COUNT_CLR	<29>	W-O	When set to 1, clears the high counter.
HIGH_ERR_STOP	<30>	R/W	When set to 1, the high counter stops if the CIA detects an error.
HIGH_COUNT_START	<31>	R/W	Initially set to 0 (does not count and keeps current values); when set to 1, starts the high counter.


Low/High_Select Bit Encodings
PERF_CONTROL Register
LOW_SELECT and HIGH_SELECT Bit Encoding

LOW_SELECT <7:0>
and
HIGH_SELECT <23:16>	Description
0000 0000	In LOW_SELECT, reserved.   In HIGH_SELECT, establishes the high counter as a 32-bit counter; HIGH_COUNT counts LOW_COUNT overflow.
0000 0001	Counts clock cycles; always increments.
0000 0010	Counts refresh cycles.
0001 0000	Counts EV5 commands acknowledged.
0001 0001	Counts EV5 read (modify or not-modify) commands.
0001 0010	Counts EV5 read-miss (not-modify) commands.
0001 0011	Counts EV5 read-miss (modify) commands.
0001 0100	Counts EV5 BCACHE_VICTIM commands acknowledged by the CIA.
0001 0101	Counts EV5 locks acknowledged by the CIA.
0001 0110	Counts EV5 memory barriers acknowledged by the CIA.
0001 0111	Counts EV5 FETCH or FETCH_M commands.
0001 1000	Counts EV5 write blocks.
0010 0000	Counts EV5 memory commands.
0010 0001	Counts EV5 I/O commands.
0010 0010	Counts EV5 I/O read commands.
0010 0011	Counts EV5 I/O write commands.
0010 0100	Counts CIA system read/flush commands issued.
0010 0101	Counts EV5 system read commands issued.
0010 0110	Counts EV5 system flush commands issued.
0010 0111	Counts NOACKs received by CIA.
0010 1000	Counts S-cache ACKs received by CIA.
0010 1001	Counts B-cache ACKs received by CIA.
0011 0000	Counts all DMA read (read; read-line; read-multiple) commands.
0011 0001	Counts only DMA read commands.
0011 0010	Counts only DMA read-line commands.
0011 0011	Counts only DMA read-multiple commands.
0011 0100	Counts all DMA write (write; write-and-invalidate) commands.
0011 0101	Counts only DMA write commands.
0011 0110	Counts only DMA write-and-invalidate commands.
0011 0111	Counts DMA dual-address cycles.
0011 1000	Counts DMA cycles on which the CIA issued a RETRY.
0011 1001	Counts I/O cycles on which the CIA issued a RETRY.
0100 0000	Counts established PCI bus locks.
0100 0001	Counts EV5 attempts to access a locked block.
0100 0010	Counts DMA statements (that cause a flush) on the victim address.
0101 0000	Counts refills of the translation lookaside buffer (TLB) by the CIA.
0100 0000	Counts single-bit error-correction codes (ECCs) detected.
all others	Reserved/unused; not counting.


Error-Reporting Registers
Control and Status Registers
Error-Reporting Registers

The AlphaStation 500 Series system uses several registers in its error-reporting activities.  These registers often contain information pertinent to solving system problems.  Click on any error-reporting register in the list that follows for information about the contents of that register.

	CPU_Error 0 (CPU_ERR0)
	CPU_Error 1 (CPU_ERR1)
	CIA_Error (CIA_ERR)
	CIA_Status (CIA STAT)
	CIA Error Mask (ERR_MASK)
	CIA Error Syndrome (CIA_SYN)
	CIA Memory Port Status 0 (MEM_ERR0)
	CIA Memory Port Status 1 (MEM_ERR1)
	PCI_Error Status 0 (PCI_ERR0)
	PCI Error Status 1 (PCI_ERR1)
	PCI Error Status 2 (PCI_ERR2)


CPU Error Information Register 0
Error-Reporting Registers
CPU Error 0 Register

For Reads:

The CPU Error 0 register (CPU_ERR0) contains the address bits of the CPU address/command bus when the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) detects an EV5-bus parity error.  This register remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the CPU Error 0 register leaves its contents undefined.

Click on the Description button to display bit fields.


CPU_ERR0 Register Bit Descriptions

Reserved	<3:0>	R-O	N/A
ADDR	<31:4>	R-O	Contains the current address on the CPU address/command bus in the event of an EV5 interface error


CPU Error Information Register 1
Error-Reporting Registers
CPU Error 1 Register

For Reads:

The CPU Error 1 register (CPU_ERR1) contains the mask-and-command field and the address field that remains on the CPU address/command bus when the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) detects an EV5-bus parity error.  This register remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the CPU Error 1 register leaves its contents undefined.

Click on the Description button to display bit fields.


CPU_ERR1 Register Bit Descriptions

ADDR <34:32>	<2:0>	R-O	Contains the address bits from the CPU address/command bus.
Reserved	<6:3>	R-O	N/A
ADDR <39>	<7>	R-O	Contains the address bit from the CPU address/command bus.
CMD	<11:8>	R-O	Contains the command from the CPU address/command bus.
INT_4_VALID	<15:12>	R-O	Contains the INT_4_VALID bits from the CPU address/command bus.
Reserved	<20:16>	R-O	N/A
ADDR_CMD_PAR	<21>	R-O	Contains the parity bit from the CPU address/command bus.
Reserved	<29:22>	R-O	N/A
FPE_2_EV5	<30>	R-O	Contains a copy of the CSR bit to force a parity error to the EV5.  For more information, see the description of FPE_2_EV5 in the CIA Diagnostic Control register (CIA_DIAG).
CPU_PE	<31>	R-O	When set to 1, the CPU interface detected a parity error.


CIA Error Register
Error-Reporting Registers
CIA Error Register

For Reads/Writes:

When the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC) detects an error condition, it logs pertinent error information in the CIA Error register (CIA_ERR).  All bits in this register, except the lost-error bits, are locked until a write to this register clears all error bits.

Note:	The lost-error bits are set only when the CIA detects an error and the CIA_ERR register is already locked.

Click on the Description button to display bit fields.


CIA_ERR Register Bit Descriptions

Error Bits:

COR_ERR	<0>	R/W	The CIA detected a correctable error.  This error applies only to direct memory accesses (DMAs), misses on the scatter/gather translation lookaside buffer, or I/O writes from the EV5.  (This error does not apply to CPU-to-memory reads; the EV5 detects such errors.  Nor does it apply to CPU-to-memory writes, because they are not checked.)
UN_COR_ERR	<1>	R/W	The CIA detected an uncorrectable error.  This error applies only to direct memory accesses (DMAs), misses on the scatter/gather translation lookaside buffer (TLB), or I/O writes from the EV5.  (This error does not apply to CPU-to-memory reads; the EV5 detects such errors.  Nor does it apply to CPU-to-memory writes, because they are not checked.)
CPU_PE	<2>	R/W	The CIA detected an EV5 bus parity error.
MEM_NEM	<3>	R/W	The CIA detected an attempt to access nonexistent memory.
PCI_SERR	<4>	R/W	The CIA detected a system error (SERR) on the PCI bus.
PERR	<5>	R/W	The CIA detected a data parity error on the  PCI bus.
PCI_ADDR_PE	<6>	R/W	The CIA detected an address parity error on the PCI bus.
RCVD_MAS_ABT	<7>	R/W	The PCI master-state machine generated a master abort.
RCVD_TAR_ABT	<8>	R/W	The PCI master-state machine received a target abort.
PA_PTE_INV	<9>	R/W	The CIA detected an invalid page table entry on a scatter/gather access.
FROM_WRT_ERR	<10>	R/W	A write to flashROM was attempted without first setting FROM_WRT_EN to 1.  For more information, see the description of FROM_WRT_EN in the CIA Diagnostic Control register (CIA_DIAG).
IOA_TIMEOUT	<11>	R/W	An I/O read/write failed to execute in 1 second, and an I/O time-out occurred.
Reserved	<15:12>	R-O	N/A

Lost-Error Bits:

Note:	The lost-error bits are set only when the CIA detects an error and the CIA_ERR register is already locked.
LOST_COR_ERR	<16>	R-O	The CIA detected a correctable error, but CIA_ERR was locked.
LOST_UN_COR_ERR	<17>	R-O	The CIA detected an uncorrectable error, but CIA_ERR was locked.
LOST_CPU_PE	<18>	R-O	The CIA detected a CPU parity error, but CIA_ERR was locked.
LOST_MEM_NEM	<19>	R-O	The CIA detected an attempt to access nonexistent memory, but CIA_ERR was locked.
Reserved	<20>	R-O	N/A
LOST_PERR	<21>	R-O	The CIA detected a data parity error on the PCI bus, but CIA_ERR was locked.
LOST_PCI_ADDR_PE	<22>	R-O	The CIA detected an address parity error on the PCI bus, but CIA_ERR was locked.
LOST_RCVD_MAS_ABT	<23>	R-O	The PCI master-state machine generated a master abort, but CIA_ERR was locked.
LOST_RCVD_TAR_ABT	<24>	R-O	The PCI master-state machine received a target abort, but CIA_ERR was locked.
LOST_PA_PTE_INV	<25>	R-O	The CIA detected an invalid page table entry on a scatter/gather access, but CIA_ERR was locked.
LOST_FROM_WRT_ERR	<26>	R-O	A write to flashROM was attempted without first setting FROM_WRT_EN to 1, but CIA_ERR was locked.  For more information, see the description of FROM_WRT_EN in the CIA Diagnostic Control register (CIA_DIAG).
LOST_IOA_TIMEOUT	<27>	R-O	An I/O time-out occurred because an I/O read/write failed to execute in 1 second, but CIA_ERR was locked.
Reserved	<30:28>	R-O	N/A
ERR_VALID	<31>	R-O	The CIA detected a valid error, but all CIA error registers are locked.


CIA Status Register
Error-Reporting Registers
CIA Status Register

For Reads:

The CIA Status register (CIA_STAT) contains status information related to the error stored in the CIA_Error register (CIA_ERR).  More specifically, this information reflects the status of the CIA at the time of error detection.

Click on the Description button to display bit fields.


CIA_STAT Register Bit Descriptions

PCI_STATUS <0>	<0>	R-O	When set to 1, the PCI target-state machine is active.
PCI_STATUS <1>	<1>	R-O	When set to 1, the PCI master-state machine is active.
Reserved	<2>	R-O	N/A
MEM_SOURCE	<3>	R-O	When set to 0, the memory-cycle source is the EV5.  When set to 1, the memory-cycle source is the PCI.
IOA_VALID	<7:4>	R-O	Contains the valid bits for the I/O command/address queue.
CPU_QUEUE	<10:8>	R-O	Contains the valid bits for the CPU command/address queue.
TLB_MISS	<11>	R-O	When set to 1, an error occurred during a refill on a translation lookaside buffer (TLB) miss.
DM_ST	<15:12>	R-O	These bits represent the state of the logic that moves data between the CIA and the data switch (DSW). Valid bit combinations and their meanings
PA_CPU_RES	<17:16>	R-O	Contains the EV5 response to the direct memory access (DMA):   00  No response 01  No ACK 10  S-cache hit 11  B-cache hit
Reserved	<31:18>	R-O	N/A


DM_ST Bit Allocation

Bit Combination	Definition
0000	Idle
0001	Restart DSW I/O write buffers
0010	I/O write
0110	DMA read or TLB miss
0111	DMA write
1000	I/O write to the GRU
1001	I/O read to the GRU
1010	I/O read to an internal CIA register
1011	I/O read to the PCI bus (32-bit or 64-bit)
others	Reserved


CIA Error Mask Register
Error-Reporting Registers
CIA Error Mask Register

For Reads/Writes:

The CIA Error Mask register (ERR_MASK) disables the error-detection and reporting feature.  For each bit, a 0 disables the detection and reporting of that error, and a 1 enables the detection and reporting of that error.

Click on the Description button to display the bit fields.


ERR_MASK Register Bit Descriptions

COR_ERR	<0>	R/W	Correctable errors
UN_COR_ERR	<1>	R/W	Uncorrectable errors
CPU_PE	<2>	R/W	CPU parity errors
MEM_NEM	<3>	R/W	Nonexistent-memory access errors
PCI_SERR	<4>	R/W	PCI system errors
PERR	<5>	R/W	PCI data parity errors
PCI_ADDR_PE	<6>	R/W	PCI address parity errors
RCVD_MAS_ABT	<7>	R/W	PCI master abort errors
RCVD_TAR_ABT	<8>	R/W	PCI target abort errors
PA_PTE_INV	<9>	R/W	Invalid page table entry errors
FROM_WRT_ERR	<10>	R/W	FlashROM write errors
IOA_TIMEOUT	<11>	R/W	I/O time-out errors


CIA Error Syndrome Register
Error-Reporting Registers
CIA Error Syndrome Register

For Reads:

The CIA Error Syndrome register (CIA_SYN) logs information pertaining to errors detected by error-correction code (ECC) checkers.  This register locks when a CIA error occurs and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the CIA Error Syndrome register leaves its contents undefined.

Click on the Description button to display data fields.


CIA_SYN Register Bit Descriptions

ECC_SYNDROME	<7:0>	R-O	Contains information logged by ECC checkers; otherwise, undefined.
Reserved	<31:8>	R-O	N/A


CIA Memory Port Status Register 0
Error-Reporting Registers
CIA Memory Port Status 0 Register

For Reads:

The CIA Memory Port Status 0 register (MEM_ERR0) contains the low-order address bits of the memory-port address bus at the time of a CIA-detected error.  This register locks and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the CIA Memory Port Status 0 register leaves its contents undefined.

Click on the Description button to display data fields.


MEM_ERR0 Register Bit Descriptions

Reserved	<3:0>	R-O	N/A
MEM_PORT_ADDR	<31:4>	R-O	Contains low-order address bits of the address in the memory port at the time of a CIA-detected error; otherwise, undefined.


CIA Memory Port Status Register 1
Error-Reporting Registers
CIA Memory Port Status 1 Register

For Reads:

The CIA Memory Port Status 1 register (MEM_ERR1) contains the high-order address bits of the memory-port address bus (as well as other information about the memory in effect) at the time of a CIA-detected error.  This register locks and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the CIA Memory Port Status 1 register leaves its contents undefined.

Click on the Description button to display data fields.


MEM_ERR1 Register Bit Description
MEM_ERR1 Register Bit Descriptions

MEM_PORT_ADDR <33:32>	<1:0>	R-O	Contains the high-order address bits of the address in the memory port at the time of a CIA-detected error.
Reserved	<6:2>	R-O	N/A
MEM_PORT_ADDR <39>	<7>	R/W	Contains high-order address bit <39>.
MEM_PORT_CMD	<11:8>	R-O	Contains the memory command when the error occurred. Valid bit combinations and their meanings
MEM_PORT_MASK	<15:12	R/W	Contains the mask bits in effect when the error occurred.
SEQ_ST	<19:16>	R/W	Contains the state of the memory sequencer when the error occurred. Valid bit combinations and their meanings
MEM_PORT_SOURCE	<20>	R/W	Indicates the source of the memory command--when set to 0, the CPU is the source; when set to 1, a direct memory access (DMA) is the source. Relationships between MEM_PORT_SOURCE and MEM_PORT_CMD
Reserved	<23:21>	R-O	N/A
SET_SEL_ENC	<28:24>	R/W	An encoded set select that indicates the memory set in effect when the error occurred. Valid bit combinations and their meanings
Reserved	<31:29>	R-O	N/A


MEM PORT CMD Encoding
MEM_PORT_CMD Encoding

MEM_PORT_CMD	MEM_PORT_SOURCE	Definition
011X	0	EV5 write block or EV5 write-block lock
10XX	0	EV5 read-miss or EV5 read-miss modify
1100	0	EV5 B-cache victim
111X	0	EV5 read-miss modify
10XX	1	DMA read or DMA read-modify
001X	1	DMA write
Others		Reserved


SEQ ST Encodings
SEQ_ST Encoding

Bit Combination	Definition
0000	Idle
0001	DMA read or DMA write
0010, 0011	EV5 read-miss (or EV5 read-miss modify) with victim
0100, 0101, 0110	EV5 read-miss (or EV5 read-miss modify) without victim
0111, 1000, 1001	Refresh
1100	Idle, waiting for pending DMA read
1110, 1111	Idle, precharging row-address select (RAS)
Others	Reserved


SET SEL ENC Encodings
SET_SEL_ENC Encoding

Bit Combination	Definition
00000	Set 0 selected	(DIMM bank 0)
00001	Set 1 selected	(DIMM bank 0)
00010	Set 2 selected	(DIMM bank 1)
00011	Set 3 selected	(DIMM bank 1)
00100	Set 4 selected	Reserved
00101	Set 5 selected	Reserved
00110	Set 6 selected	Reserved
00111	Set 7 selected	Reserved
01000	Set 8 selected	Reserved
01010	Set A selected	Reserved
01011	Set B selected	Reserved
01100	Set C selected	Reserved
01101	Set D selected	Reserved
01110	Set E selected	Reserved
01111	Set F selected	Reserved
10000	No set selected
11111	Refresh cycle


PCI Error Status 0 Register
Error-Reporting Registers
PCI Error Status 0 Register

For Reads:

CIA Revision 1 (AlphaStation 500)

CIA Revision 2 (AlphaStation 500)

The PCI Error Status 0 register (PCI_ERR0) contains information related to the state of the PCI interface at the time of an error (logged by the CIA when it detects the error).  Like all CIA error-reporting registers, this register locks and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the PCI Error Status 0 register leaves its contents unpredictable.

Note:	Some data fields in PCI_ERR0 contain information associated with the address stored in the PCI Error Status 1 register (PCI_ERR1), which holds information related to direct memory access (DMA) errors.  Other data fields in PCI_ERR0 contain information associated with the address stored in the PCI Error Status 2 register (PCI_ERR2),which holds information related to errors on the PCI bus.

Click on the Description button to display data fields.


PCI_ERR0 Register Bit Descriptions

Note: Be sure to check which CIA revision you have, then refer to the appropriate chart.

CIA Revision 1 (AlphaStation 500):

DMA_CMD	<3:0>	R-O	Associated with the address stored in PCI_ERR1, contains the PCI command of the current DMA.
LOCK_STATE	<4>	R-O	When set to 1, the CIA was locked when the it detected the error.
DMA_DAC	<5>	R-O	Associated with the address stored in PCI_ERR1, indicates that an error occurred during a PCI dual-address cycle (when set to 1).
Reserved	<7:6>	R-O	N/A
WINDOW	<11:8>	R-O	Associated with the address stored in PCI_ERR1, indicates the window selected by the PCI address: 0000   No window 0001   Window 0 0010   Window 1 0100   Window 2 1000   Window 3
Reserved	<15:12>	R-O	N/A
MASTER_STATE	<19:16>	R-O	Associated with the address stored in PCI_ERR2, indicates the master-state value:   0   Idle 1   Drive bus 2   Address-step cycle 3   Address cycle 4   Data cycle 5   Last read-data cycle 6   Last write-data cycle 7   Read stop cycle 8   Write stop cycle 9   Read turnaround cycle A   Write turnaround cycle B   Reserved C   Reserved D   Reserved E   Reserved F   Unknown state
TARGET_STATE	<22:20>	R-O	Associated with the address stored in PCI_ERR2, indicates the target state value:   0   Idle 1   Busy 2   Read-data cycle 3   Write-data cycle 4   Read stop cycle 5   Write stop cycle 6   Read turnaround cycle 7   Write turnaround cycle
Reserved	<23>	R-O	N/A
PCI_CMD	<27:24>	R-O	Associated with the address stored in PCI_ERR2, indicates the current PCI command.
PCI_DAC	<28>	R-O	Associated with the address stored in PCI_ERR2, indicates that an error occurred during a PCI dual-address cycle (when set to 1).
Reserved	<31:29>	R-O	N/A

CIA Revision 2 (AlphaStation 500):

DMA_CMD	<3:0>	R-O	Associated with the address stored in PCI_ERR1, contains the PCI command of the current DMA.
LOCK_STATE	<4>	R-O	When set to 1, the CIA was locked when the it detected the error.
DMA_DAC	<5>	R-O	Associated with the address stored in PCI_ERR1, indicates that an error occurred during a PCI dual-address cycle (when set to 1).
Reserved	<7:6>	R-O	N/A
WINDOW	<12:8>	R-O	Associated with the address stored in PCI_ERR1, indicates the window selected by the PCI address: 00000   No window 00001   Window 0 00010   Window 1 00100   Window 2 01000   Window 3 01000   Window 4 (Monster Window)
Reserved	<15:13>	R-O	N/A
MASTER_STATE	<19:16>	R-O	Associated with the address stored in PCI_ERR2, indicates the master-state value:   0   Idle 1   Drive bus 2   Address-step cycle 3   Address cycle 4   Data cycle 5   Last read-data cycle 6   Last write-data cycle 7   Read stop cycle 8   Write stop cycle 9   Read turnaround cycle A   Write turnaround cycle B   Reserved C   Reserved D   Reserved E   Reserved F   Unknown state
TARGET_STATE	<23:20>	R-O	Associated with the address stored in PCI_ERR2, indicates the target state value:   0   Idle 1   Busy 2   Read-data cycle 3   Write-data cycle 4   Read stop cycle 5   Write stop cycle 6   Read turnaround cycle 7   Write turnaround cycle 8   Read wait cycle 9   Write wait cycle A-E   Reserved F   Unknown state
PCI_CMD	<27:24>	R-O	Associated with the address stored in PCI_ERR2, indicates the current PCI command.
PCI_DAC	<28>	R-O	Associated with the address stored in PCI_ERR2, indicates that an error occurred during a PCI dual-address cycle (when set to 1).
Reserved	<31:29>	R-O	N/A


PCI Error Register 1
Error-Reporting Registers
PCI Error Status 1 Register

For Reads:

The CIA uses the PCI Error Status 1 register (PCI_ERR1) to log the PCI address for the current direct memory access (DMA) that pertains to an error logged in the PCI_Error Status 0 register (PCI_ERR0).  Like all CIA error-reporting registers, this register locks and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the PCI Error Status 1 register leaves its contents unpredictable.

Note:	The PCI_ERR1 register and some fields in PCI_ERR0 (DMA_CMD, DMA_DAC, and WINDOW) contain information related to the memory used while the CIA handles a DMA:        Correctable error (CIA_ERR<0>)      Uncorrectable error (CIA_ERR<1>)      Attempt to access nonexistent memory (CIA_ERR<3>)      Invalid page-table entry (CIA_ERR<9>)

Click on the Description button to display data fields.


PCI_ERR1 Register Bit Descriptions

DMA_ADDRESS<31:0>	<31:0>	R-O	Contains the DMA address <31:0>.
Note:	This register always captures DMA address <31:0>, even for a direct memory access (DMA) dual-address cycle (DAC).  The most significant PCI address--<39:32>--can be obtained from the W_DAC register; however, for the CIA to hit on the DAC, PCI address <63:40> must be set to 0.


PCI Error Status 2 Register
Error-Reporting Registers
PCI Error Status 2 Register

For Reads:

The CIA uses the PCI Error Status 2 register (PCI_ERR2) to log the PCI address that pertains to an error logged in the PCI_Error Status 0 register (PCI_ERR0).  Like all CIA error-reporting registers, this register locks and remains locked until a write to the CIA_Error register (CIA_ERR) clears all error bits.  Unlocking the PCI Error Status 2 register leaves its contents unpredictable.

Note:	The PCI_ERR2 register and some fields in PCI_ERR0 (MASTER_STATE, TARGET_STATE, PCI_CMD, and PCI_DAC) contain information related to the following errors associated with the PCI bus:        PCI data-parity error (CIA_ERR<5>)      PCI address-parity error (CIA_ERR<6>)      PCI master abort (CIA_ERR<7>)      PCI target abort (CIA_ERR<8>)      IOA time-out (CIA_ERR<11>)

Click on the Description button to display data fields.


PCI_ERR2 Register Bit Descriptions

PCI_ADDRESS<31:0>	<31:0>	R-O	Contains the PCI address <31:0>.
Note:	This register always captures PCI address <31:0>, even for a direct memory access (DMA) dual-address cycle (DAC).  The most significant PCI address--<39:32>--can be obtained from the W_DAC register; however, for the CIA to hit on the DAC, PCI address <63:40> must be set to 0.


Memory-Control Registers`
Control and Status Registers
Memory-Control Registers

The AlphaStation 500 Series system memory logic provides the row and column address for the memory banks, as well as all the control signals (for example, row address select [RAS], column address select [CAS], write enable, and memory enable).  The memory logic also provides control signals to the data switch (DSW) application-specific integrated circuit (ASIC) that specify when to send or strobe data to or from memory.  Lastly, this logic controls memory refreshes.

Several registers play a role in controlling the system memory.  Click on any memory-control register in the list that follows for information about the contents of that register.

	Memory Configuration (MCR)
	Memory Base Address (MBA0-MBAE)
	Memory Timing (TMG0-TMG2)


Memory Configuration Register
Memory-Control Registers
Memory Configuration Register

For Reads/Writes:

The Memory Configuration register (MCR) defines the system and memory configuration for the AlphaStation 500 Series system.  The system uses the contents of this register to configure the memory controller for the control, I/O, and addressing (CIA) application-specific integrated circuit (ASIC).

Click on the Description button to display data fields.


MCR Register Bit Descriptions
MCR Bit Descriptions

MEM_SIZE	<0>	R/W	The console firmware sets this bit; for the AlphaStation 500 Series system, this setting must be 1.  A 1 setting configures the memory port to a 256-bit data path (Remember that the tower memory boards must be populated identically to prevent an illegal configuration flag.)  A 0 setting configures the memory port to a 128-bit data path, which is not supported by the AlphaStation 500 Series system.
Reserved	<3:1>	R-O	N/A
CACHE_SIZE	<6:4>	R/W	Contains the cache size (as determined by the console firmware using the Cache and Memory Configuration register [CACHE_CNFG]) written before any memory cycles start.
Reserved	<7>	R-O	N/A
REF_RATE	<17:8>	R/W	Contains the value of the memory-refresh rate.  (Memory refreshes each time it reaches the specified value specified is reached.)  A setting of 0 disables memory refreshes.
REF_BURST	<19:18>	R/W	Controls dual inline memory module (DIMM) refresh quantitieshow many DIMMs and how many refreshes for each REF_RATE reached:   00   RAS all DIMMs at once, single refresh. 01   RAS all DIMMs at once, double refresh. 10   RAS one-half of the DIMMs, single refresh. 11   RAS one-half of the DIMMs, double refresh.
TMG_R0	<21:20>	R/W	Controls the nominal row-address setup rate:   00   15 nanoseconds 01   30 nanoseconds 10   45 nanoseconds 11   60 nanoseconds
LONG_CBR_CAS	<22>	R/W	Specifies the CAS pulse width for CAS-before-RAS refreshes:   0   60 nanoseconds 1   90 nanoseconds
Reserved	<25:23>	R-O	N/A
DLY_IDLE_BC	<27:26>	R/W	Specifies the delay allowed before B-cache must be free to receive data from memory:   00   One-cycle delay 01   Two-cycle delay 10   Three-cycle delay 11   Four-cycle delay Note:  These bits must be set to 00 if bit 29 specifies a zero-cycle delay.
Reserved	<28>	R-O	N/A
EARLY_IDLE_BC	<29>	R/W	When set to 1, specifies a zero-cycle delay for read data from memory to the CPU; otherwise, DLY_IDLE_BC (described previously) controls when B-cache must be free to receive data from memory.
Reserved	<31:30>	R-O	N/A


Memory Base Address Registers 0,2,4,6,8,A,C,E
Memory-Control Registers
Memory Base-Address Registers 0,2,4,6,8,A,C,E

For Reads/Writes:

CIA Revision 1 (AlphaStation 500)

CIA Revision 2 (AlphaStation 500)

The eight Memory Base-Address registers (MBA0,2,4,6,8,A,C,E) correspond to and control the eight memory banks supported by the CIA.  (The minimum bank size for each MBA register is 16 MB.)  Each MBA register contains a PATTERN field that, when compared with the incoming address, determines the memory bank being accessed.

Click on the Description button to display data fields.


MBA0,2,4,6,8,A,C,E Register Bit Descriptions

Note: Be sure to check which CIA revision you have, then refer to the appropriate chart.

CIA Revision 1 (AlphaStation 500)

S0_VALID	<0>	R/W	When set to 1, side 0 of the memory bank is valid.
ROW_TYPE	<2:1>	R/W	Specifies the row and column settings of the memory banks being referenced (for generating the memory-address map):   00   10 row 10 column 01   12 row 10 column or 11x11 10   13 row 11 column or 12x12 11   Reserved
Reserved	<3>	R/O	N/A
MASK	<8:4>	R/W	Indicates which bits to use when comparing PATTERN with the incoming memory-bank address, thereby indicating the size of the dual inline memory module (DIMM) in the corresponding memory bank.  For example, for a 256-bit memory data bus:    DIMM Size     MASK   Definition    4 or 8 MB      00001   Do not use <24> in comparison.   8 or  16 MB    00011   Do not use <25:24> in comparison. 16 or  32 MB    00111   Do not use <26:24> in comparison  32 or  64 MB    01111   Do not use <27:24> in comparison  64 or 128 MB   11111   Do not use <28:24> in comparison.
Reserved	<14:9>	R-O	N/A
S1_VALID	<15>	R/W	When set to 1, side 1 of the memory bank is valid.
PATTERN	<25:16>	R/W	Data compared with the incoming CPU address <33:24> to determine the memory bank being accessed.
Reserved	<27:26>	R-O	N/A
TMG_SEL	<29:28>	R/W	Specifies which Memory Timing register (TMG0-TMG2) to use:   00   TMG0, used for 50- and 60-nanosecond DIMMs 01   TMG1, used for 70-nanosecond DIMMs 10   TMG2, used for 80-nanosecond DIMMs 11   Reserved
Reserved	<31:30>	R-O	N/A

CIA Revision 2 (AlphaStation 500)

S0_VALID	<0>	R/W	When set to 1, side 0 of the memory bank is valid.
ROW_TYPE	<3:1>	R/W	Specifies the row and column settings of the memory banks being referenced (for generating the memory-address map):   000   10 row 10 column 001   12 row 10 column or 11x11 010   13 row 11 column or 12x12 011   10 row 10 column, 11x9, or 12x8 100   10 row 9 column 101   11 row 10 column 110   12 row 11 column 111   13 row 12 column
MASK	<8:4>	R/W	Indicates which bits to use when comparing PATTERN with the incoming memory-bank address, thereby indicating the size of the dual inline memory module (DIMM) in the corresponding memory bank.  For example, for a 256-bit memory data bus:    DIMM Size     MASK   Definition    4 or 8 MB      00001   Do not use <24> in comparison.   8 or  16 MB    00011   Do not use <25:24> in comparison. 16 or  32 MB    00111   Do not use <26:24> in comparison  32 or  64 MB    01111   Do not use <27:24> in comparison  64 or 128 MB   11111   Do not use <28:24> in comparison.
Reserved	<14:9>	R-O	N/A
S1_VALID	<15>	R/W	When set to 1, side 1 of the memory bank is valid.
PATTERN	<25:16>	R/W	Data compared with the incoming CPU address <33:24> to determine the memory bank being accessed.
Reserved	<27:26>	R-O	N/A
TMG_SEL	<29:28>	R/W	Specifies which Memory Timing register (TMG0-TMG2) to use:   00   TMG0, used for 50- and 60-nanosecond DIMMs 01   TMG1, used for 70-nanosecond DIMMs 10   TMG2, used for 80-nanosecond DIMMs 11   Reserved
Reserved	<31:30>	R-O	N/A


Memory Timing Registers
Memory-Control Registers
Memory Timing Registers

For Reads/Writes:

The Memory Timing registers (TMG0, TMG1, and TMG2) contain the timing parameters that control the memory sequencer.

Because this register contains more data than can be displayed here, click on the Description button to display the bit fields and access a more thorough explanation.


TMG0-TMG2 Register Bit Descriptions
TMG0,1,2 Register Bit Descriptions

TMG_R1	<1:0>	R/W	Read starting--data delay: 00   30 nanoseconds 10   60 nanoseconds
TMG_R2	<3:2>	R/W	Read--row-address hold: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_R3	<5:4>	R/W	Read--cycle time: 00   60 nanoseconds 10   90 nanoseconds
TMG_R4	<7:6>	R/W	Read--CAS assertion delay: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_R5	<9:8>	R/W	Read--CAS pulse width: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_R6	<11:10>	R/W	Read--column-address hold: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_W1	<13:12>	R/W	Write--data delay: 00   30 nanoseconds 10   60 nanoseconds
TMG_W4	<16:14>	R/W	Write--CAS assertion delay: 000   60 nanoseconds 001   75 nanoseconds 010   90 nanoseconds 011   105 nanoseconds 100   120 nanoseconds 101   135 nanoseconds
TMG_PRE	<17>	R/W	RAS--precharge delay: 0   0 nanoseconds 1   30 nanoseconds
TMG_V3	<19:18>	R/W	Victim/Write--cycle time: 00   60 nanoseconds 10   90 nanoseconds
TMG_V4	<22:20>	R/W	Linked victim--CAS assertion delay: 000   60 nanoseconds 001   75 nanoseconds 010   90 nanoseconds 011   105 nanoseconds 100   120 nanoseconds 101   135 nanoseconds
Reserved	<23>	R-O	N/A
TMG_V5	<25:24>	R/W	Victim/Write--CAS pulse width: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_V6	<27:26>	R/W	Victim/Write--column-address hold: 00   30 nanoseconds 01   45 nanoseconds 10   60 nanoseconds 11   75 nanoseconds
TMG_RV	<29:28>	R/W	Read-to-Victim--start delay, then PCI_MEM_EN assertion delay: 00   0 nanoseconds, then 15 nanoseconds 01   0 nanoseconds, then 30 nanoseconds 10   30 nanoseconds, then 45 nanoseconds 11   30 nanoseconds, then 60 nanoseconds
TMG_RD_DLY	<31:30>	R/W	Read--data delay (affects DSW): 00   0 nanoseconds 01   15 nanoseconds 10   30 nanoseconds 11   45 nanoseconds


PCI Address-Related Registers
Control and Status Registers
PCI Address-Related Registers

Incoming peripheral component interconnect (PCI) addresses must be mapped to the 8-GB CPU cached memory--using either direct mapping (physical mapping with an address offset) or scatter/gather mapping (virtual mapping).  The AlphaStation 500 Series system provides four programmable address windows (called PCI target windows) that control peripheral access to system memory.  Associated with each window are three registers:

	Window Base (W_BASE)
	Window Mask (W_MASK)
	Translated Base (T_BASE)

Another register--Window DAC Base (W_DAC) --is used for PCI 64-bit addressing (in other words, dual-address cycles or DACs).  It is associated with only one of the PCI target windows,

The final register in the PCI address-related category is Scatter/Gather Translation Buffer Invalidate (SG_TBIA).  It maintains the coherency of the translation lookaside buffer (TLB).

Click on any previously mentioned PCI address-related register for information about the contents of that register.


Scatter/Gather Translation Buffer Invalidate Register
PCI Address-Related Registers
Scatter/Gather Translation Buffer Invalidate Register

For Writes:

Writes to the Scatter/Gather Translation Buffer Invalidate register (SG_TBIA) mark the specified group of scatter/gather TLB TAGs as invalid and unlocked.

Click on the Description button to display data fields.


TBIA Register Bit Descriptions
SG_TBIA Register Bit Descriptions

SG_TBIA<1:0>	<1:0>	W-O	Writing to this area invalidates the scatter/gather translation buffers.  The valid bit combinations are:   00   No operation 01   Invalidate and unlock all locked TLB TAGs 10   Invalidate unlocked TLB TAGs 11   Invalidate and unlock all TLB TAGs
Reserved	<31:2>	R-O	N/A


Window Base Registers
PCI Address-Related Registers
Window Base Registers

For Reads/Writes:

The Window Base registers (W_BASE[0], W_BASE[1], W_BASE[2], and W_BASE[3]) provide the base address for a particular target window.  These registers should not be modified unless software ensures that no PCI traffic is scheduled for the window being modified.

Click on the Description button to display data fields.


Wx_BASE, x=0-3 Register Bit Descriptions
Wx_BASE (x=0,1,2,3) Register Bit Descriptions

W_EN	<0>	R/W	When set to 1, the PCI target window is enabled and used in response to PCI-initiated transfers that match the address range of the target window.
Wx_BASE_SG	<1>	R/W	When set to 1, the PCI target window uses scatter/gather mapping to translate a PCI address to a physical memory address. PCI address-translation table for enabling scatter/gather mapping When set to 0, the PCI target window uses direct mapping to translate a PCI address to a CPU address. PCI address-translation table for disabling scatter/gather mapping
MEMCS_enable (only in W0_BASE)	<2>	R/W	When set to 1, the MEMCS signal from the PCI-to-EISA bridge (PCEB) is AND'd with the window match.
DAC_enable (only in W3_BASE)	<3>	R/W	When set to 1, the W_DAC register is compared against PCI address <39:32> for a PCI DAC.  If the compare matches and the 32-bit section of the PCI address matches, then a dual-address cycle (DAC) occurs.
Reserved	<19:4>	R-O	N/A
W_BASE	<31:20>	R/W	Indicates the PCI base address of the PCI target window and determines the type of match in that window.


Window Mask Registers
PCI Address-Related Registers
Window Mask Registers

For Reads/Writes:

The Window Mask registers (W_MASK[0], W_MASK[1], W_MASK[2], and W_MASK[3]) provide a mask that maps to bits <31:20> of an incoming PCI address.  The size of each window can be programmed from 1 MB to 4 GB in powers of two by masking the incoming bits using this register as indicated in the PCI target window sizing table.

Click on the Description button to display the data fields.


Wx_MASK, x=0-3 Register Bit Descriptions
Wx_MASK (x=0,1,2,3) Register Bit Descriptions

Reserved	<19:0>	R-O	N/A
W_MASK	<31:20>	R/W	Specifies the size of the PCI target window and masks out address bits not used when determining a PCI target-window match. Bit combinations that determine target-window size


Scatter/Gather Mapping Enabled Table

W_MASK<31:20>	S/G Map Table Size	S/G Map Address<33:0>  (used to index S/G table in memory)
0000 0000 0000	1 KB	T_BASE<33:10> to PCI_AD_H<19:13>:000
0000 0000 0001	2 KB	T_BASE<33:11> to PCI_AD_H<20:13>:000
0000 0000 0011	4 KB	T_BASE<33:12> to PCI_AD_H<21:13>:000
0000 0000 0111	8 KB	T_BASE<33:13> to PCI_AD_H<22:13>:000
0000 0000 1111	16 KB	T_BASE<33:14> to PCI_AD_H<23:13>:000
0000 0001 1111	32 KB	T_BASE<33:15> to PCI_AD_H<24:13>:000
0000 0011 1111	64 KB	T_BASE<33:16> to PCI_AD_H<25:13>:000
0000 0111 1111	128 KB	T_BASE<33:17> to PCI_AD_H<26:13>:000
0000 1111 1111	256 KB	T_BASE<33:18> to PCI_AD_H<27:13>:000
0001 1111 1111	512 KB	T_BASE<33:19> to PCI_AD_H<28:13>:000
0011 1111 1111	1 MB	T_BASE<33:20> to PCI_AD_H<29:13>:000
0111 1111 1111	2 MB	T_BASE<33:21> to PCI_AD_H<30:13>:000
1111 1111 1111	4 MB	T_BASE<33:22> to PCI_AD_H<31:13>:000


Scatter/Gather Mapping Disabled Table

W_MASK<31:20>	Translated  Address<33:0>	Unused Translated Base Register Bits
0000 0000 0000	T_BASE<33:20> to PCI_AD_H<19:0>	T_BASE<19:10>
0000 0000 0001	T_BASE<33:21> to PCI_AD_H<20:0>	T_BASE<20:10>
0000 0000 0011	T_BASE<33:22> to PCI_AD_H<21:0>	T_BASE<21:10>
0000 0000 0111	T_BASE<33:23> to PCI_AD_H<22:0>	T_BASE<22:10>
0000 0000 1111	T_BASE<33:24> to PCI_AD_H<23:0>	T_BASE<23:10>
0000 0001 1111	T_BASE<33:25> to PCI_AD_H<24:0>	T_BASE<24:10>
0000 0011 1111	T_BASE<33:26> to PCI_AD_H<25:0>	T_BASE<25:10>
0000 0111 1111	T_BASE<33:27> to PCI_AD_H<26:0>	T_BASE<26:10>
0000 1111 1111	T_BASE<33:28> to PCI_AD_H<27:0>	T_BASE<27:10>
0001 1111 1111	T_BASE<33:29> to PCI_AD_H<28:0>	T_BASE<28:10>
0011 1111 1111	T_BASE<33:30> to PCI_AD_H<29:0>	T_BASE<29:10>
0111 1111 1111	T_BASE<33:31> to PCI_AD_H<30:0>	T_BASE<30:10>
1111 1111 1111	T_BASE<33:32> to PCI_AD_H<31:0>	T_BASE<31:10>


PCI Target Window Sizing Table

W_MASK<31:20>	Size of Window
0000 0000 0000	1 MB
0000 0000 0001	2 MB
0000 0000 0011	4 MB
0000 0000 0111	8 MB
00000000 1111	16 MB
0000 0001 1111	32 MB
0000 0011 1111	64 MB
0000 0111 1111	128 MB
0000 1111 1111	256 MB
0001 1111 1111	512 MB
0011 1111 1111	1 GB
0111 1111 1111	2 GB
1111 1111 1111	4 GB
Other values	Unsupported


Translated Base Registers
PCI Address-Related Registers
Translated Base Registers

For Reads/Writes:

The Translated Base registers (T0_BASE, T1_BASE, T2_BASE, and T3_BASE)--one for each PCI target window--map PCI addresses into memory.  These registers should not be modified unless software ensures that no PCI traffic is scheduled for the window being modified.

Click on the Description button to display data fields.


TX_BASE,x=0-3 Register Bit Descriptions
Tx_BASE (x=0,1,2,3) Register Bit Descriptions

Reserved	<9:0>	R-O	N/A
T_BASE	<33:10>	R/W	When scatter/gather mapping is disabled, specifies the base CPU address of the translated PCI address for the PCI target window. PCI address-translation table for disabling scatter/gather mapping When scatter/gather mapping is enabled, specifies the base CPU address for the scatter/gather mapping table for the PCI target window. PCI address-translation table for enabling scatter/gather mapping


Window DAC Base Register
PCI Address-Related Registers
Window DAC Base Register

For Reads/Writes:

The Window DAC Base register (W_DAC) provides the <7:0> address bits for comparison against PCI address <39:32> during a dual-address cycle (DAC).  The DAC_BASE register is also used with this register; however, it applies only to window 3 (provided that it is enabled by the DAC_enable bit in W_BASE[3]).

Click on the Description button to display data fields.


W_DAC Register Bit Descriptions

DAC_BASE	<7:0>	R/W	Specifies bits <39:32> of the PCI base address used to determine a match in the target window for a dual-address cycle.
Reserved	<31:8>	R-O	N/A


Scatter/Gather Address-Translation Registers
Control and Status Registers

Scatter/Gather Address-Translation Registers

When scatter/gather mapping is enabled, the PCI address indicates the address of a page table entry that contains the physical address of that page.  The actual scatter/gather map is stored in memory.  To improve scatter/gather operation performance, the PCI bridge incorporates an eight-entry translation lookaside buffer (TLB) that increases address translation speed.

The AlphaStation 500 Series system uses three address-translation registers for scatter/gather mapping.  Click on any scatter/gather address-translation register in the list that follows for information about the contents of that register.

	Lockable Translation Buffer TAG (LTB_TAGx)
	Translation Buffer TAG (TB_TAGx)
	Translation Buffer and Page (TBx_PAGEn)


Lockable Translation Buffer Tag Registers
Scatter/Gather Address-Translation Registers
Lockable Translation Buffer TAG Registers

For Reads/Writes:

The Lockable Translation Buffer TAG registers (LTB_TAG0, LTB_TAG1, LTB_TAG2, and LTB_TAG3) allow software to write to them.  Furthermore, they can be locked such that the hardware cannot discard entries on a scatter/gather translation lookaside buffer (SG_TLB) miss.

Click on the Description button to display data fields.


LTB_TAG0 - LTB_TAG3 Register Bit Descriptions
LTB_TAG0,1,2,3 Register Bit Descriptions

VALID	<0>	R/W	When set to 1, used for address translation (provided that CIA_CTLR[SG_TLB_EN] is also set to 1).
LOCKED	<1>	R/W	When set to 1, the hardware cannot discard (overwrite) this entry.
DAC	<2>	R/W	When set to 1, this TAG entry corresponds to a 64-bit PCI address (on a dual-address cycle).  When set to 0, this TAG entry corresponds to a 32-bit PCI address (on a single-address cycle).
Reserved	<14:3>	R-O	N/A
TB_TAG	<31:15>	R/W	Represents the TAG for each translation buffer entry.


Translation Buffer Tag Registers
Scatter/Gather Address-Translation Registers
Translation Buffer TAG Registers

For Reads/Writes:

The Translation Buffer TAG registers (TB_TAG0, TB_TAG1, TB_TAG2, and TB_TAG3) allow software to write to them.  However, they cannot be locked; hardware can discard entries on a scatter/gather translation lookaside buffer (SG_TLB) miss.

Click on the Description button to display data fields.


TB_TAG0 - TB_TAG3 Register Bit Descriptions
TB_TAG0,1,2,3 Register Bit Descriptions

VALID	<0>	R/W	When set to 1, used for address translation (provided that CIA_CTLR[SG_TLB_EN] is also set to 1).
Reserved	<1>	R-O	N/A
DAC	<2>	R/W	When set to 1, this TAG entry corresponds to a 64-bit PCI address (on a dual-address cycle).  When set to 0, this TAG entry corresponds to a 32-bit PCI address (on a single-address cycle).
Reserved	<14:3>	R-O	N/A
TB_TAG	<31:15>	R/W	Represents the TAG for each translation buffer entry.


Translation Buffer Page Register
Scatter/Gather Address-Translation Registers
Translation Buffer and Page Registers

For Reads/Writes:

The AlphaStation 500 Series system contains 32 Translation Buffer and Page registers (4 for each of the 8 translation buffer entries).  The CIA automatically updates these registers (four at a time) on a TLB miss.

Click on the Description button to display data fields.


TBx_PAGEn Register Bit Descriptions

VALID	<0>	R/W	When set to 1, indicates that the page table entry is valid.
PAGE_ADDRESS	<21:11>	R/W	Forms the physical address <33:13>.  PCI_AD_H <12:0> forms the physical address <12:0>.  For the AlphaStation 500 Series system, physical address <33> must be set to 0.
Reserved	<31:22>	R-O	N/A


GRU-Related CSRs
Control and Status Registers

GRU-Related Registers

The GRU is a group of application-specific integrated circuit (ASIC) control and configuration registers consisting of:

	Interrupt Request (INT_REQ)
	Interrupt Mask (INT_MASK)
	Interrupt Level/Edge Select (INT_EDGE)
	Interrupt High/Low Select (INT_HILO)
	Interrupt Clear (INT_CLEAR)
	Cache and Memory Configuration (CACHE_CNFG)
	Reset (RESET)

Click on any GRU-related register in the preceding list for information about the contents of that register.


Interrupt Request Register
GRU-Related Registers
Interrupt Request Register

For Reads:

The Interrupt Request register (INT_REQ) reads the interrupt request lines from the GRU main interrupt logic..  Any bit set to 1 activates that particular interrupt.

Click on the Description button to display data fields.


INT_REQ Register Bit Descriptions

INT_REQ	<31:0>	R-O	Defines the interrupt request lines from the main interrupt logic (in the GRU).   Bit assignments for interrupts


Main Interrupt Logic IRQ Assignments

Output	IRQ	Interrupt	Usage
EV5 IRQ <1>	0 1 2 3	A B C D	PCI I/O riser slot 2 (32-bit); J4; PCI slot 11
	4 5 6 7	A B C D	PCI I/O riser slot 1 (32-bit); J3: PCI slot 12
	8 9 10 11	A B C D	PCI I/O riser slot 0 (64-bit); J1; PCI slot 7
	12		SCSI controller, PCI slot 9
	13		Ethernet controller, PCI slot 6
	15-14		Reserverd
	16 17 18 19	A B C D	PCI I/O riser slot 3 (32-bit); J5; PCI slot 8
	20		Alternate console
	21		Secure console
	22-23		Reserved
	27-24		Module REV
	30-28		Reserverd
	31	EISA_INT	8259 INT output


Interrupt Mask Register
GRU-Related Registers
Interrupt Mask Register

For Reads/Writes:

The Interrupt Mask register (INT_MASK) accesses the interrupt mask register that is located in the GRU main interrupt logic..  The main interrupt logic has 32 inputs, all of which can be masked individually.

Click on the Description button to display data fields.


INT_MASK Register Bit Descriptions

INT_MASK	<31:0>	R/W	When set to 1, enables interrupt request input.


Interrupt Level/Edge Select Register
GRU-Related Registers
Interrupt Level/Edge Select Register

For Reads/Writes:

The Interrupt Level/Edge Select register (INT_EDGE)controls the GRU main interrupt logic;; it signifies whether the interrupt-request line is an edge-type line (in other words, pulse) or a level-type line (standard PCI).

Note:	Because the AlphaStation 500 Series system requires that all IRQ lines be set to level-type, all bits must be set to 0.

Click on the Description button to display data fields.


LEVEL_EDGE Register Bit Descriptions

LEVEL_EDGE	<31:0>	R/W	Indicates the type the IRQ line.  When set to 1, the IRQ line is an edge-sensitive (ISA-type) line.


Interrupt High/Low Select Register
GRU-Related Registers
Interrupt High/Low Select Register

For Reads/Writes:

The Interrupt High/Low Select register (INT_HILO) controls the GRU main interrupt logic;; it indicates whether the IRQ is active high (PCI-to-EISA bridge interrupt) or active low (standard PCI interrupt).

Note:	The AlphaStation 500 Series system requires that bits 0-20 be set to 0; Bit 31 must be set to 1.

Click on the Description button to display data fields.


INT_HILO Register Bit Descriptions

INT_HILO	<31:0>	R/W	Indicates whether the IRQ line is active high or active low.  When set to 1, the IRQ line is active high.


Interrupt Clear Register
GRU-Related Registers
Interrupt Clear Register

For Reads/Writes:

The Interrupt Clear register (INT_CLEAR) accesses the interrupt mask register that is located in the GRU main interrupt logic..  The main interrupt logic has 32 inputs, all of which can be cleared individually.

Note:	If an interrupt occurs while INT_CLEAR is set to 1, the interrupt will be masked.

Click on the Description button to display data fields.


INT_CLEAR Register Bit Descriptions

INT_CLEAR	<31:0>	R/W	When set to 1, clears the interrupt.


Cache and Memory Configuration Register
GRU-Related Registers
Cache and Memory Configuration Register

For Reads:

The Cache and Memory Configuration register (CACHE_CNFG) contains the clock divisor information.  The console firmware uses the information in this register to configure the B-cache.

Click on the Description button to display data fields.


CACHE_CNFG Register Bit Descriptions

Reserved	<3:0>	R-O	N/A
CLOCK_DIVISOR	<7:4>	R-O	When set to 1, drives the clock divisor onto the IRQ lines during reset in order to program the EV5 system clock ratio.
Reserved	<10:8>	R-O	N/A
Reserved	<12:11>	R-O	N/A
Reserved	<15:13>	R-O	N/A
Reserved	<31:16>	R-O	N/A


Reset Register
GRU-Related Registers
Reset Register

For Writes:

When set to the hexadecimal 0000DEAD, induces a system reset.

Click on the Description button to display data fields.


RESET Register Bit Descriptions

RESET	<31:0>	W-O	When set to the hexadecimal 0000DEAD, induces a system reset.


EV5 System-Specific Configuration Registers
Control and Status Registers
EV5 System-Specific Configuration Registers

The AlphaStation 500 Series system uses three EV5 system-specific configuration registers for controlling cache-memory behavior.  Click on any register in the list that follows for information about the contents of that EV5 register.

	S-Cache Control (SC_CTL)
	B-Cache Control (BC_CONTROL)
	B-Cache Configuration (BC_CONFIG)


SCache Control Register
EV5 System-Specific Configuration Registers
S-Cache Control Register

For Reads/Writes:

Data in the S-Cache Control register (SC_CTL) controls the behavior of the S-cache.

Click on the Description button to display data fields.


SC_CTL Register Bit Descriptions

SC_FHIT	<0>	R/W
SC_FLUSH	<1>	R/W
SC_TAG_STAT<5:0>	<2:7>	R/W
SC_FP_DP<3:0>	<1:18>	R/W
SC_BLK_SIZE	<12>	R/W	The only data field of interest for system initialization, this bit must remain set.  (The AlphaStation 500 Series system B-cache uses a 64-byte block size; the S-cache and B-cache must use the same block size.)
SC_SET_EN<2:0>	<15:13>	R/W
Reserved	<63:16>	R-O


Bcache Control Register
EV5 System-Specific Configuration Registers
B-Cache Control Register

For Writes:

The B-Cache Control register (BC_CONTROL) controls the behavior of the B-cache.

Click on the Description button to display data fields.


BC_CONTROL Register Bit Description
BC_CONTROL Register Bit Descriptions

BC_ENABLED	<0>	W-O	When set to 1, enables the external B-cache.   When set to 0 (disabling B-cache), the bus interface unit (BIU) will not perform external-cache reads or writes. A reset clears this bit.
			Note:  This bit must be set to 1 before the DECchip 21164-AA performs the first cache read or write from either the B-cache or the system.  Although the AlphaStation 500 Series system functions partially with the B-cache disabled, it does not check DMA addresses against Write Block commands in the CIA's CPU queue (causing a potential for data from memory that is not current).
Reserved	<1>	W-O	This bit must be set to 0.
EI_OPT_CMD0	<2>	W-O	When set to 1, sends the optional LOCK and SET_DIRTY CIA commands  to DECchip 21164-AA for recognition by the system interface. When set to 0, DECchip 21164-AA acknowledges LOCK and SET_DIRTY internally, but does not forward them to the system interface.   A reset clears this bit.
			Note:  Because the AlphaStation 500 Series system does not use LOCK or SET_DIRTY, this bit must be clear before DECchip 21164-AA performs the first cache read or write from either the B-cache or the system.
EI_OPT_CMD1	<3>	W-O	When set to 1, sends the optional MB (memory barrier) CIA command (enabled in the CIA Acknowledgment Control register [CACK_EN]) to DECchip 21164-AA for recognition by the system interface. When set to 0, DECchip 21164-AA acknowledges EV5 memory barriers internally, but does not forward them to the system interface.   A reset clears this bit.
			Note:  The AlphaStation 500 Series system does not require MB commands, so this bit can remain cleared.
CORR_FILL_DAT	<4>	W-O	Contains correct-fill data (in error-correction code [ECC] mode) either from the B-cache or from system memory.  When set to 1, error-correction logic checks the fill data before transferring it to the S-cache or the D-cache; if an error is correctable, it is transparent to the system.   When set to 0, correct-fill data transfers directly to the D-cache before ECC detection; if an error is correctable, corrected data returns again, invalidating D-cache and taking an error trap. A reset clears this bit.
			Note:  Because the AlphaStation 500 Series system does not correct fill data, this bit should be set to 1.
VTM_FIRST	<5>	W-O	When set to 1, set for systems without a victim buffer.  Because the AlphaStation 500 Series system uses a victim buffer, this bit must be set to 0 for maximum system performance.
EI_ECC_OR_PARITY	<6>	W-O	Determines whether to operate the external interface in quadword ECC mode or byte-parity mode. A reset does not clear this bit.
			Note:  Because the AlphaStation 500 Series system provides ECC only, this bit must be set to 1 before DECchip 21164-AA performs the first cache read or write from either the B-cache or the system.
BC_FHIT	<7>	W-O	When set to 1 (with B-cache enabled), forces all external references in cached spaces to hit B-cache, regardless of tag-status bits. A reset clears this bit.
			Note:  To bypass the system interface during clean-to-dirty transitions, set EI_OPT_CMD0 (BC_CONTROL<2>) to 0 before using this diagnostic self-test feature.
BC_TAG_STAT	<12:8>	W-O	Available only in B-cache force-hit mode (BC_FHIT set to 1), allows passage of any combination of tag-status and parity bits to the B-cache for diagnostic testing.  A reset leaves these bits undefined. Descriptions of B-cache tag-status bits
BC_BAD_DAT	<14:13>	W-O	When set to 1, this diagnostic testing area can write invalid data (with correctable or uncorrectable errors) in ECC mode.  Setting bit <13> inverts data bits <0> and <64>; setting bit <14> inverts data bits <1> and <65>.  A reset clears these bits.
EI_DIS_ERR	<15>	W-O	When set to 1, DECchip 21164-AA ignores any ECC or parity errors on correct-fill data received either from the B-cache or from system memory.  It also ignores any B-cache tag or control parity error is ignored.   A reset sets this bit to 1.
			Note:  The AlphaStation 500 Series system requires that both B-cache and memory initialize error-free before enabling error-checking.  This bit must not be cleared until B-cache and memory initialization completes.
TL_PIPE_LATCH	<16>		When set to 1, DECchip 21164-AA pipes the system-control pins ADDR_BUS_REQ_H, CACK_H, and DACK_H for one CPU cycle. A reset clears this bit.
			Note:  The AlphaStation 500 Series system does not use this feature; this bit should remain cleared.
WAVE_PIPING	<18:17>	W-O	Indicates to the BIU the number of wave-pipelining cycles to use during private B-cache reads.  (As many as four CPU cycles are allowed.) A system startup initializes these values to 0 CPU cycles.


BC_TAG_STAT Bit Combination Table

B-Cache Tag-Status Bit	Description
12	Parity for B-cache tag
11	Parity for B-cache tag-status bits
10	B-cache tag valid bit
9	B-cache tag shared bit
8	B-cache tag dirty bit


Bcache Configuration Register
EV5 System-Specific Configuration Registers
B-Cache Configuration Register

For Writes:

The B-Cache Configuration register (BC_CONFIG) contains data used for configuring the B-cache.

Click on the Description button to display data fields.


BC_CONFIG Register Bit Descriptions

BC_SIZE	<2:0>	W-O	Indicates the size of the B-cache.  At system startup, the B-cache size is 1 MB. Valid values for B-cache size
			Note:  This data field should be set before initialization of the B-cache and system memory.
Reserved	<3>	W-O	This bit must be set to 0.
BC_RD_SPD	<7:4>	W-O	Indicates to the BIU the read access time of the B-cache (in CPU cycles).  This speed must be between 4 (setting at system startup) and 10 cycles.  The AlphaStation 500 Series system can accept B-cache RAM speeds of 8, 10,12, and 15 nanoseconds.
			Note:  This data field should be set before initialization of the B-cache and system memory.
BC_WR_SPD	<11:8>	W-O	Indicates to the BIU the write access time of the B-cache (in CPU cycles).  This speed must be between 4 (setting at system startup) and 10 cycles.  The AlphaStation 500 Series system can accept B-cache RAM speeds of 8, 10,12, and 15 nanoseconds.
			Note:  This data field should be set before initialization of the B-cache and system memory.
BC_RD_WR_SPC	<14:12>	W-O	Indicates to the BIU the number of CPU cycles to wait before switching from a private-read to a private-write B-cache transaction.  (The system-startup default is 1 cycle.)  This field must be set before DECchip 21164-AA performs the first cache read or write from either the B-cache or the system.
Reserved	<15>	W-O	This bit must be set to 0.
FILL_WE_OFFSET	<18:16>	W-O	Contains the B-cache write enable pulse offset value (from the Sysclock edge) used to supply fill information from the system.  The value in this field can range from 1 to 7 CPU cycles; however, it must never exceed the Sysclock ratio.  (The system-startup default is 1 cycle.)  This field must be set before DECchip 21164-AA performs the first cache read or write from either the B-cache or the system.
Reserved	<19>	W-O	This bit must be set to 0.
BC_WE_CTL	<28:20>	W-O	Controls the timing of the write enable during a write or fill.  When set to 1, the write pulse is started.  Each bit in this bit field corresponds to a particular CPU cycle.  A system startup clears all bits in this field.
Reserved	<32:29>	W-O	This field must be set to 0.


BC_SIZE Cache Sizes Table

B-Cache Size <2:0>	Definition
000	Invalid
001	1 MB
010	2 MB
011	4 MB
100	8 MB
101	16 MB
110	32 MB
111	64 MB


Troubleshooting
Troubleshooting the Digital AlphaStation 500 Series System
Click on the appropriate button to view the area of interest.


Troubleshooting Strategy
Troubleshooting
Gathering Information

A successful troubleshooting strategy requires a plan of attack.  Gathering information is the first action to perform.  Use the site log to review the system's service history.  Ask the user or customer contact the following questions:

	What first alerted the user to the problem?
	Were any changes or upgrades applied recently to the operating system, firmware, or application software?
	What symptoms did the user notice?  Were there any unusual sounds or smells?
	Did the user make any initial troubleshooting efforts?  What were the results?
	Is the operating system functioning?
-	If the answer is no, use the power-on self-test (POST) and other loadable diagnostics.
-	If the answer is yes, gather information from log files such as the error log , operator log, and crash dump files.  Run the operating system-based diagnostics program, DEC VET.


Troubleshooting Process
A Troubleshooting Strategy


Power System Troubleshooting

Click on the  button to display a power troubleshooting checklist.

Click here to see the location of the power indicator lights

Click here to see the location of the system power switch


Indicator Lights

There are two indicator lights on the front of the Alphasystem 500 series systems.  The left-hand light indicateds SCSI bus activity; the right-hand light is the power on indicator.


Power  Button
On/Off Switch

Push in the top of the On/Off switch to turn on the system.  The switch is part of the power supply; if it is suspected of being faulty, replace the entire power supply.


Fan Locations

The AlphaStation 500 Series system has three fan locations.

1.	System fan
2.	Cache cooling fan
3.	Power supply fan (in the power supply)


Power Troubleshooting Checklist
Troubleshooting
Power Troubleshooting Checklist

Symptom	Check

Power indicator light not lit.	On/Off switch set to off.
	Power at wall receptacle.
	AC cord.
Power indicator lights for a few seconds, then goes out.	Three fans operating. Click here to see location of fans Caution: The power supply turns off if it senses that a fan has failed.
Power indicator lit, but no screen display.	Monitor turned on and power indicator lit. Raster present if brightness turned up.
	Fuses and circuit breakers.
	Video controller cable properly connected.
	Serial ROM (SROM) error-code indicators.
	Power present at system board.    Power supply pinouts


Power Supply Pinouts
Troubleshooting
Power Supply Pinouts

Power
Supply	Pin	Wire
Connector	Number	Color		Voltage
P8 and P9 (Disk Drive)	1 2 3 4	Red Black Black Blue	+5V GND GND +12V
P4-P7 and P11 (Disk Drive)	1 2 3 4	Blue Black Black Red	+12V GND GND +5V
P1 (System Board)	1 2 3 4 5 6	White Red Blue Yellow Black Black	POK_H +5V +12V -12V (key) GND GND
P2 (System Board)	1 2 3 4 5 6	Black Black Gray Red Red Red	GND (key) GND -5V +5V +5V +5V
P3 (System Board)	1 2 3 4 5 6	Red Red Red Black Black Black	+5V +5V +5V(key) GND GND GND
P10 (System Board)	1-8 9-16	Black Orange	GND +3.3V
Fan Connector Variable (8.5-15.2V)	1 2	Red Black	+Fan Fan Rtn


Cooling Problems
Troubleshooting
Thermal Problems

The AlphaStation 500 Series system operates at an ambient temperature ranging from 10 [image] to 40 [image] C (50 [image] to 104 [image] F).  The system unit is cooled by three speed-controlled fans, the system fan in front of the CPU, the cache fan which cool cache on the system board, and the power supply fan.

  Click here to see the actual location of the fans.

The power supply varies the fan voltage based on feedback from a temperature sensor located in the enclosure assembly.  The voltage may range from 7.0V to 13.0V.  The power supply detects fan failures by monitoring fan ripple current.  If a fan fails, the failure detector turns off the system after a one second delay.

If your system shuts down immediately after startup, or if overheating is suspected, observe the power supply fan through its opening on the rear of the enclosure as you cycle the power.  If it is spinning, remove the enclosure cover, cycle the power again, and check to see if the system and cache fan cooling fans are spinning before the system shuts down.

Intermittent problems could result from overheating.  Check that the airflow path is clear.  Make sure that no materials are blocking the front bezel.  Also, make sure that the cables inside the system are arranged and mounted properly, verifying that the airflow is not blocked.


Initialization and POST Errors
Troubleshooting
Initialization and Power-On Self-Test Errors

When the system is turned on, the code in serial read-only memory (SROM) initializes the CPU, core logic, and memory.  After a successful initialization, the SROM code loads the power-on self-test (POST) code.  The POST code primarily performs data-path verification along with some functional testing.  Typically, POSTs report errors that would prevent the main console from displaying.  When the initialization or POST code encounters a fatal error, the process stops.  For nonfatal errors, the error is displayed and/or logged, and the process continues.


SROM Mini-Console
Serial ROM (SROM) Mini-Consoles

The SROM mini-consoles are provided for use by manufacturing.  Select the SROM
mini-console from the eight SROM jumper positions.


Console Code or Checksum Failure

SROM is loaded on power-up..Following successful completion of this code, the SRM/ARC console is decompressed and loaded into memory.  Control is passed to the loaded console if the checksum is correct; if it is not, a failsafe loader will attempt to load a console from the floppy drive.


SROM Unable to Load Flash Code
FlashROM Code Fails to Load

If the SROM is unable to load the flashROM code (ARC or SRM console firmware), the SROM executes its fail safe loader (floppy diskette).

Note:  Since only the checksum or header may be corrupt if a checksum error is detected, the SROM does not execute the floppy diskette loader; in that case the SROM continues loading the ARC or SRM console firmware.

If flashROM error codes F0 through FF are detected, the SROM code uses its built-in fail-safe mechanism that attempts to load from a diskette using the boot block and update utility.

Each SROM program contains either a floppy diskette loader or a mini-console which is selected with the SROM jumpers on the system board.

 SROM error codes
 SROM jumpers


Console Troubleshooting
Troubleshooting
Console

The AlphaStation 500 Series system contains two console firmware systems:

	The advanced RISC computing (ARC) console supports the Windows NT operating system.
	The system reference manual (SRM) console supports the Digital UNIX and OpenVMS operating systems.
Note:  The SRM console in the flashROM does not contain all diagnostics.  (Manufacturing has a superset of the SRM console that contains loadable diagnostics to support their environment.)

A power failure during a flashROM upgrade by the update utility could corrupt the contents of the flashROM.  After turning on the system, the SROM code, sensing the flashROM corruption, attempts to load from the diskette drive.  If the SROM code fails to load from the diskette, select the SROM mini-console.


Boot Troubleshooting
Troubleshooting
Boot

Symptom	Check for

No response to keyboard commands.	Keyboard connected to proper port.
	Stuck key.
Will not boot from a diskette drive.	Configuration not supported at this time.
Will not boot from a small computer system interface (SCSI) disk  drive.	Will a bootable disk boot the operating-system (Windows NT, Digital UNIX, or OpenVMS)?  If so, possibly the SCSI disk is empty, corrupted, or not formatted.
	SCSI termination: The SCSI bus must be terminated at the last internal and the last external SCSI peripherals.  The internal SCSI cable contains termination.
	SCSI ID jumpers: Check for conflicting IDs and properly set jumpers and switches.
	SCSI cabling:  Check for level and properly oriented cables.  Also, check for bent pins.


Troubleshooting Errors and Machine Checks
Troubleshooting
Machine Checks

When an error exception occurs, the CPU:

1.	Drains the pipeline.
2.	Loads the program counter (PC) into the EXC_ADDR register.
3.	Dispatches the code (plus an offset) to the PALcode exception routine.  (The offset for machine checks is 0x400.)  The PALcode then begins gathering information and building a machine-check stackframe.

  Analyzing a machine check


Error Checking Map
Click on specific blocks for descriptions.


Serial ROM (SROM)

The SROM and the SROM interface to DECchip 21164-AA do not have error-checking capability.


Bcache Error Detection
B-Cache Error Detection

The B-cache does not detect errors, but it does furnish information through parity bits to error-detection networks in the CPU.  Parity bits include:

	Tag address even parity (written by the CPU)
	Tag control even parity (written by memory control or by the CPU)
Keep your cache cool.  Arrange and mount the cables properly to let the air flow without blockage.


ROM Error Detection

The read-only memory (ROM) section of the system uses checksums to protect the data.  First the serial ROM (SROM) verifies the data through checksums.


EV5 CPU Errors

Memory Data Path Errors

Memory Errors

Memory Control Errors


CIA Errors

Memory Data Path Errors

Memory Errors

Memory Control Errors

CIA AISIC Host PCI Bridge Detected Errors


Memory Data Path Error Detection
CIA and CPU Memory Data Path Error Detection

The CPU performs its own data checking for CPU-initiated transactions.

The CIA performs error detection for transactions initiated by direct memory accesses (DMAs).  When either the B-cache or memory is read because of a DMA transaction (DMA read or DMA write masked), the data is checked for ECC errors.  If an error exists, the CIA notifies the CPU.

If an error occurs on data during a DMA write, the CIA writes the potentially invalid data to memory.


Memory Error Detection
CIA and CPU Memory Error Detection

Cache on the system board and a variable number of DIMMs on the system board comprise the AlphaStation 500 Series system memory.

DIMMs do not detect errors, but they do furnish information though ECC to error-detection and correction networks in the CPU and the CIA.  During CPU-initiated transactions, the CPU generates ECC checkbits on the data which are stored by the DIMMs.  (In the case of writing a B-cache victim to memory, B-cache contains the checkbits.)  During direct memory access (DMA) write transactions, the CIA generates the checkbits.


CIA Memory Control Errors
CIA and CPU Memory Control Errors

The CIA memory control logic provides control for: filling the B-cache, extracting victims on CPU-initiated transactions, probing the B-cache on direct memory accesses (DMAs), and invalidating the B-cache when a DMA write hit occurs. The EV5 CPU detects both the B-cache tag address and the B-cache tag control parity errors, while the CIA detects nonexistent memory errors as follows:

	B-cache tag address parity error (bc_TAPErr)
	B-cache tag control parity error (bc_TCPErr)
	Nonexistent memory error (nxMErr)

When an access to nonexistant memory is detected, the CIA signals the CPU with a hard error.  Error information is captured by:

	Loading the current sysAdr<33:4> into the MEM_ERR0 register
	Setting the appropriate bits in the CIA_ERR register

If another error occurs when these registers are locked, the LostErr bit in the CIA_ERR register will be set and the error information of the lost error will not be captured.


PCI Bridge-Detected Errors
CIA AISIC Host PCI Bridge-Detected Errors

When the CIA AISIC host peripheral component interconnect (PCI) bridge detects errors, the PCI Error Address register (PCI_ERR) logs addresses sent or received on the PCI.  Click on any of the errors listed below for information about the error and the actions taken as a result of the error.

CPU-Initiated Transaction Errors:

No device error (master abort)	Target abort error
Address error	Read data error
Write data error	I/O timeout

DMA Transaction Errors:

Address parity error	Read data error
Write data error	Memory error
Uncorrectable read data error	Scatter/gather invalid error
Correctable and uncorrectable write data errors	Scatter/gather uncorrectable read data errors

Note:  Interrupts to the CPU flag DMA transaction errors.


No Device Error
No Device Error (CPU-Initiated)

If, on an I/O transaction, DEVSEL# is not signaled within five cycles, the PCI bridge assumes there will be no response to the transaction from a PCI device.

	The RCND_MAS_ABT bit in the CIA_ERR register.
	The PCI Error register (PCI_ERR2) contains the address sent at the beginning of the transaction and is locked.
	On write transactions, the CIA error bit is signaled to interrupt the CPU.
	On read transactions, CIA asserts FILL_ERROR to the CPU.


Target Abort Error
Target Abort Error (CPU-Initiated)

If the target device ends a PCI transaction (using target-abort protocol) during an I/O transaction:

	The tAbt bit in the DCSR and the pciCmd field are set appropriately.
	The PCI Error register (PCI_ERR) is locked.
	On write transactions, the CIA error is signaled to interrupt the CPU.
	On read transactions, CIA asserts FILL_ERROR to the CPU to end the transaction.


Address Parity Error
Address Parity Error (CPU-Initiated)

Because no method exists for the PCI bridge to monitor the PCI bus soft-error (SERR) signal, the PCI bridge cannot determine whether an address parity error occurs during I/O transactions.


Read Data Parity Error
Read PCI Data Parity Error (CPU-Initiated)

The POST code disables PCI data parity checking.


Write Data Parity Error
Write PCI Data Parity Error (CPU-Initiated)

On I/O write transactions, a write data parity error occurs if the slave device signals PERR# for any longword of data.

	The transaction continues normally.
	The PCI Error Address register (PCI_ERR) is locked. (If an error occurs on more than one longword of a single-write burst, the LostErr bit in the CIA_ERR register is set.)
	The CIA error is signaled to interrupt the CPU.


I/O Timeout

If an I/O transaction is not completed within one second after initiation, the transaction is timed out to the IOA timeout bit in CIA _ERR.


Address Parity Error (DMA)
PCI Address Parity Error (DMA Transaction)

POST code disables address parity checking at the CIA.


Read Data Parity Error (DMA)
Read PCI Data Parity Error (DMA Transaction)

The PCI master device occasionally detects parity errors on the data phase of DMA read transactions.  Even if the device signals PERR#, the PCI bridge takes no action because it is the responsibility of the master device to handle the error.


Write Data Parity Error (DMA)
Write PCI Data Parity Error (DMA Transaction)

A data parity error occurs on the data phase of DMA write transactions when the generated parity of the incoming data and byte enables sampled from the PCI address and C/BE lines differ from the value sampled from PAR.

POST code disables data parity checking at CIA.


Memory Error (DMA)
Non-Existent Memory Error (DMA Transaction)

If the memory control logic detects an error (nonexistent memory [nem])during a DMA transaction, it logs the address and the specific error bit and terminates the PCI by signaling a target abort.

	The MEM_NEM bit is set in CIA_ERR.
	The PCI ERR1 register is locked with the PCI address of the memory transaction.
	The CIA error is signaled.
	On read transactions, the CIA terminates the PCI transaction using the target-abort protocol.
	On write transactions, the CIA dismisses the write buffer entry (a single cache line).


Read Uncorrectable Data Error (DMA)
Uncorrectable Read Data Error (DMA Transaction)

If an ECC error occurs in memory (or cache), the CIA informs the CPU using CIA error.PCI bridge chip over the epiData bus.

	The CIA error is signaled.
	The un_cor_err bit in the CIA_ERR register is set.
	The PCI Error registers are locked.
	If there is an ECC error in the cache block, the invalid data is requested by the PCI, the transaction is ended using the target-abort protocol.


Scatter/Gather Invalid Error
Scatter/Gather Invalid Error (DMA Transaction)

If a mapped DMA transaction contains an invalid scatter/gather entry, data will not be written to or read from memory.

	The iPTL bit in the DCSR is set.
	The PCI Error Address register (PEAR) is locked.
	The CIA_ERR bit is signaled.
	Read transactions terminate on the PCI using the target-abort protocol.


Write Correctable and Uncorrectable Data Error (DMA)
Correctable and Uncorrectable Write Data Errors (DMA Transaction)

If a DMA write transaction is not a full hexword, the memory control logic performs a read-modify-to-write transaction.  If an error is detected during the read (from memory) transaction before the write transaction completes, the PCI bridge performs no action.


Scatter/Gather Read Uncorrectable Error (DMA)
Scatter/Gather Uncorrectable Read Data Errors (DMA Transaction)

An uncorrectable data error that occurs when accessing a scatter/gather map entry in memory causes actions similar to those caused when an uncorrectable data error occurs in a DMA read transaction:

	The uMRD bit in the DCSR is set.
	The address is logged in the sysBus Error Address register (SEAR).
	The CIA error is signaled.


PCI Bus Error Detection

Not all PCI devices are required to detect and report parity errors, but all are required to generate parity on all of their transactions.  During the address phase, the PAR bit provides even parity for AD [31:0] and C/BE[3:0], regardless of whether or not all the lines carry meaningful information.

Master devices drive PAR for the address and data phases on write transactions. Target devices drive PAR during the data phase of read transactions.

The peripheral component interconnect (PCI) contains PERR and SERR to signal errors:

	PERR reports data parity errors for all transactions except special-cycle commands; targets use PERR to signal data parity errors to the master device.  Only one device at a time can drive PERR.
	SERR reports address parity errors and data parity errors on special cycles; it is sent to the CPU as a nonmaskable interrupt (NMI).  SERR is a wire-OR'd signal that can be driven by several devices at any one time.


ISA Bus Error Detection
EISA Bus Error Detection

The hidden EISA bus uses an I/O channel check (IOCHK) signal to indicate that an industry-standard architecture (ISA) device detected a parity error on the EISA bus.  Using IOCHK causes a nonmaskable interrupt (NMI) to be sent to the CPU.


Analyzing Machine Checks
Digital AlphaStation 500 Series System
Analyzing Machine Checks

The following example demonstrates one approach to analyzing a machine check.

*** unexpected interrupt through vector 00000066

IPRs:

EXC_ADDR:   000000000004BF74  EXC_SUM:  0000000000000000 EXC_MASK:  0000000004

ISR:  0000000080400000  ICSR:  000000414C000000 IC_PERR_STAT: 0000000000000000

DC_PERR_STAT:0000000000000000  VA:0000008580007A80  MM_STAT:0000000000016051

SC_ADDR:FFFFFF0000012EEF  SC_STST:0000000000000000 BC_TAG_ADDR:FFFFFF80004D0FFF

EI_ADDR:FFFFFF7FEFF587FF  FILL_SYN:0000000000002BC1 EI_STAT:FFFFFFF002FFFFFF

LO_LOCK:FFFFFF00001191FF

ALCOR Error CSRs (CPU 0)

CIA_ERR:  FFFFFFFF81000100 ERR_STAT: 00000000000006F2 ERR_MASK: 00000003

ECC_SYN:  0000000000000000 MEM_ST0:  00000000017100C0 MEM_ST1: 00000000101

PCI_ERR0: 0000000007060007 PCI_ERR1: 00000000000B8800 PCI_ERR2: 000000000...

EIR0:     0000000001710100 EIR1:     0000000000001685

I/O CSRs:

MEMORY BASE ADDRESS CSRs

MBA:  10008011

MBA:  10040011

MBA:  00000000

MBA:  00000000

MBA:  00000000

MBA:  00000000

MBA:  00000000

MBA:  00000000

MCR:  2001FE31

TMG0: 6030C140

TMG1: 6030C142

TMG2: A44B0660

*** Console Stopped because of Machine Check  ***

*** Press HALT Button to return to console !! ***

Interpetation

The following is a brief description of what various bits mean in the registers dumped after thi sample machine check above.  Refer to the full register definitions for more detail.  Note that certain information is valid only if an error bit is set.  In this example a PCI target abort error is indicated (see CIA_ERR: bit 31).

EXC_ADDR:         PC of next instruction to execute when the exception was taken
EXC_SUM:           Summary of arithmetic traps (none shown)
EXC_MASK:         Exception mask 63:32(F31:F0), 31:0(I31:I0)
ISR:                      Interrupt summary register mck & I22 are set
ICSR:                   IBOX control bits
IC_PERR_STAT:  No ICACHE parity errors shown
DC_PERR_STAT:

VA:
MM_STAT:           bit 0 indicates an error during a write operation
                            bit 5 indicates a bad virtual address
                            bits 10:6 are the RA field of the faulting instruction
                            bits 16:11 are the instruction opcode bits (STL instruction)
SC_ADDR:
SC_STST:
BC_TAG_ADDR:

EI_ADDR:           meaning full if EI_STAT error bit set
FILL_SYN:          meaning full if EI_STAT error bit set
EI_STAT:            shows a chip id of 2, no errors
LO_LOCK:

CIA_ERR            bit 8 PCI master state machine receive a target abort
                           bit 24 another aster state machine receive a target abort!
               Note:   bit 31 error detected and CIA error registers are locked!
ERR_STAT:        bit 1    PCI master state machine active
                           bit 7:4  IO command/address bits are valid
                           bit 10:8 CPU command/address bits are valid
ERR_MASK:
MEM_ST0:         bit 31:4 memory port add (valid when CIA_ERR is locked)
MEM_ST1:         bit 1:0  mem port address <33:32>
                          bit 11:8 mem port command (in this case a DMA Write was in progress)
PCI_ERR0:        bit 11:8 window 0 hit
                          bit 19:16 (6) Last Write Data Cycle
                          bit 27:24 current PCI command (7 Memory Write)
PCI_ERR1:        bit 31:0 DMA address for command in executing/logged in PCI_ERR0
PCI_ERR2:        bit 31:0 PCI address
EIR0:                 interrupt req reg (int pending from Slot 0(A) & Slot 3(A)
EIR1:                 interrupt mask (1 enabled)


Failing DIMM Isolation
Digital AlphaStation 500 Series System
Failing DIMM Isolation

The following example demonstrates the use of a machine check analysis to isolate a failing DIMM.

Processor correctable error through vector 00000063.

EI_STAT: FFFFFFF0C2FFFFFF  EI_ADDR: FFFFFF0012745D8F

FILL_SYN:  0000000000000010  ISR: 0000000100000000 MCES 4

check data bit 4 J28 0

page # 9305 base 9d

Interpretation

The following shows the meaning of the displayed register bits for the example above.  In this case an ECC error is indicated and the console has identified the DIMM (and data bit) with the error.  If this information is incorrect you will need to use the address and syndrome to issolate the problem.

EI_STAT:         bit 30 indicates error on fill data from main memory
                        bit 31 indicates Correctable ecc error detected
EI_ADDR:        bit 39:4 address of error

FILL_SYN:       bit 7:0  syndrome of error in lower quadword (see syndrome table)
                        bit 15:8 syndrome of error in upper quadword
ISR:                 bit 31   indicates a CRD interrupt (correctable ECC error)
MCES             <0>       Machine check in progress
                       <1>       System Correctable Error
                       <2>       Processor Correctable Error
                       <3>       Disable reporting of Processor Correctable Errors
                       <4>       Disable reporting of System Correctable Errors


Nonmaskable Interrupts (NMIs)

Nonmaskable interrupts (NMIs) originate on the PCI/EISA bridge chip (ESC).  NMIs are used for:

SERR#:	The PCI/EISA bridge chip detects an address parity error on the PCI bus and takes no action except to  report the error to the CPU.
IOCHK#:	The PCI/EISA bridge chip detects a parity error on an expansion module plugged into the ISA bus.


Troubleshooting Tools
Digital AlphaStation 500 Series System
Troubleshooting Tools

Many tools are available to assist you with troubleshooting.  Some tools help test and exercise the system, and others gather and format information.

The DEC Verifier and Exerciser Tool (DEC VET) falls into the first category.  DEC VET is an online tool for verifying system installations and acceptance.  It is also used to maintain and troubleshoot systems and to perform load and stress tests on single devices, systems, and networks.  Versions of DEC VET are available for each operating system.  For more information, see the following guides:

	DEC Verifier and Exerciser Tool User's Guide for Windows NT
	DEC Verifier and Exerciser Tool User's Guide for Digital UNIX
	DEC Verifier and Exerciser Tool User's Guide for OpenVMS

Each operating system has a specific mechanism for capturing and logging error information.  To access an operating system error log, click on one of the following buttons:

  Windows NT

  Digital UNIX

  OpenVMS


Accessing the Windows NT Error Log

Windows NT maintains an event log file. The event logging service starts automatically when Windows NT is started. The Event Viewer is used to view and manage the event logs.

Start the Event Viewer by clicking on its icon. The icon is located in the Administrative Tools group in Program Manager. Windows NT uses three logs:

	System log	Tracks events logged by Windows NT system components (for example, the failure of a driver to properly load)
	Application log	Tracks events logged by applications
	Security log	Tracks changes to the security system and identifies possible security breaches

Use the Log menu of the Event Viewer to select the log you need to view.  For more information, either refer to the Event Viewer chapter in Microsoft Windows NT System Guide or use online help.


Accessing the Digital UNIX Error Log

The event report formatter for Digital UNIX is UERF. The syntax of the command is:

    /usr/sbin/uerf [ options ... ]

The uerf command uses the uerf.bin, uerf.hlp, and uerf.err data files.  The uerf.bin file is the event information database. The uerf.hlp file is the help file. The uerf.err file is the event message file.  The uerf command expects to find the data files in the /usr/sbin directory.

By default, the uerf command outputs the contents of the event log file specified by the *.* entry in the /etc/binlog.conf configuration file.  To report on any other event log file (or if there is no *.* entry), you must use the uerf command with the -f option.

Note:	For further information, see the "UERF Man" pages. (Type man uerf at the Digital UNIX prompt.)

EXAMPLES

The following example produces a report containing all event events, excluding logged operating-system events and operator and maintenance-class events:

uerf -O -x -c oper,maint

The following example produces an event report from the /usr/adm/binary.errlog.old file:

uerf -f /usr/adm/binary.errlog.old

The following examples produce event reports for the specified record codes:

uerf -r 100,102

uerf -r 100-109

The following example produces a report of all the events that occurred between 10:47 a.m. on April 13, 1995 and 5:30 p.m. on April 20, 1995:

uerf -t s:13-apr-1995,10:47:00 e:20-apr-1995,17:30:00

The following example produces an event report of the events that occurred on the current day and year, starting at 1:20 p.m. and ending at the current time:

uerf -t s:13:20

The following example produces a report of all logged events and displays it in reverse chronological order, starting with the current date and time:

uerf -R


Accessing the OpenVMS AXP Error Log
Accessing the OpenVMS Error Log

Access the OpenVMS Errorlog Report Formatter (ERF) with the ANALYZE/ERROR_LOG command. The syntax is:

  ANALYZE/ERROR_LOG [filespec[,...]]

For more information, see the VMS Error Log Utility Reference Manual.

EXAMPLES

The following example uses all the defaults:

$ ANALYZE/ERROR_LOG

The following example limits the entry range generated from the ERRLOG.SYS file to entries from 1 to 18:

$ ANALYZE/ERROR_LOG/ENTRY=(START:1,END:18) ERRLOG.SYS

The following example shows how to exclude a given class of event information (disk information, in this case):

$ ANALYZE/ERROR_LOG/EXCLUDE=(DISK)

The following example furnishes a report containing only disk-related information:

$ ANALYZE/ERROR_LOG/INCLUDE=(DISK)


Field-Replaceable Units (FRUs)
Digital AlphaStation 500 Series System
Field-Replaceable Units (FRUs)

CAUTION:  When servicing the AlphaStation 500 Series system, always remove the AC power cord and follow Digital service procedures.

  Internal Cut-Away View of System     [image]   Diagram of System Board Components

Click on any of the items listed below to access procedures related to removing and replacing FRUs.

  Opening the Enclosure

  Floppy drive

  CD-ROM

  Mass Storage Devices

  PCI Cards

  PCI Riser Card

  System Fan

  Cache Fan

  Speaker

  Audio Card

  MAU Ethernet Card

  Power supply

  DIMMs

  System Board


Opening the Enclosure
Field-Replaceable Units (FRUs)
Opening the Enclosure

To open the AlphaStation 500 Series system enclosure:

1.  Turn off the system and all external peripheral devices.

2.  Unplug the power cord from the wall outlet.

3.  Wait at least 15 seconds, to allow time for the power supply capacitors to fully discharge.

4.  Unlock the rear panel by turning the key (1) counterclockwise.

5.  Facing the rear of the system, remove the top cover thumbscrew (2) and remove the top cover by sliding it rearward and lifting up (3)..

6.  If necessary to access the item you are servicing,

slide the side panel which is next to the PCI cards to the rear and remove it.

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.


Side Panel

From inside the enclosure, push the side panel tab outward through its slot, and slide the side panel rearward and out to remove it.


Removing and Replacing a Device in the Floppy Drive
Field-Replaceable Units (FRUs)
Removing and Replacing the Floppy Drive

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

To remove the floppy drive:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover
3.	Snap out the bracket containing the floppy drive and the optional mass storage drive (if any) by pushing in on the plastic tabs (1) on either side of the rear of the bracket.
4.	Lift the bracket containing the drives up from the enclosure (2).
5.	Remove the IDE and power cables from the floppy drive.  Note the position of the cables so you can reconnect them to the correct devices later.
6.	Remove the two floppy mounting screws on the side of the bracket (3).
7.	Slide the floppy drive (6) out of the bracket by pushing out on the plastic retaining tabs in the middle of the bracket (4).  It is not necessary to remove the EMI shield (5) to replace the floppy drive.
To replace the floppy drive:

1.	Check the configuration jumpers of the replacement drive and configure it.  For information about addresses, terminations, and so forth, refer to the drive manual.
2.	Slide the floppy drive into the mounting bracket and secure it with the screws.
3.	Slide the bracket forward into the system unit until the plastic tabs on either side of the bracket snap into place.
4.	Connect the IDE and power cables. Caution:  The floppy drive IDE cable has two distinct ends which are labeled: a controller end, and a drive end.  If you have disconnected the cable at both ends, you must refer to the labels to prevent damage which could result if the cable is not oriented correctly.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the CD-ROM
Field-Replaceable Units (FRUs)
Removing and Replacing the CD-ROM

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

To remove the CD-ROM:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Remove the SCSI adapter from the CD-ROM.  It is not necessary to remove the adapter from the end of the SCSI cable, since you will be using it with the replacement CD-ROM.
4.	Remove power cable from the CD-ROM.
3.	Remove the audio cable from the CD-ROM (the other end is connected to the audio card at the rear of the enclosure.
4.	Remove the pin which is inserted down through the four holding tabs on the right-hand side panel of the system enclosure (1).
5.	Snap out the bracket containing the CD-ROM by pushing in on the button latch built into the right-hand side panel of the system enclosure (2).
6.	Slide the CD-ROM and bracket toward the rear of the system unit and remove them (3).
7.	Seperate the CD-ROM from its bracket by removing the four screws (4), and sliding it forward (5).
To replace the CD-ROM:

1.	Check the configuration jumpers of the replacement drive and configure it.  For information about addresses, terminations, and so forth, refer to the drive manual.
2.	Attach the CD-ROM mounting bracket using the four screws.
3.	Slide the CD-ROM and bracket forward into the top slot in the right-hand storage bay, until the latch built into the right-hand side panel of the system enclosure engages to hold them in place.
4.	Replace the pin which is inserted down through the four holding tabs on the right-hand side panel of the system enclosure (1).
5.	Reconnect the SCSI adapter, SCSI cable and power and audio cables to the  CD-ROM.
6.	Replace the enclosure cover.
7.	Connect the AC power cord and turn on the system.


Removing and Replacing a Storage-Bay Device
Field-Replaceable Units (FRUs)
Removing and Replacing a Mass Storage-Bay Device

The AlphaStation 500 Series system enclosure contains two internal mass-storage bay areas--left and right, as viewed from the front of the system.

The left-hand internal storage bay area (under the floppy drive) can hold one 3.5-inch x 1.0-inch hard disk.

The right-hand internal storage bay area (under the CD-ROM) contains a drive tray which accomodates up to two hard drives: either one 3.5-inch x 1.0-inch hard disk, or one 3.5-inch x 1.6-inch hard disk, or  two 3.5-inch x 1.0-inch hard disks.  Due to thermal considerations, you cannot install a 3.5-inch x 1.6-inch hard disk and a 3.5-inch x 1.0-inch hard disk simultaneously in this bay.

  Click here to see the relative locations of the mass storage bay areas.

  Procedure for replacing the storage device in the left-hand storage bay

  Procedure for replacing a storage device in the right-hand storage bay


Removing and Repalcing a Mass Storage Device in the Left-hand Storage Bay
Field-Replaceable Units (FRUs)
Removing and Repalcing a Mass Storage Device in the Left-hand Storage Bay Area

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

The left-hand storage bay area (under the floppy drive) can hold one 3.5-inch x 1.0-inch hard disk.

To remove the mass storage device from the left-hand mass storage bay:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover
3.	Snap out the bracket containing the drives by pushing in on the plastic tabs on either side of the rear of the bracket.
4.	Remove the IDE and power cables from the floppy drive and the mass storage drive.  Note the position of the cables so you can reconnect them to the correct devices later.
5.	Remove the four mounting screws on the side of the bracket and slide the floppy drive out of the bracket.
6.	Remove the metal EMI shield under the floppy drive.
7.	Remove the four mounting screws which attach the bracket to the top of the mass storage drive and slide the drive out of the bracket.
Note: Under the floppy drive, the bracket will accomodate a 1.0-inch high device only.

To replace the mass storage device:

1.	Check the configuration jumpers of the replacement drive and configure it.  For information about addresses, terminations, and so forth, refer to the drive manual.
2.	Slide the mass storage  drive into the mounting bracket and secure it with the four screws through the mounting bracket from the top.
3.	Replace the EMI shield.
4.	Slide the floppy drive into the mounting bracket and secure it with the four screws from the side of the bracket.
5.	Slide the bracket forward into the system unit until the plastic tabs on either side of the bracket snap into place.
6.	Connect the IDE and power cables to both the mass storage and floppy drives.   Caution:  The floppy drive IDE cable has two distinct ends which are labeled: a controller end, and a drive end.  If you have disconnected the cable at both ends, you must refer to the labels to prevent damage which could result if the cable is not oriented correctly.
7.	Replace and secure the enclosure cover.
8.	Reconnect the AC power cord and turn on the system.


Removing and Replacing a Mass Storage Device in the Right-hand Storage Bay
Field-Replaceable Units (FRUs)
Removing and Replacing a Mass Storage Device in the Right-hand Storage Bay Area

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

The right-hand storage bay area (under the CD-ROM) contains a drive tray which accomodates up to two hard drives: either one 3.5-inch x 1.0-inch hard disk, or one 3.5-inch x 1.6-inch hard disk, or  two 3.5-inch x 1.0-inch hard disks.  Due to thermal considerations, you cannot install a 3.5-inch x 1.6-inch hard disk and a 3.5-inch x 1.0-inch hard disk simultaneously in this bay.

To add or replace one of the two 3.5-inch mass storage devices in the right-hand storage bay:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
4.	Snap out the bracket containing the CD-ROM by pushing in on the button latch built into the right-hand side panel of the system enclosure (see Replacing the CD-ROM).
5.	Slide the CD-ROM and bracket toward the rear of the system unit and remove them.  It is not necessary to disconnect the cables from the CD-ROM.
6.	Snap out the bracket containing the 3.5-inch mass storage drives by pushing in on the button (1) built into the right-hand side panel of the system.
7.	Slide the drive assembly and bracket (2) toward the rear of the system unit and remove it.
8.	Disconnect the SCSI and power cables from the devices you are replacing.
9.	Remove the four screws (3) and slide the device from the bracket (4).
5.	Slide the drive assembly and bracket toward the rear of the system unit and remove it.
To replace one of the two 3.5-inch mass storage devices in the right-hand storage bay:

Note: The bracket will accomodate a 1.6-inch high device only in the upper slot, and a 1.0-inch high device only on the bottom.

1.	Check the configuration jumpers of the replacement drive and configure it.  For information about addresses, terminations, and so forth, refer to the drive manual.
2.	Slide the new device into the bracket and replace and tighten the four screws.
3.	Slide the device(s) and bracket forward into the five tabs on the bottom of the enclosure in the right-hand storage bay until the latch built into the right-hand side panel of the system enclosure engages to hold them in place.
4.	Reconnect the SCSI and power cables to the device.
	Replace the CD-ROM and bracket.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing an Expansion Module
Field-Replaceable Units (FRUs)
Removing and Replacing a PCI Module

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

Note:  Adding or moving PCI modules may require reconfiguration of your operating system.

The AlphaStation 500 Series system features one 64-bit PCI slot and three 32-bit PCI slots.

The upper slot is the 64-bit slot.

To remove a PCI module:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Remove the side panel
4.	Disconnect any cables connected to the module you are removing.
5.	Remove the screw (2) at the front of the module.
6.	Gently pull the expansion module outward to release it from its slot (1) on  the PCI riser card.

To replace a PCI module:

1.	Insert and secure the replacement module into its slot on the PCI riser card by pressing it firmly into the socket.
2.	Replace and tighten the screw on the front of the module.
3.	Connect previously removed cables to the replacement module.
4.	Replace and secure the left side panel.
4.	Replace and secure the enclosure cover.
5.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the PCI Riser Card
Field-Replaceable Units (FRUs)
Removing and Replacing the PCI Riser Card

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

Note:  Adding or moving PCI modules may require reconfiguration of your operating system.

To remove the CPI riser card:

1.	Turn off the system and disconnect the AC power cord.
2	Remove the encosure cover enclosure cover.
3.	Remove the side panel to expose the PCI cards.
4.	Remove all PCI cards
5.	Remove the screws (1) holding the PCI riser card to the cross member at the top and lift it (2) out of its connector on the system board.

To replace the PCI riser card:

1.	Insert the replacement board into the slot on the system board, using the standoffs on the cross member to ensure proper alignment.  Use appropriate force to seat the card.
2.	Replace the screws at the top of the riser card.
3.	Replace the PCI cards.
4.	Replace and secure the side panel.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the System Fan
Field-Replaceable Units (FRUs)
Removing and Replacing the System Fan

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

See fan locations for the exact location of the system fan.

To remove the system cooling fan:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Disconnect the fan wire at J1 on the system board, noting the wire routing.
4	Remove the cooling-fan and bracket by lifting it upward (1).
5.	Push outward on the three bracket tabs (2) and Remove the fan from its bracket by sliding it forward (3).
Note:	You will reuse the bracket in the replacement procedure.

To replace the system fan:

1	Snap the replacement fan into the mounting bracket.
2.	Reroute the fan wire along the removal path.
3.	Insert the bracket and fan into the slot and snap it into place.
4.	Connect the fan wire at J1 on the system board.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the Cache Cooling Fan
Field-Replaceable Units (FRUs)
Removing and Replacing the Cache Cooling Fan

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

See fan locations for the exact location of the cache fan.

To remove the cache fan:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Remove the left-hand storage bay and any devices in it.
4.	Disconnect the fan wire at J3 on the system board, noting the wire routing.
5	Remove the cache cooling-fan by pushing outward on the two tabs (1), and snapping it upward (2) off the mounting bracket.
To replace the cache fan:

1.	Reroute the fan wire along the removal path.
2.	Place the fan in its mounting brackect.
3.	Connect the fan wire at J3 on the system board.
4.	Replace the left-hand storage bay and its devices.
6.	Replace and secure the enclosure cover.
7.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the Speaker
Field-Replaceable Units (FRUs)
Removing and Replacing the Speaker

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

The internal speaker is located behind the front of the system unit, next to the LEDs.

To remove the internal speaker:

1.	Remove the enclosure cover.
2.	Remove the right-hand mass storage bay.
3.	Disconnect the speaker cable (red and black, twisted-pair wire) from J5 on the audio card.
4.	Slide the speaker sideways to the left (as viewed from the front of the enclosure) to remove it from the speaker mounting bracket.
To replace the internal speaker:

1.	Snap the replacement speaker into the bracket.
2.	Reconnect the speaker wires.
3.	Replace the left-hand mass storage bay.
4	Replace and secure the eclosure cover.
5.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the Audio Card
Field-Replaceable Units (FRUs)
Removing and Replacing the Audio Card

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

To remove the audio card:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Disconnect any external devices connected to the audio card through the rear of the enclosure.
4.	Disconnect the speaker cable from the J5 connector on the audio card.
5.	Disconnect the the CD-ROM cable from the J6 connector on the audio card.
6.	From the rear of the enclosure, remove the audio card screw.
7.	Slide the audio card upward and out of the enclosure.
To replace the audio card:

1.	Slide the audio card downward into the tabs in the enclosure.
2.	Replace the audio card screw from the rear of the enclosure.
3.	Reconnect the speaker and CD-ROM cables.
4.	Reconnect any external devices to the audio card through the rear of the enclosure.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the MAU Ethernet Card
Field-Replaceable Units (FRUs)
Removing and Replacing the MAU Ethernet Card

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

To remove the MAU Ethernet card:

1.	Turn off the system and disconnect the AC power cord.
2.	Remove the enclosure cover.
3.	Disconnect the external Ethernet cable attached to the card  through the rear of the enclosure.
4	Disconnect the internal MAU Ethernet cable from J2 on the card.
5	From the rear of the enclosure, remove the MAU Ethernet card screw.
6.	Slide the card upward and out of the enclosure.

To replace the MAU Ethernet card:

1.	Slide the MAU Ethernet card downward into the tabs in the enclosure.
2.	Replace the MAU Ethernet card screw from the rear of the enclosure.
3.	Reconnect the internal MAU Ethernet cable to the card at J2.
4.	Reconnect the external MAU Ethernet cable.
5.	Replace and secure the enclosure cover.
6.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the Power Supply
Field-Replaceable Units (FRUs)
Removing and Replacing the Power Supply

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

The power supply for the AlphaStation 500 Series system is rated at 320 W output.  It features four output voltages and automatic input-voltage selection.

To remove the power supply:

1.	Turn off the system and disconnect the AC power cord.
2	Disconnect the three power supply cables from their connectors on the system board.
3.	From the rear of the enclosure, remove the four power supply screws (1).
4	Remove the two screws which hold the power supply to the bottom of the enclosure (2).
4.	Lift the power supply upward (3) out of the retaining flanges and remove it.

To replace the power supply:

1.	Slide the replacement power supply downward into the enclosure so that it engages the two retaining flanges.
2.	Replace the two screws which secure the power supply to the bottom of the enclosure, but do not tighten them yet..
3.	Replace the four screws from the rear of the enclosure.
4.	Tighten the two screws which secure the power supply to the bottom of the enclosure.
5.	Connect the three power supply cables to their connectors on the system board (each connector is a different size, so you will be able to connect them only to the correct cable).
7.	Replace and secure the enclosure cover.
8.	Reconnect the AC power cord and turn on the system.


Removing and Replacing DIMMs
Field-Replaceable Units (FRUs)
Removing and Replacing Dual Inline Memory Modules (DIMMs)

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

To remove a DIMM:

1.	Review the configuration rules for memory if you are not familiar with them.
2.	Turn off the system and disconnect the AC power cord.
3.	Unlock and remove the enclosure cover.
4.	Remove the DIMM by releasing the end latches (1) and pulling it gently upwards out of the socket (2). Note:  Keep in mind that you may have to remove other DIMMs to gain access to the failed one.  So that you can return DIMMs to their sockets properly, remember where the DIMMs were placed.

To replace a DIMM:

1.	Install the replacement DIMM into the socket (3) and engage both end latches.
2.	Replace and secure the enclosure cover.
3.	Reconnect the AC power cord and turn on the system.


Removing and Replacing the System Board
Field-Replaceable Units (FRUs)
Removing and Replacing the System Board

CAUTION:  Always wear a grounded wrist strap when servicing internal components of the AlphaStation 500 Series system.

  Internal cut-away view of the system     [image]  Diagram of system board components

To remove the system board:

1.	Turn off the system and disconnect the AC power cord.
2	Remove the enclosure cover.
3.	Remove the side panel.
4	Remove any PCI cards present in the system.
5	Remove the PCI riser.
6.	Snap out the bracket containing the floppy and the left hand storage drive by pushing in on the plastic tabs on either side of the rear of the bracket.  A portion of removing the left-hand storage bay devices depicts this step and the following step.
7.	Remove the SCSI and power cables from the floppy drive and the mass storage drive.  Note the position of the cables so you can reconnect them to the correct devices later.
8	Remove the MAU Ethernet card.
9	Remove the audio card.
10.	Remove the DIMMs.
11.	Remove the system fan.
12.	Remove the cache fan.
13.	Disconnect the power cables from the power supply (at the system board connectors).
14.	Remove the nine system board mounting screws.  The two screws at the front corner of the enclosure are located just inside the locator pin holes (see (1) and (2), below for the positioning of the locator pin holes and the two front screws, respectively).
15.	Gently lift the system board off its locating pins and out of the enclosure.

To install the replacement system board:

1.	Place the system board into the appropriate slots at the rear of the enclosure and onto its locating pins.
2.	Replace the nine mounting screws.
3.	Connect the three power supply cables.
4.	Reinstall the cache fan and its cable.
5.	Reinstall the system fan and its cable.
6.	Reinstall the DIMMs.
7.	Reinstall the audio card and its cables.
8.	Reinstall the MAU Ethernet card and its cables.
9.	Reinstall the left-hand storage bay and reconnect all cables.
10.	Reinstall the PCI riser.
11.	Reinstall any PCI cards you removed and their external cables.
12.	Reconnect any other internal and external cables which you disconnected.
13.	Replace and secure the left side panel and the enclosure cover.
14.	Reconnect the AC power cord and turn on the system.


System Board Components Diagram
Field-Replaceable Units (FRUs)
System Board Components Diagram

Callout Number	Component(s)
1	System board
2	Parallel port (J41)
3	External SCSI (J42)
4	3.5-inch removable media interface connector (Floppy) (J38)
5	Keyboard (top) and mouse (bottom) connectors (J39)
6	Serial ports (COM1, top/COM2, bottom) (J40)
7	Audio card (J36)
8	SROM port (J24)
9	Power connector (+5V sense, -5V sense) (J21)
10	Power connector (+3.43V sense) (J8)
11	Power connector (+12V sense) (J7)
12	LEDs Halt/Reset cable connector (J5)
13	Diagnostic port (for Manufacturing only (J4)
14	Locating pin holes (two positions)
15	Cache fan connector
16	Connectors for DIMM memory modules (J23, J24, J25, J26, J27, J28, J29, J30)
17	Cache
18	System fan connector (J1)
19	EV5 CPU
20	Mounting holes (nine locations)
21	CIA bridge
22	PCI riser card (J34)
23	Media adapter Unit (MAU) connector header (J32)
24	Internal SCSI header (J37)


Glossary

- A -

advanced RISC computing (ARC)

ARC

ASIC

- B -

B-cache

boot block

BIU

bus

- C -

cache memory

CAS

central processing unit (CPU)

checksum

CIA

control and status register (CSR)

control, input/output, and addressing (CIA)

CPU

CSR

- D -

DAC

data switch (DSW)

DCSR

direct memory access (DMA)

dirty parityDIMM

DMA

- E -

ECC

ECL

EDSR

EISA

- F -

flashROM

- G -

GB

GRU

- H -

hard error (HERR)

- I -

IDE

interrupt

interrupt masking

I/O

IOA

IRQ

ISA

- J -

jumper

- K -

Kb

KB

- L -

LED

- M -

mask

maskable interrupt

Mb

MB

MHz

- N -

NMI

nonmaskable interrupt (NMI)

nonvolatile random-access memory (NVRAM)

ns

NVRAM

- O -

OCP

- P -

page table entry (PTE)

parity error (PERR)

PCEB

PEAR

peripheral component interconnect (PCI)

PERR

PTE

- Q -

- R -

RASType hotspot text in this box

RISC

read-only memory (ROM)

- S -

SAC

scatter/gather

SCSI

SERR

SIMM

small computer system interface (SCSI)

soft error (SERR)

SRM

SROM

system reference manual (SRM)

- T -

TLB

- U -

- V -

victim

- W -

- X -

- Y -

- Z -


ARC
advanced RISC computing (ARC)

In the AlphaStation 500 Series system, the console firmware that supports the Windows NT operating system.


CPU
central processing unit (CPU)

The main unit of a computer that contains the circuits controlling interpretation and execution of instructions; the central processing unit holds the main storage, arithmetic unit, and special registers.


DIMM

Abbreviation for dual inline memory module.


DMA
direct memory access (DMA)

A method of addressing memory, a device, or a location by its actual value; in other words, the actual value is not translated or processed prior to use.


DSW
data switch (DSW)

An ASIC component of the AlphaStation 500 Series system; the four DSW ASICs provide the data path between the EV5, memory, and the CIA ASIC (for PCI data).


EISA

Abbreviation for extended industry-standard architecture.


flashROM

In the AlphaStation 500 Series system, the read-only memory that contains console firmware; four 256-KB flashROMs yield a total size of 1 MB.  Certain conditions permit writing to the flashROMs, allowing field updates to the firmware.


GB

A suffix to a numerical value that indicates size in gigabytes (for example, 1 GB); a gigabyte equals 1,073,741,824 bytes.


IRQ

A high-priority signal representing an interrupt request that informs another task of some significant event.


ISA

Abbreviation for industry-standard architecture.


I/O

A reference to input and output functions.


Kb

A suffix to a numerical value that indicates size in kilobits (for example, 512 Kb); a kilobit equals 1024 bits.


KB

A suffix to a numerical value that indicates size in kilobytes (for example, 640 KB); a kilobyte equals 1024 bytes.


LED

Abbreviation for light-emitting diode.


Mb

A suffix to a numerical value that indicates size in megabits (for example, 10 Mb); a megabit equals 1,048,576 bits.


MB

A suffix to a numerical value that indicates size in megabytes (for example, 550 MB); a megabyte equals 1,048,576 bytes.


MHz

A suffix to a numerical value that indicates frequency in megahertz.


ns

A suffix to a numerical value that indicates speed in nanoseconds (for example, 22 ns).


NVRAM
nonvolatile random-access memory (NVRAM)

Random-access memory that retains its contents, even while the system is turned off.  In the AlphaStation 500 Series system, the NVRAM stores setup information for the console firmware--either advanced RISC computing (ARC) or system reference manual (SRM).


PCI
peripheral component interconnect (PCI)

The connection permitting communication between units (distinct from the CPU and physical memory) that can provide the system with input or accept output from it.


RISC

An abbreviation for reduced instruction set computing.


ROM
read-only memory (ROM)

Memory that cannot be altered in normal use of the system--usually a small memory that contains often-used instructions such as microprograms or system software (for example, firmware).


SCSI
small computer system interface (SCSI)

In the AlphaStation 500 Series system, an I/O bus that provides the interface between the system and peripheral devices.


SIMM

Abbreviation for single inline memory module.


SRM
system reference manual (SRM)

In the AlphaStation 500 Series system, the console firmware that supports the Digital UNIX and OpenVMS operating systems.


SROM
serial read-only memory (SROM)

In the AlphaStation 500 Series system, the portion of read-only memory that contains the code to perform power-up initialization and configuration of the central processing unit (CPU) and the input/output (I/O) system.


PCEB

Abbreviation for PCI-to-EISA bridge.


victim

A block of cache-memory data replaced by new data.


ASIC

Abbreviation for application-specific integrated circuit.  The AlphaStation 500 Series system uses six ASICs:

	Four data switch (DSW) ASICs
	One control, input/output, and addressing (CIA) ASIC
	One miscellaneous ASIC called the GRU ASIC


B-cache

In the AlphaStation 500 Series system, a direct-mapped, write-back, ECC-protected plug-in secondary cache partitioned across three required SIMMs.


CIA

Abbreviation for control, input/output, and addressing--an ASIC component of the AlphaStation 500 Series system.  The CIA ASIC accepts the address and command from the EV5 and drives the memory array with the address, row-address selects (RASs), and column-address selects (CASs).  It also provides an interface to the PCI bus.


GRU

In the AlphaStation 500 Series system, a miscellaneous ASIC on the IOD bus that handles both the PCI-interrupt logic and the memory/cache presence-detection logic and generates the data bus used to access the flashROMs.


interrupt

A break in the usual flow of a system or program to perform an external task.


jumper

A short length of wire used either to compete a circuit termporarily or to bypass a circuit.


OCP

Abbreviation for operator control panel.


IOA

Abbreviation for I/O address.


ECC

Abbreviation for error-correction code.


cache memory

A small, high-speed memory placed between slower main memory and the processor.  A cache increases effective memory-transfer rates and processor speed.  It contains copies of data recently used by the processor and fetches several bytes of data from memory in anticipation that the processor will access the next sequential series of bytes.


CAS

An abbreviation for the column-address select signal.


RAS

An abbreviation for the row-address select signal.


page table entry (PTE)

An entry in the process-page table that describes the location and status of a process page.  In a global page table, a PTE describes the location and status of a page of a global section.  In the system page table, a PTE describes the status and location of a page of the operating system.


TLB

An abbreviation for translation lookaside buffer.


SERR
soft error (SERR)

A recoverable error.  A SERR is a wire-OR'd signal that can be driven by several devices at any one time.  SERR reports address parity errors and data parity errors on special cycles; it is sent to the CPU as a nonmaskable interrupt (NMI).


HERR
hard error (HERR)

A nonrecoverable error.


PERR
parity error (PERR)

With even parity, the number of 1's in a set of binary data should be even; with odd parity, the number of 1's should be odd.  Exceptions to either parity type indicate a parity error and generate a PERR signal.  PERR reports data parity errors for all transactions except special-cycle commands; targets use PERR to signal data parity errors to the master device.  (Only one device at a time can drive PERR.)


bus

A flat, flexible cable consisting of many transmission lines (or wires) that interconnect system components to provide commmunication paths for addresses, data, and control information.


BIU

Abbreviation for bus interface unit.


dirty parity

Parity that contains errors, but is allowed (for example, to troubleshoot data-transmission problems).


DAC

Abbreviation for dual address cycle.


SAC

Abbreviation for single address cycle.


ECL

Abbreviation for emitter-coupled logic.


CSR
control and status register (CSR)

A register that resides in the processor's I/O space and contains control and status data pertaining to a device or controller.


S/G
scatter/gather

Pertaining to the ability to transfer data in one I/O operation either from discontiguous pages in memory to contiguous bolocks on disk or from contiguous blocks on disk to discontiguous pages in memory.


checksum

A sum of digits or bits used to verify the validity of a number or an operation.


PEAR

Abbreviation for PCI Error Address register.


EDSR

Abbreviation for Error and Diagnostic Status register.


DCSR

Abbreviation for Diagnostic control and status register.


NMI
nonmaskable interrupt (NMI)

Nonmaskable interrupts (NMIs) are interrupts that cannot be ignored.  In the AlphaStation 500 Series system, NMIs originate on the PCI/EISA bridge chip (for example, address parity errors on the PCI bus and parity errors on expansion modules plugged into the ISA bus).


mask

To disable or enable functions by writing specific bit patterns to a register.


interrupt masking

The method of defining whether a specified interrupt is ignored.


IDE

Abbreviation for internal drive electronics.


boot block

A block in a file of a system disk that contains a program for loading the operating system into memory.