Copyright: Copyright « 1996 Digital Equipment Corp


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AlphaStation 300 Service Information Team

Questions or comments about this documentation can be sent to:

Kathe Rhoades

lando::rhoades or rhoades@lando.enet.dec.com


Press an Action Button

There is nothing of interest here. Click on ENTRANCE to go to the Main menu, or click on EXIT to exit this file.


AlphaStation 300 Service Information Table of Contents


Digital AlphaStation 250 Series Service Information - Draft Notes

This draft version of the Service Information is based on the following:

Please send your comments to WREATH::DONALD.


Copyright and Trademarks

Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe or existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.

Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid written license from Digital or an authorized sublicensor.

Copyright © Digital Equipment Corporation 1996.  All rights reserved.

The following are trademarks of Digital Equipment Corporation:, AlphaGeneration, AlphaServer, OpenVMS, ThinWire, the AlphaGeneration logo, and the DIGITAL logo.

Windows NT is a trademark of Microsoft Corporation.  UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd.

All other trademarks and registered trademarks are the property of their respective holders.


AlphaGeneration
Welcome to the fast world of AlphaGeneration systems.  Performance has arrived on your desktop.  Fasten your seatbelt and hang on for the ride of your life!


Copying and Printing Popup Displays

Normally information contained in popup displays can not be copied or printed.  The AlphaServer 300 Service Information makes provisions to allow you to copy and print popups.

Copyable and printable popups have a hotspotted title line.  Simply click on the title and the popup will become a main window topic.  You may now copy or print the text using the File and Edit menus on the menu bar.  When done, click on the Back button to return to the parent topic of the popup.


Who is the Audience?
Audience

The primary audience of the AlphaServer 300 Service Information is Digital's Multivendor Customer Services organization.  Secondary audiences include customers who maintain their own systems, and value added resellers (VARs).


Disoriented?
Getting Disoriented?

Do you find yourself losing track of where you are in the service information?  A couple of buttons will help keep you on track.  The BACK button will take you backwards a topic at a time along the path you have already traveled.  For example, if you click on the topic title of a popup, the popup becomes the main topic to facilitate printing and copying the information.  To return to the previous topic, click on the BACK button.

The other button that will help cure disorientation is the CONTENTS button.  Just click on this button and you will be brought back to the main menu screen.


For More Information

	Digital AlphaServer 300 User's Guide	EK-AS300-UG
	DECchip 21064-AA Microprocessor Hardware Reference Manual	EC-N0079-72
	PCI Local Bus Specification, Revision 2.0	PCI Special Interest Group, order number 281446-001


AlphaServer 300 Overview

Overview Menu

Features

Your AlphaServer 300 system has the following features:

  DECchip 21064A (4/266)
  2 MB Bcache
  Up to 512 MB of system memory
  Local bus architecture - 32-bit, 33MHz PCI
      (also includes ISA bus)
  Easy upgradability: three expansion slots,
      four drive bays
  10BaseT and 10Base2 Ethernet
  Choice of operating system: Windows NT
      Server, DIGITAL UNIX, or OpenVMS
  3-year warranty

Specifications:

  Physical
  Electrical
  Environmental


Mechanical Specifications
AlphaServer 300 Overview
Mechanical Specifications

Height:	99.75 mm (3.9 inches)
Width:	425.0 mm (16.7 inches)
Depth:	400.0 mm (15.75 inches)
Weight:	11-14 kg (25-30 lbs)


Electrical Specifications
AlphaServer 300 Overview
Electrical Specifications (for the 210 W power supply)

Auxiliary AC output	2 Amps max at 115 volts (1 Amp at 230 volts) (CAUTION: Some monitors draw more than 2 Amps.)
DC Outputs	Max Load	Max Power	Ripple  (Peak to Peak)
+3.3 V	35.0 Amp	115.5 W	50  mV
+5.0 V	30.0 Amp	150.0 W	50  mV
-5.0 V	0.3 Amp	1.5 W	150  mV
+12.0 V	4.6 Amp	55.2 W	100  mV
-12.0 V	0.3 Amp	3.6 W	150  mV
	Total	210   W

Note: The maximum power from any combination of +3.3 V and +5.0 V together does not exceed 150 W.


Environmental Specifications
AlphaServer 300 Overview
Environmental Specifications

Operating temperature range	10 [image] C to 40 [image] C
Maximum rate of change	11 [image] C per hour
Relative humidity	20% to 80% with diskette or tape
Altitude	2400 meters (8000 feet) @36 [image] C
Acoustic - power	4.8 B LWAd (Idle), 4.9 B LWAd (operating)
Acoustic - pressure	39 dBA LpAm (idle), 40 dBA LpAm (operating)


Front View of the System


AlphaServer 300 Overview
Front View of the System

1.	Power on indicator
2.	Disk activity indicator
3.	Reset button
4.	3.5-inch floppy drive
5.	Floppy drive diskette eject button
6.	Power switch
7.	CD-ROM eject button
8.	CD drive (optional)
9.	Storage bay for optional hard drive
10.	Louvered air intake (Do not block air intake.)


Rear View of the System


AlphaServer 300 Overview
Rear View of the System

1.	AC voltage selection switch
2.	Keyboard connector
3.	Enclosure lock
4.	Twisted pair connector (10BaseT)
5.	ThinWire connector (10Base2)
6.	ISA expansion slot (for half-size ISA options only)
7.	PCI/ISA combination slot
8.	PCI expansion slot (In this example a PCI graphics adapter is shown.)
9.	Security loop
10.	Diagnostic LED viewing ports
11.	External SCSI port
12.	Enhanced bi-directional parallel port
13.	Serial line unit connectors
14.	Mouse connector
15.	AC input


Block Diagram


Block Diagram (Hot spotted)


Block Diagram - SROM
SROM

The Serial ROM (SROM) and the SROM bus are necessary for initial program load and diagnosis of the DECchip 21064A.  The SROM is 8 KB and contains code to perform power-up initialization and configuration of the CPU and I/O system.


Block Diagram DECchip 21064
DECchip 21064A

The DECchip 21064A is the system's CPU.  The chip includes integer and floating-point units and the primary caches.  The DECchip is a CMOS super-scalar, super-pipelined, dual instruction issue processor with the following features:

	266 MHz internal clock rate (model 4/266)
	3.3V supply voltage
	Dual-instruction issue
	Pipelined floating-point unit
	Instruction cache - 16 KB on-chip physical direct-mapped.  An Icache block (or line) contains 32 bytes of instruction stream data.
	Data cache - 16 KB on-chip write-through, direct-mapped, read allocated, physical tagged.  Each Dcache block contains 32 bytes of data.
	Write buffer with four 32-byte entries
	Demand-paged memory management unit with:   12-entry I-stream translation buffer   32-entry D-stream translation buffer
	Parity for the onboard Icache and Dcache memories and the data bus.


Block Diagram Cache
Cache

The secondary cache  has the following features:

	2 MB, single-set, direct-mapped, write back, allocate on read and write
	132 bits wide (128 data bits plus 4 parity bits)
	Cache line size = 32 bytes
	16K tag store containing: 11-bit tag address, 3-bit control and 2-bit parity


Block Diagram FlashROM
FlashROM

The flashROM is used to store firmware.  There are four 256-KB flashROMs for a total size of 1 MB.  Under certain conditions, the flashROMs may be written, which allows field updates to the firmware.


Block Diagram LEDs
LEDs
The serial ROM (SROM) initialization program, the diagnostic ROM (DROM) power-on self-test program, and the console firmware (ARC and SRM), send codes to the LEDs.  If there is a failure, the status code displayed in the LEDs can help you isolate the problem.


Memory SIMMs

The main memory system has the following features:

	Eight industry-standard 72-pin SIMM sockets arranged in two banks: 0 and 1.  A bank consists of four SIMMs. (The SIMMs within a bank must be the same size.)
	Total size ranges from 32 MB to 512 MB.
	70 ns access time SIMMs.
	Each bank (4 SIMMs) is 132 bits wide (128 data bits and 4 parity bits).


PCI to SCSI Adapter

The PCI-based SCSI controller is an NCR 53C810.  It supports 8-bit, single-ended fast SCSI-2 peripherals.  It supports devices at speeds from 5 MB/second (asynchronous) to 10 MB/second (synchronous - fast SCSI).  The system supports internal SCSI peripherals as well as those external to the system unit.  Up to seven peripherals may be on the SCSI bus.

The default device ID of the SCSI controller is 7.


Real-Time Clock (TOY)

The real-time clock is a BQ3287.  The chip contains time and date information and has a provision to periodically interrupt the CPU.  The chip also contains 50 bytes of nonvolatile RAM.


ISA Bus

The ISA bus originates at the ISA bridge on the riser card.  In addition to the two ISA slots on the riser card, the ISA bus connects to the super I/O chip (adapter for the floppy disk, two serial lines, and parallel port), the time-of-year clock (TOY), the sound card slot, and the keyboard/mouse controller.

ISA bus data width: 16 bits


Super I/O Chip

The super I/O chip (National 87332) connects the ISA bus to the following:

  Floppy disk controller (FDC) - a tape backup drive may also use this bus.

  Two serial lines (UARTs).

  Enhanced bi-directional parallel port.


Keyboard Controller

The keyboard controller chip (8242) ties the keyboard and mouse to the ISA bus.


Non_Volatile RAM
Nonvolatile RAM

The nonvolatile RAM (NVR) is an 8-KB device.  The NVR retains its contents, even while the system is turned off.  The NVR is used to store setup information for the console firmware (ARC and SRM).  The NVR is accessed from the main memory data bus through the ROM interface.


Memory Bus

The memory bus connects the data path portion of the core logic chip set to main memory and the ROM interface.

Width to/from memory:  128 bits plus 4 parity bits (one for each longword)

Width to/from ROM interface: 32 bits ( [31:8] for addressing and [7:0] for data )


PCI Bus

The Peripheral Component Interconnect (PCI) is a 32-bit-wide multiplexed address/data bus with a clock speed of 33.33 MHz (allowing a transfer rate of up to 132 MB per second).

The PCI bus provides the system with its primary I/O interconnect.  The PCI bus originates in the PCI bridge portion of the core logic chipset.  Two PCI expansion slots, a SCSI-2 controller, the Ethernet LAN controller, and the ISA bridge are on the PCI bus.

PCI bus width: 32 bits (AD[31:0])

An even parity bit (PAR) is calculated on 36 bits ( AD[31:0] and C/BE[3:0] ).


ISA Bridge

The ISA bridge manages traffic flow between the PCI bus and the ISA bus.  The bridge is an Intel 82378 system I/O chip located on the riser card.  The bridge also provides a utility bus interface to the mouse and keyboard controller, and the time-of-year clock.


ISA Slots
ISA Expansion Slots

There are two ISA expansion slots on the riser card.  The upper ISA slot shares its position with the lower PCI slot, so the option in this position can be either PCI- or ISA-based.  The lower ISA slot is for half-size ISA options only.


PCI Bus Expansion Slots

There are two PCI expansion slots located on the riser card.  The slots accommodate full-sized 32-bit PCI options requiring +5V and/or +3.3V DC.  The lowermost PCI slot shares its position with the uppermost ISA slot, so options in this position can be either PCI- or ISA-based.


ROM Interface

The ROM interface handles the traffic between the main memory data bus and the devices on the flashbus.  The flashbus devices are accessed by setting up an index register and then accessing a data register to either read or write data.

The ROM interface uses memory data bus [31:8] for address and control information and [7:0] for data.


Memory Control

The memory control is part of the core logic.  The major features of this area are:

	Control for filling Bcache and extracting victims on CPU-initiated transactions.
	Control for probing the Bcache on DMA transactions (and invalidating on DMA write hits).
	Provides sysBus arbitration.
	Stores addresses for the four cache-line deep memory write buffer.
	Controls the loading of the I/O write buffer and the DMA read buffer.


Decode
Data Path

The data path is part of the core logic.  The major functions provided by the data path are:

	The error logic supports longword parity.  Error checking is done on DMA transactions.  On CPU-initiated transactions, the CPU performs this function.
	The memory write buffer contains four entries.  Each entry is a cache line (32 bytes).  Data stored in this buffer has been through all coherency checks and is written to memory in the order in which it was received.
	The memory read buffer is a one-cache line temporary holding buffer used to hold data read from memory until it can be sent to the CPU or the DMA read buffer.
	The merge buffer is a one-cache line temporary holding buffer used to hold CPU data on memory writes.
	The I/O write buffer has two entries of one cache line each.  They act as buffers for CPU write data directed toward the PCI bridge or PCI bus.
	The DMA read buffer stores data that is being read from memory by a device on the PCI bus.  The buffer is two cache lines deep.
	The DMA write buffer stores four cache lines of PCI memory write data.  After cache coherency checks are performed, the buffer is unloaded.


Memory Address
Memory Address Bus

The memory-control portion of the core logic supplies the memory address over this bus to the main memory SIMMs.  Along with 12 address bits, RAS/CAS signals are sent to the SIMMs.


epiBus

The PCI bridge logic communicates with the data path logic using the epiBus.

epiBus width: 32 bits


System Data Bus

The system data bus connects to the CPU, Bcache, memory control, and data paths.

System data bus width: 128 bits plus 4 parity bits (one for each longword)


System Address Bus

The system address bus connects the CPU, Bcache, memory control, and the PCI bridge.  The bus is 29 bits wide.


FlashBus

The flashbus ties the ROM interface logic to the flashROM, DROM, NVR, and LEDs.

Flashbus data width: 8 bits


PCI
PCI Bridge

This logic functions as a bridge between the PCI and the CPU, Bcache, and memory.  The PCI bridge logic has the following features:

	Scatter/gather mapping from the 32-bit PCI address to the 34-bit physical address.  Address translations are speeded up by an eight-entry translation lookaside buffer (TLB).
	Sparse and dense space addressing is supported.
	Stores address information for the DMA write buffer and I/O write buffer.


Diagnostic ROM

The 64-KB diagnostic ROM (DROM) contains power-on self-test code (POST).  The DROM code is executed after being successfully loaded by the SROM code.  Following successful completion of POST, the DROM code loads and starts the appropriate flashROM (either the ARC or SRM console firmware).  Alternatively, if there was a flashROM problem, the DROM code attempts to boot a floppy diskette .


Sound Card

The AlphaServer 300 sound card provides 16-bit stereo-quality audio with line in/line out capability.  The card plugs into a dedicated option slot and is accessed through the ISA bus.  A headset and microphone are standard.  The sound card drives the internal speaker and supports audio from the CD-ROM drive (if present).  The sound card is compatible with the Microsoft Sound Card.


Ethernet LAN Controller

The Ethernet LAN controller is a DECchip 21040 located on the riser card.  A cable attaches the controller chip to the media adapter unit (MAU) located on the rear bulkhead.  The MAU furnishes connections for twisted pair (10BaseT) and ThinWire (10Base2).


Scatter/Gather
Scatter/Gather Address Translation

Incoming 32-bit PCI memory addresses have to be mapped to the 34-bit physical memory space.  The mapping can be either direct (physical mapping with an extension register) or scatter/gather mapped (contiguous virtual pages can be mapped to pages scattered throughout physical memory).

When scatter/gather mapping is enabled, the translated address is generated by performing a scatter/gather map table lookup.  The translated base register specifies the starting base address of the scatter/gather map table.  Bits of the incoming PCI address are used as an offset from the base address of the table to form the address of a page table entry in the map.  The page table entry contains the physical address of the page.  PCI address bits [12:5] are appended to the page address to form the physical memory address.

The scatter/gather map table is stored in memory.  The PCI bridge incorporates an 8-entry translation lookaside buffer (TLB) to improve scatter/gather performance.


PCI Sparse Memory Space Definition
PCI Sparse Memory Space (2 0000 0000 - 2 FFFF FFFF)

Sparse memory space is a region in which the lower bits of the CPU address, [7:3], indicate the transfer size.  This space provides byte, word, or tribyte granularity, which the PCI bus requires.  CPU address bits [31:8] are sent out on the PCI bus as PCI AD[26:3].  If CPU address [31:29] is zero, host address extension register 0 (HAXR0) supplies PCI AD[31:27].  If CPU address [31:29] is non-zero, HAXR1 supplies PCI AD[31:27].


PCI Dense Memory Space Definition
PCI Dense Memory Space (3 0000 0000 - 3 FFFF FFFF)

Dense memory space is a region in which the minimum access granularity is a longword.  There is a one-to-one mapping between the CPU address and the PCI address.  In other words, a longword address from the CPU maps to a longword on the PCI bus.

Dense space is typically used for data buffers on the PCI.


What is ARC?

ARC (for Advanced RISC Computing) is the console system that supports the Microsoft Windows NT Server operating system.  ARC does not support the Digital UNIX or OpenVMS operating systems (they use the SRM console).

The ARC console is a menu-driven system.  The ARC console code resides in a portion of the system flashROMs.  The design goal was to hide the complexities of older console designs from the console user.  For example, you do not need to remember actual environment variable names, just make a selection from a list of choices.


What is SRM?

SRM (for Alpha System Reference Manual) is the console system that supports the Digital UNIX or OpenVMS operating systems.  SRM does not support the Microsoft Windows NT Server operating system (It uses the ARC console).

The SRM console has a command line interface.  The SRM console code resides in a portion of the system flashROMs.  It is evident when typing help, that this is a substantial console.  That means the SRM is more suited as a troubleshooting tool than other consoles.  During troubleshooting, you might need to switch to the SRM console to locate an otherwise unobtainable piece of information.


Serial Line Units

The serial line units (SLUs) support full MODEM control.  The baud rates supported by the serial line units are:

50	75	110	134.5
150	300	600	1200
1800	2000	2400	3600
4800	7200	9600	19200
38400	57600	115200

Refer to the operating system documentation to confirm which baud rates from the preceding list are supported by the operating system.

The name each SLU is recognized by is dependent on the operating system.  For example, with the OpenVMS AlphaServer 300 with a graphics console (console = graphics), COM1 is OPA1 and COM2 is TTA0.  If there is a serial console (console=serial), then COM1 is OPA0 (COM2 does not change).


Configuring the system

Configuration Menu


Basic Configurations
Basic Configuration Information


Configuring the AlphaServer 300
Basic Configuration Information

AlphaServer 300 systems include:

	CPU module with a DECchip 21064A (model 4/266).
	One PCI slot, one PCI/ISA combination slot, and one half-size ISA expansion slot.
	Eight SIMM sockets and parity-protected main memory.
	Integrated PCI-based SCSI-2 controller with DMA and an external hi-density SCSI-2 connector on the rear panel.
	Factory-installed operating system (DIGITAL UNIX, OpenVMS).  Microsoft Windows NT Server is not factory installed.
	1.44-MB, 3.5-inch floppy disk drive.
	Two serial ports and one bi-directional enhanced parallel port.
	PS/2 style keyboard and mouse ports.
	Keyboard and three-button mouse.


Windows NT Based AlphaServer 300 Package

Order Number	Memory	Hard Disk	CD-ROM	Graphics	Floppy Disk	16-Bit Audio
PB462-AA (4/266)	32 MB	535 MB PBXRZ-CA	RRD43 PBXRD-AA	Order separately	1.44 MB PBXRX-AA	With headset and mic.
All models include an embedded Ethernet controller.


Digital UNIX Based AlphaServer 300 Package

Order Number	Memory	Hard Disk	CD-ROM	Graphics	Floppy Disk	16-Bit Audio
PB460-AA (4/266)	64 MB	1.05 GB PBXRZ-EA	RRD43 PBXRD-AA	Order separately	1.44 MB RX23L-AA	With headset and mic.
All models include an embedded Ethernet controller.


OpenVMS Based AlphaServer 300 Package

Order Number	Memory	Hard Disk	CD-ROM	Graphics	Floppy Disk	16-Bit Audio
PB461-AA (4/266)	64 MB	1.05 GB PBXRZ-EA	RRD43 PBXRD-AA	Order separately	1.44 MB RX23L-AA	With headset and mic.
All models include an embedded Ethernet controller.


Internal Mass Storage Bays


Configuring the AlphaServer 300
Internal Mass Storage Bays

The AlphaServer 300 enclosure has four internal mass storage bays.

1.  The outer bay lower area can hold one 5 1/4-inch half-height, front-accessible or non-accessible storage device.  Due to thermal restrictions, hard drives cannot be installed in this bay.

2.  The outer bay upper area contains a standard 3.5-inch 1.44 MB floppy drive.  The floppy disk is controlled by the floppy disk controller (FDC).  The FDC is capable of controlling up to two drives.

3.  The inner bay lower area can hold a 3.5-inch low-profile front accessible or non-accessible device.

4.  The inner bay upper area can contain a 3.5-inch non-accessible device.  The first hard disk is normally located here.


Expansion Card Configuration
Configuring the AlphaServer 300
Expansion Card Configurations

The AlphaServer 300 supports both PCI and ISA options.  There is one PCI slot, one combination PCI/ISA slot, and one half-size ISA slot.  An expansion option in the combination slot may either be an ISA option or a PCI option - but never both at the same time.

The following configuration rule applies to the slots:

If the system has:	Then the system may have up to:
Two PCI-slot options	One ISA-slot option
One PCI-slot option	Two ISA-slot options
No PCI-slot options	Two ISA-slot options
  Click here to return to the Configuration Menu.


Memory Configuration


Configuring the AlphaServer 300
Memory Configuration

The AlphaServer 300 memory may range from 32 MB to 512 MB.  The 70 ns DRAM memory plugs into the motherboard as two groups of four SIMMs (eight sockets).

A populated bank of memory must contain four SIMMs of the same capacity.  There are no restrictions on the physical ordering among the banks when using different sized bank pairs.  For example, the SIMMs in bank 0 may be larger or smaller than the SIMMs in bank 1.  The initialization code will set the base address of the largest bank to the lowest address.


Console Configuration


Configuring the AlphaServer 300
Console Configuration

The AlphaServer 300 flashROMs contain two console systems:

1.	ARC, which supports Windows NT.

2.	SRM, which supports DIGITAL UNIX and OpenVMS.

In the SRM console, the os_type environment variable selects the console to be loaded.  Use the SRM set command to set os_type to one of the following values: UNIX, OSF, VMS, or NT.  (Either OSF or UNIX will set the os_type to Digital UNIX.)

Either a graphics monitor connected to the VGA module at the rear of the system or a serial terminal connected to the COM1 serial port can be used as the console terminal.  If the system is running Windows NT, a graphics monitor is required.  The value of the console environment variable (serial or graphics) determines the device.

Use the set console serial command to set the console to display output to a serial terminal.

Use the set console graphics command to set the console to display output to a graphics monitor.

If you are using the ARC console and wish to switch to the SRM console, go to the ARC Setup menu and select the Switch to OpenVMS or Switch to Digital UNIX menu items.

Configuration information is stored in the NVRAM on the motherboard.  If the motherboard or the battery on the motherboard is replaced, the information in the NVRAM and real-time clock is lost.  Keep records of the configuration (IRQs, DMAs, I/O addresses, and so forth) to facilitate getting the system back into use after motherboard replacement.


PCI Device Configuration


Configuring the AlphaServer 300
PCI Device Configuration

The console firmware performs the following PCI-configuration tasks:

Task		Action
Determine what PCI devices are present.		Try to read the ID registers.
When a device is located, determine its address space requirements.		All 1's are written to its base address register. Device returns the address bits it uses set to 1's, all others are 0's.
Initialize the base registers		Set up all base address registers in order from largest to smallest.
Determine interrupt assignments		The SRM console uses the configuration database to first identify ISA bus IRQ assignments.  It then assigns open IRQs to the PCI devices. The ARC console assigns IRQs to the PCI devices as follows: IRQ10 to Ethernet (on riser card) IRQ15 to PCI slot 1 IRQ9 to PCI slot 2 IRQ11 to the embedded SCSI
The PCI specification defines three physical address spaces.  Besides the usual memory and I/O space, there is configuration address space.  Configuration address space allows the devices to be initialized and configured by software/firmware.  PCI devices have 256 bytes of configuration register information.  Of the 256 bytes, 64 bytes are the predefined header region.  The remaining 192 bytes are device specific.

The PCI bus must be initialized each time the system is powered on.  Configuration cycles (accesses to CPU addresses 1 e000.0000 through 1 fff.ff80) are used for this purpose.  The initialization device select (IDSEL) input is used to select a PCI device during configuration read and write transactions.  The AD bits associated with the PCI devices in the AlphaServer 300 are shown below:

Device	IDSEL Bit Assignment	PCI Base Address	CPU  Base Address
SCSI	AD[17]	0002.0000	1 e006.0000
ISA Bridge	AD[18]	0004.0000	1 e007.0000
Ethernet (on riser)	AD[22]	0040.0000	1 e00b.0000
PCI Bus Slot #1	AD[23]	0080.0000	1 e00c.0000
PCI Bus Slot #2	AD[24]	0100.0000	1 e00d.0000

CPU base address <20:16> represents the encoded value of the IDSEL bit to be asserted (IDSEL bits range from PCI AD<31:11>).  For example, in a CPU base address of 1.e006.0000, the encoded IDSEL value is 06.  Starting at PCI AD<11> and counting up 7 bits (0-6), points to PCI AD<17>, which is hardwired as an IDSEL line to the SCSI controller.


PCI Expansion Slots

The two PCI expansion slots are each unique.  PCI slot 1 is hardwired to IDSEL bit <23>.  This bit is used during the configuration cycle.  PCI slot 2 is hardwired to IDSEL bit <24>.  Another PCI device, the Ethernet LAN controller, is mounted permanently on the riser card.  It is hardwired to IDSEL bit <22>.


ISA Expansion Slots

The two ISA slots are electrically identical to each other.  The uppermost ISA slot is capable of holding a full-height ISA option.  The lower ISA slot is restricted to half-size ISA options.


PCI Configuration Space Header
PCI Predefined Header Region


SCSI Bus Configurations


Configuring the AlphaServer 300
SCSI Bus Configurations

The SCSI controller (NCR 53C810) is a PCI option mounted on the motherboard.  The controller supports a total of seven internal and external fast SCSI-2 devices (up to three internal and the rest external).  Termination is required at both the internal and the external ends of the SCSI bus.

The internal SCSI bus cable connects to the motherboard at (1).  The daisy-chained cable has a connector (2) available for a device in the lower section of the bay.  The system hard drive (3) is normally in the upper section of the bay.  If present, the CD-ROM drive (4) will be the last internal device on the bus.  If (2) is empty, the end of the cable must be connected to the hard drive (3).

For more information:
  SCSI bus length restrictions
  Guidelines when adding internal SCSI devices
  Internal termination
  External termination


SCSI Bus Length

The total SCSI bus length, including internal cables and etch on the motherboard as well as the external cables between storage enclosures and the cables inside the storage enclosures, must not exceed three meters (9.8 feet) for fast SCSI operation or four meters (13.1 feet) for slow SCSI (5 Mbyte/second) operation.  The AlphaServer 300 system's internal SCSI length is about 1.4 meters (4.6 feet), leaving 1.6 meters (5.25 feet) available for external fast SCSI use (2.6 meters (8.5 feet) for slow SCSI).


SCSI Bus Internal Termination

The last drive on the internal SCSI bus cable must supply the terminator.  If you add devices on the internal SCSI bus, make sure their termination is disabled.  Refer to the appropriate drive manual.


SCSI Bus External Termination

  When no external SCSI peripherals are present, the external portion of the SCSI bus is automatically terminated on the motherboard (see number 1 in the figure).  When an external SCSI cable is present, the automatic termination is turned off and termination must be provided by the last external SCSI device.  If you add external SCSI peripherals (see number 2 in the figure), make sure the last peripheral on the external SCSI bus is properly terminated.


Adding Internal SCSI Devices Guidelines
Guidelines When Adding Internal SCSI Devices

	Use the end connector of the internal SCSI cable to reach the lower outer storage bay (typically used for a CD-ROM drive).
	SCSI devices using a daisy-chained connector must not have their terminator enabled.
	The last drive gets the end connector of the cable.
	The last drive must supply the terminator.


ISA Bus Configurations


Configuring the AlphaServer 300
ISA Bus Configurations

The AlphaServer 300 has a built-in ISA device as well as slots for up to two additional ISA options.  The built-in device is a super I/O chip (National PC87332) which provides controllers for the floppy disk bus, two serial lines, and the bi-directional enhanced parallel port.

Before you add ISA options to an OpenVMS or DIGITAL UNIX system, use ISACFG to add the new options to the configuration database.  If an option is added to the system without the database being updated, and the operating system is booted, the system could hang.  The SRM console uses the configuration database to determine PCI assignments.  If the SRM console does not know about an ISA option, a PCI option might inadvertently be assigned the same IRQ as the ISA option, possibly resulting in a hung operating system.

The OpenVMS operating system also uses a VMS configuration file (ISA_CONFIG.DAT).  Check the OpenVMS operating system documentation for information about maintaining the contents of this file.

NOTE: The ARC console preassigns IRQ 9, 10, 11, and 15 to PCI devices for Windows NT systems.

Use the following procedure when adding ISA options to DIGITAL UNIX and OpenVMS systems:

Action	Result or Next Step
1.  Perform operating system configuration tasks, if any.  Refer to your operating system installation guide and release notes.	The operating system is prepared for the ISA option.  Click here to see ISA addresses.
2.  Shut down the system.	The system is at the SRM console prompt (>>>).
3.  >>>isacfg options	Adds the new ISA option to the SRM console configuration table using the appropriate command options.  (See the ISACFG command for details)
4.  >>>init	Typing init incorporates the changes into the configuration database.
5.  Configure the ISA option.	Use the manual that came with the ISA option to set up the ISA option to match the configuration database.
6.  Turn off the system and install the ISA option.	The option is mounted in the system.
7.  Turn on the system and boot.	The operating system boots and sees the new ISA option.


Interrupts


Configuring the AlphaServer 300
Interrupts

Take care to avoid setting up interrupt conflicts.  Click on the blocks below for more information about the interrupt system.


CPU Interrupts

Name	irq_h	Source	Comments
ERR_IRQ	0	Core logic	CPU bus and parity errors
Not used	1
INT	2	PCI/ISA bridge	8259 compatible types (ISA and PCI device interrupts)
NMI/SERR	3	PCI/ISA bridge	Non-maskable interrupts (IOCHK and SERR)
IRQ8	4	TOY	Real-time clock
HALTREQ	5	Front panel switch	Controlled by jumper J3


IRQ Assignments

The timer, keyboard, and mouse are hardwired to IRQs 0, 1, and 12 respectively.  The parallel port (LPT1) is assigned to IRQ7, although it is possible to use IRQ5.

IRQ8, normally the interval timer interrupt, is not connected in theAlphaServer 300.  The timer interrupt signal (IRQ8) is routed directly to the CPU instead.

IRQ13, normally used to signal a coprocessor error or signal the end of a DMA scatter/gather operation, is not connected in the AlphaServer 300.


PCI IRQ Assignments

Single-function PCI devices have PIRQ numbers based on the device's location.  In the AlphaServer 300 the PIRQs are wired as follows: embedded Ethernet to PIRQ0, PCI slot 1 to PIRQ1, PCI slot 2 to PIRQ2, and the embedded SCSI controller to PIRQ3.

Console firmware sets bits in the route control registers to assign a PIRQ to an IRQ level.  The available IRQ levels are 5, 9, 10, 14, and 15.  The SRM console assigns the IRQs to PCI devices based on what IRQs are already allocated to ISA devices.  The ISA IRQ allocation data is contained in the configuration database, which is maintained with the ISACFG command.  For example, since the parallel port is assigned to IRQ7, the SRM console will not assign a PCI device to that IRQ.  You must update the configuration database before physically adding an ISA option.  This ensures that a PCI device will not receive an ISA device's IRQ, which could cause the system to hang.  Because the ISA IRQ values stored in the database are used to determine the PCI IRQ assignments, it is important to leave enough IRQs available for the PCI options on the system.

Windows NT has hardcoded the PIRQ to IRQ assignments.  Keep these in mind when adding ISA options to a Windows NT system.  The assignments are:

PIRQ0 (Ethernet)	to   IRQ10
PIRQ1 (PCI slot 1)	to   IRQ15
PIRQ2 (PCI slot 2)	to   IRQ9
PIRQ3 (SCSI)	to   IRQ11


ISA IRQ Assignments

To prevent conflicts, exercise care when assigning interrupts.  When assigning IRQs to ISA devices on a DIGITAL UNIX or OpenVMS system, remember to update the console configuration database with the ISACFG command before adding the option.  Make sure enough IRQs remain available for the PCI options on the system.

The available ISA IRQ assignments on systems running Digital UNIX or OpenVMS are IRQ 5, 9, 10, 14, and 15.  On systems running Windows NT, the ARC console preassigns IRQ 9, 10, 11, and 15 to PCI devices, if they are present.

If the system has three of these IRQs assigned to ISA options, two remaining IRQs would be available for PCI options (the Ethernet controller and one of the PCI slots on the riser card).

IRQ7 is assigned to the parallel port, and IRQ11 is assigned to the SCSI controller. (Note: The operating system may use polled I/O to access the parallel port, therefore freeing IRQ7.  This is the case with DIGITAL UNIX and Windows NT systems.)

By disabling an existing ISA device with the ISACFG -enadev 0 command, another IRQ could be made available.


IRQ Controller

The interrupt controller is the functional equivalent of two 82C59 controllers and is located in the PCI to ISA bridge chip.  IRQ2 on the master controller is used to cascade the controllers together.  This means that IRQ8-IRQ15 have a higher priority than IRQ3-IRQ7.


DMA Channel Assignments


Configuring the AlphaServer 300
DMA Channel Assignments

The ISA interface uses eight DMA channels.  DMA channel 4 is used to cascade the two four-channel controllers together and therefore is unavailable.

Any DMA channel may be programmed for 8-bit or 16-bit transfers.

Channel	Device
0	Available to: ISA option slots
1	Available to: ISA option slots
2	Floppy Disk Controller
3	Available to: ISA option slots and the parallel port
4	Unavailable (Channels 0-3 are cascaded to this channel)
5	Available to: ISA option slots
6	Available to: ISA option slots
7	Available to: ISA option slots


Address Space Map


Configuring the AlphaServer 300
Address Space Map

Cacheable
0 0000.0000 -	0 ffff.ffff	Main memory
Non-cacheable
1 0000.0000 -	1 7fff.ffff	Non-cacheable memory
1 8000 0000 -	1 9fff.ffff	Memory controller registers
1 a000.0000 -	1 afff.ffff	PCI bridge registers
1 b000.0000 -	1 bfff.ffff	PCI interrupt/special cycle
1 c000.0000	1 dfff.ffff	PCI sparse I/O space (16 MB)  The lower 256 KB of this space is used for addressing PCI and ISA devices.  Click here to see ISA addresses.
1 e000.0000	1 ffff.ffff	PCI configuration space
PCI sparse memory space
2 0000.0000 -	2 ffff.ffe0	128 MB of PCI space (lower address bits carry byte masks and length information).  Used when byte, word, tribyte, longword, or quadword access granularity is required.
PCI dense memory space
3 0000.0000 -	3 ffff.ffe0	4 GB of PCI space.  Used for devices with access granularity greater than a longword.  Typically used for data buffers.


I/O View of Address Space


Configuring the AlphaSever 300
I/O View of Address Space


Halt Request

A halt request may be asserted when you press the front-panel Halt/Reset button.  Jumper J3 determines whether the button generates a halt request or a reset.


Motherboard
Motherboard Configuration


Configuring the AlphaServer 300
Motherboard Configuration

1.	DECchip 21064A CPU
2.	Battery
3.	Diagnostic LEDs
4.	Rear panel connectors
5.	Power connectors (Four from the 210 W power supply or three from the 180 W power supply.)
6.	Floppy drive controller (FDC) connector
7.	Internal SCSI bus connector
8.	DROM
9.	SROM
10.	Memory connectors
11.	Not used
12.	Riser card connector


ISA Device Addresses

All addresses are shown in hexadecimal.

Device	ISA Address	PCI Address	CPU Address
Keyboard	060	0000 0060	1 C000 0C00
Mouse	064	0000 0064	1 C000 0C80
TOY clock	070 - 071	0000 0070	1 C000 0E00
Serial port 1	03F8 - 03FF	0000 03F8	1 C000 7F00
Serial port 2	02F8 - 02FF	0000 02F8	1 C000 5F00
Parallel port	0378 - 0380	0000 0378	1 C000 6F00
Floppy disk controller	03F2 - 03F7	0000 03F2	1 C000 7E40


Console Commands

AlphaServer 300 Console Commands

Console Menu

The AlphaServer 300 system contains two functional consoles:  the ARC console supports the Windows NT operating system, and the SRM console supports the Digital UNIX and OpenVMS operating systems.  The console firmware resides in 1 MB of flashROM on the CPU module.  The flashROMs may be updated in the field.

ARC console commands

SRM console commands

ICONFIG (A Forms-Based Interface to ISACFG)

ISA Configuration Utility (ISACFG)

EWRK3 Configuration Utility (EWRK3_CONFIG)

Console Firmware Update Procedure

PCI Option Firmware Update Procedure

Setting Default Console to ARC or SRM


ARC Commands

AlphaServer 300 Console Commands

ARC Console Commands

The ARC console has a menu interface.  The first menu to come up when the ARC firmware boots is the Boot menu.  From the Boot menu you can boot Windows NT or another operating system or run a program (for example, the ARCINST program).

Alpha Firmware Version 4.49
Copyright (c) 1993-1996 Microsoft Corporation
Copyright (c) 1993-1996 Digital Equipment Corporation

Boot menu:

Boot Windows NT
Boot an alternate operating system
Run a program
Supplementary menu...

Use the arrow keys to select, then press Enter.


Boot Windows NT

Selecting this menu item causes the system to boot the default operating system.  The boot selection identifier, Windows NT in this case, uses values that were set up with the Manage boot selection menu. . . .  The default boot selection identifier is the identifier at the top of the identifier list.

When the Boot Windows NT command is selected, you will see something similar to the following:

OS Loader V3.5

.............

Microsoft (R) Windows NT (TM) Version 3.5

1 System Processor [49128 Kb memory]

Checking file system on C:

The type of file system is FAT.

The volume is clean.

The screen then displays a Microsoft Windows NT Server graphic and the Welcome box appears.


Boot an alternate operating system

This choice will prompt you to boot from a list of all available boot selection identifiers. The default selection is Windows NT.

Boot menu:

Boot Windows NT (Default)
Boot Digital UNIX
Boot OpenVMS

Use the arrow keys to select, then press Enter.


Run a program

Prompts you for a program to run.  The program runs on top of the ARC firmware and must be linked in a special manner.  For example, the formatting and partitioning program, ARCINST, is started in this manner.

Run a program:  A:arcinst


ARC Console Supplementary Menu

AlphaServer 300 Console Commands

Supplementary Menu

The Supplementary menu is selected off the Boot menu and contains the following choices:

Alpha Firmware Version 4.49
Copyright (c) 1993-1996 Microsoft Corporation
Copyright (c) 1993-1996 Digital Equipment Corporation

Supplementary menu:

Install new firmware
Install Windows NT from CD-ROM
Set up the system...
Display hardware configuration
Boot menu...

Use the arrow keys to select, then press Enter.


Install new firmware

This choice allows you to update the system console firmware from the ARC console, using either a FAT-formatted update floppy or the Alpha Systems Firmware Update CD-ROM.  Start the firmware update as follows:

1.   Insert the Firmware Update CD-ROM into the CD drive.  (Or, insert the FAT-formatted update floppy into the diskette drive.)

2.  From the ARC Boot Menu, select Supplementary menu… .

3.  From the Supplementary menu, select Install new firmware.

4.  Complete the update procedure as described in Console Firmware Update Procedure.


Install Windows NT from CD-ROM

Before selecting this choice, insert the Windows NT distribution CD-ROM into the CD drive.


Set up the system...

AlphaServer 300 Console Commands

Setup Menu

The Setup menu is selected off the Supplementary menu.  Use the Setup menu to work with variables, configurations, boot selections, machine-specific setups, and to switch to the SRM console.

Alpha Firmware Version 4.49
Copyright (c) 1993-1996 Microsoft Corporation
Copyright (c) 1993-1996 Digital Equipment Corporation

Setup menu:

Set system time
Set default environment variables
Set default configuration
Manage boot selection menu...
Setup autoboot
Machine specific setup...

Edit environment variables
Reset system to factory defaults

Help
Switch to OpenVMS or Digital UNIX console
Supplementary menu and do not save changes
Supplementary menu and save changes

Use the arrow keys to select, then press Enter.


Set system time

Selecting this choice will prompt you to enter the date and then the time (in 24-hour format).

Enter the new date

Enter month [1-12]: 10
Enter day [1-31]: 08
Enter year [0-9999] 1996

Enter time

Enter hour [0-23]: 14
Enter minutes [0-59]: 43
Enter second [0-59]: 0


Set default environment variables

Selecting this choice will prompt you to set the default system partition. After you have selected the media, ARC prompts you for information such as SCSI bus number, SCSI ID, and partition number.  Press ESC to return to the previous menu.

Enter location of default system partition:

   Select media:
SCSI Hard Disk
Floppy Disk
CD-ROM

Enter SCSI bus number: 0
Enter SCSI ID: 0
Enter partition [must be FAT or NTFS]: 1


Set default configuration

This selection allows you to configure the system floppy drives and keyboard type.  You are prompted for monitor resolution, floppy drive capacity, number of floppy drives, keyboard language, and the SCSI Host ID (typically 7).

Select monitor resolution:
1280x1024
1024x768
800x600
640x480

Select floppy drive capacity:
5.25" 1.2MB
3.5" 1.44MB
3.5" 2.88MB

Select second floppy drive capacity:
5.25" 1.2MB
3.5" 1.44MB
3.5" 2.88MB
None

Select keyboard:
U.S.	101-key keyboard
Japanese	106-key keyboard
French	102-key keyboard
German	102-key keyboard
Spanish	102-key keyboard

.
.
.

Enter SCSI Host ID (0-7) for SCSI bus number 0: 7


Managing Boot Selection Menu...

AlphaServer 300 Console Commands

Boot Selections Menu

The Boot selections menu is selected off the Setup menu.  Use the Boot selections menu to perform tasks associated with maintaining the list of boot selection identifiers.  Click here for a list of the ARC boot selection variables.

Alpha Firmware Version 4.49
Copyright (c) 1993-1996 Microsoft Corporation
Copyright (c) 1993-1996 Digital Equipment Corporation

Boot selections menu:

Add a boot selection
Change a boot selection
Verify boot selections
Delete a boot selection
Dump boot selections
Rearrange boot selections
Setup menu...

Use the arrow keys to select, then press Enter.


ARC Boot Selection Environment Variables
ARC Boot Selection Variables

Variable	Description
LOADIDENTIFIER	The name of the boot selection, for example, Windows NT.  You can specify any string value.  The firmware does not check the string value.
SYSTEMPARTITION	The ARC-defined device name for the partition containing the operating system loader (OSLOADER.EXE for Windows NT).
OSLOADER	The full file name of the operating system loader, including partition device name, directories, and file name.
OSLOADPARTITION	The ARC-defined device name for the partition containing the operating system kernel.
OSLOADFILENAME	The directory name of the root directory for the operating system tree, \WINNT.
OSLOADOPTIONS	A string that is passed to the operating system at load time.  This string can be used to modify operating system behavior.  The firmware does not check the value of this string.


Add Boot Selections
Add a boot selection

Select this choice to add a boot selection identifier. The system will display a series of menus and prompts.  If you have not changed the location of the operating system files, you can use the default answers.  If you have changed the location of the operating system files, you must edit the default answers or choose boot selections other than those provided by the procedure.

Enter location of system partition for this boot selection:

Select media:
   SCSI Hard Disk
   Floppy disk
   CD-ROM

Enter SCSI bus number: 0
Enter SCSI ID: 0
Enter partition (must be FAT or NTFS): 1
Enter the osloader directory and name: \os\winnt\osloader.exe

Is the operating system in the same partition as the osloader:
Yes
No

Enter the operating system root directory: \winnt

Enter a name for this boot selection: Windows NT

Do you want to initialize the debugger at boot time?
Yes
No


Changing a Boot Selection
Change a boot selection

This choice allows you to edit a boot selection.  First choose the boot selection identifier that you wish to edit.  Then use the up and down arrow keys to bring up the environment variable to be changed.  Press Enter to access the current value of the selected environment variable.  When the change is made, press Enter and then ESC to return to the previous menu.

Selection to edit:
Windows NT

    Name:  OSLOADFILENAME
    Value:  \winnt

Environment variables for boot selection 1:

     LOADIDENTIFIER=Windows NT
     SYSTEMPARTITION=scsi()disk(0)rdisk()partition(1)
     OSLOADER=scsi()disk(0)rdisk()partition(1)\osloader.exe
     OSLOADPARTITION=scsi()disk(0)rdisk()partition(2)
     OSLOADFILENAME=\winnt
     OSLOADOPTIONS=nodebug


Checking Boot Selections
Verify boot selections

Use Verify boot selections to perform a validity test on the available boot selections.  If the system detects an error in a boot selection, the system displays the name of the boot selection in which it detected the error, and you are prompted as follows:

Problems were found with:

Windows NT.

Choose an action:

Ignore problems with this boot selection
Delete this boot selection
Change this boot selection
OSLOADPARITION cannot be found, value is:
scsi()disk(0)rdisk()partition(2)


Deleting Boot Selections
Delete a boot selection

Delete a boot selection by using the up and down arrow keys to choose the boot selection identifier you wish to delete.  Press Enter.  Press ESC to return to the previous menu without deleting a selection.

Selection to delete:

Windows NT
Windows NT 2
Windows NT 3


Dumping Boot Selections
Dump boot selections

The dump boot selections command displays all of the boot selections.

LOADIDENTIFIER=Windows NT 2;Windows NT ;Windows NT 3
SYSTEMPARTITION=scsi()disk(0)rdisk()partition(1);
                scsi()disk(1)rdisk()partition(1);
                scsi()disk(0)rdisk()partition(1)
OSLOADER=scsi()disk(0)rdisk()partition(1)\os\nt\osloader.exe;
         scsi()disk(0)rdisk()partition(1)\os\nt\osloader.exe;
         scsi()disk(0)rdisk()partition(1)\osloader.exe
OSLOADPARTITION=scsi()disk(0)rdisk()partition(1);
                scsi()disk(0)rdisk()partition(1);
                scsi()disk(0)rdisk()partition(2)
OSLOADFILENAME=\winnt;\winnt;\winnt
OSLOADOPTIONS=nodebug;nodebug;nodebug

 Press any key to continue...


Rearrange boot selections

Use Rearrange boot selections to reorder the list of boot selections.  Use the up and down arrow keys to choose a selection.  Press Enter to move that selection to the top of the list.  A boot selection identifier that is moved to the top of the list becomes the default boot selection.

Pick selection to move to the top, ESC to exit:

Windows NT
Windows NT 2
Windows NT 3


Setting up Autoboot
Setup autoboot

If you want the system to boot automatically, choose this command and select Yes.  Press Enter and at the next prompt, enter a countdown value.  The default is 10 seconds.

Should the system autoboot:

Yes
No

Enter countdown value (in seconds): 10


Machine Specific Setup
Machine-specific setup

Selecting Machine-specific setup displays the current status of the SCSI termination and PCI parity checking controls. For the AlphaServer 300, the SCSI termination selection has no effect:

1.	SCSI termination	Not used on AlphaServer 300
2.	PCI parity checking	The default for this selection is "off."  It is recommended that you leave the default setting.  See Disabling PCI Parity for more information.


Editing Environment Variables

AlphaServer 300 Console Commands

Edit environment variables

The Edit environment variables selection allows you edit or create user-defined Windows NT system environment variables.

Caution:  Editing the values of the default ARC firmware environment variables could result in corrupted data or make the system inoperable.  Use the Edit environment variables selection only to create or edit your own environment variables.

In the following example, FWSEARCHPATH is defined as the search path to be used by the ARC firmware to locate SCSI devices.

Use Arrow keys to select a variable, ESC to exit:

    Name:  FWSEARCHPATH
    Value: scsi()disk(0)rdisk()partition(1)

Environment variables:
     CONSOLEIN=multi()key()keyboard()console()
     CONSOLEOUT=eisa()video()monitor()console()
     FWSEARCHPATH=scsi()disk(0)rdisk()partition(1)
     TIMEZONE=PST8PDT
     A:=eisa()disk()fdisk()
     LANG_ID= 0
     LANG_SRC = 0
     FLOPPY2=N
     FLOPPY=1
     AUTOLOAD=YES
     COUNTDOWN=10
     KEYBOARDTYPE=0
     VERSION=4.49
     ENABLEPCIPARITYCHECKING=FALSE


ARC Firmware Environment Variables

Variable	Description
CONSOLEIN	The console input device. The default value is multi()key()keyboard()console().
CONSOLEOUT	The console output device. The default value is eisa()video()monitor()console().
FWSEARCHPATH	The search path used by the ARC firmware and other programs to locate particular files. The default value is the same as the SYSTEMPARTITION environment variable value.
TIMEZONE	The time zone in which the system is located. This variable accepts ISO/IEC9945-1 (POSIX) standard values.
A:	The default floppy drive. The default value is eisa()disk()fdisk().
LANG_ID	The language that is to be used in the firmware.  This is set automatically to the appropriate value.
LANG_SRC	Indicates the location of the sources for the Unicode strings used in the firmware. This is set automatically to the appropriate value.
FLOPPY	The capacity  of the default floppy drive, either 1 (1.2 MB), 2 (1.44 MB), or 3 (2.88 MB).
FLOPPY2	The capacity of an optional second floppy drive, either N (not installed), 1, 2, or 3.
AUTOLOAD	The default startup action, either Y (boot) or N or undefined (remain in ARC firmware).
COUNTDOWN	The default time limit in seconds before the system boots automatically when AUTOLOAD is set to yes. The default value is 10.
KEYBOARDTYPE	The keyboard language.  The default is U.S. (English).
VERSION	The ARC firmware version.
ENABLEPCIPARITYCHECKING	When set to the default value (FALSE), disables parity checking on the PCI bus in order to prevent machine check errors that can occur if the PCI device has not properly set the parity on the bus.


Reset system to factory defaults

Reset system to factory defaults will overwrite the environment, configuration, and boot selections with the system defaults.  The command asks for confirmation that you want to do this.


Help

The Help selection is a one-screen aid that shows the steps necessary to set up the system and keys that are used to edit strings and return to a previous menu.

Do the following steps, in this order, to set up the system:

1. Set system time.
2. Set default environment variables.
3. Set default configuration.
4. Create at least one boot selection.
5. Setup autoboot, if desired.

-> A menu item with an arrow represents a section of the NVRAM with a problem.  Select these items (in top to bottom order) to repair the NVRAM before attempting to boot or install Windows NT.

"Reset system to factory defaults" does steps 2  5 for a typical system.

Home, End, Delete, and Backspace will help you edit strings.

The ESCape key returns from a menu, and aborts a sequence.

The firmware automatically reboots if the configuration is changed.

Press any key to continue. . .


Switch to OpenVMS or OSF Console

AlphaServer 300 Console Commands

Switch to OpenVMS or Digital UNIX console

This menu allows you to change to the SRM console on the power off-on cycle.  To change to SRM, select either Switch to OpenVMS or Switch to Digital UNIX, depending on which operating system you are running.

Which operating system should be launched at the next power cycle?

Boot selection is currently NT.

Switch to NT
Switch to OpenVMS
Switch to Digital UNIX
Setup menu...

Use the arrow keys to select, then press Enter..


Supplementary menu and save changes

This selection is only available after configuration information has been changed.  When this command is chosen, the firmware will reboot.


Display hardware configuration

AlphaServer 300 Console Commands

Display Hardware Configuration

This choice displays a list of available hardware devices on your system.  The first screen displays processor information, the amount of memory installed, and the type of video card installed.  The second screen displays devices detected by the firmware.  Multi() devices include the monitor, keyboard port, and serial line ports.  SCSI() devices are SCSI disk, tape, or CD-ROM devices.  The third screen displays PCI devices, including a SCSI controller, ISA bridge chip (super I/O chip), Ethernet controller, memory (NVRAM board), and VGA controller.

Alpha Processor and System Information:

  Processor ID       21064
  Processor Revision 3
  System Revision    0x1
  Processor Speed    266 MHz
  Physical Memory    64 MB

Extended Firmware Information:

  Version: 4.49 960719.1755

NVRAM Environment Usage: 10%

      (329 of 3052 bytes)

Video Option detected:

BIOS controlled video card

 Press any key to continue...

                                      Monday, 11-11-1996  5:05:38 PM

Devices detected by the firmware:

   multi(0)video(0)monitor(0)
   multi(0)key(0)keyboard(0)
   multi(0)disk(0)fdisk(0)     (Removable)
   multi(0)serial(0)
   multi(0)serial(1)
   scsi(0)disk(1)rdisk(0)    (RAW)       DEC     RZ28B   (C) DEC0006
** scsi(0)tape(5)tape(0)                 DEC     TLZ06   (C) DEC4BQE
   scsi(0)cdrom(6)fdisk(0)   (Removable) DEC     RRD45   (C) DEC 1084

** --> Devices detected but not supported by the firmware.

 Press any key to continue...

                                        Monday, 11-11-1996  5:05:38 PM

PCI slot information:

Bus    Device Function  Vendor Device Revision  Interrupt  Device
Number Number  Number     ID     ID      ID      Vector     Type
------ ------ --------  ------ ------ --------  ---------  ----------
    0      6       0      1000      1      2         6      SCSI
    0      7       0      8086    484     84         0      ISA bridge
    0     11       0      1011      2     23         a      Ethernet
    0     12       0      1011      7      2         f      Memory
    0     13       0      1011      d     22         9      VGA

 Press any key to continue...


SRM Console

AlphaServer 300 Console Commands

SRM Console

SRM Console Conventions

SRM Console Special Characters

Console Commands

The SRM console firmware supports many commands.  Type Help at the >>> prompt for a list of all the commands.  The following console commands include those you are more likely to use (click on a command for more information):

Boot

Examine

Deposit

Set

Show

Isacfg

EWRK3_CONFIG


SRM Console Conventions

The following table lists SRM console conventions:

Item	Convention
Console prompt	>>>
Continuation line prompt	_>
Maximum command length	255 characters
Multiple contiguous spaces or tabs	Treated as a single space
Command abbreviations	Allowed, if not ambiguous
Command qualifiers or options	Prefix with a space and a dash " -"
Numbers	Hexadecimal, unless otherwise specified.  (Note that registers such as R0-R31 are shown in decimal notation.)


SRM Console Special Characters

The following table lists SRM console special characters:

Character/Key(s)	Function
Return	Terminates command line input.
Backspace	Deletes the character that was previously typed.
Ctrl A	Toggles insert/overstrike mode.   (Overstrike is the default.)
Ctrl B, or up arrow	Recalls previous commands.  (The last 16 commands are stored.)
Ctrl C	Terminates the foreground process.
Ctrl E	Moves the cursor to the end of the line.
Ctrl F or right arrow	Moves the cursor right one position.
Ctrl H	Moves the cursor to the beginning of the line.
Ctrl O	Stops console output.
Ctrl Q	XOFF, Resumes the flow of data to the console .
Ctrl S	XON, Stops the flow of data to the console.
Ctrl U or Ctrl D	Deletes the entire line.
Ctrl R	Retypes the current command line.


SRM Boot Command
AlphaServer 300 Console Commands
Boot Command

boot [-file filename] [-flags longword[,longword]] [-protocols enet_protocol] [-halt] [boot_device][-arc]

Description

The boot command performs the following functions:

  Initializes the processor

  Loads a program image from the specified boot device

  Transfers control to the loaded image

Where:

-file filename	Specifies the name of a file to load into the system.  For booting from Ethernet, this name is limited to 15 characters.  Use the set boot_file command to set an environment variable that specifies a default boot file.
-flags longword[,longword]	Specifies additional information for the operating system.  Use the set boot_osflags command to set an environment variable that specifies a default boot flag values.   OpenVMS boot flags.   Digital UNIX boot flags.
-protocols enet_protocol	Specifies an Ethernet protocol that will be used for a network boot.  Values may be mop or bootp.
-halt	Forces the bootstrap operation to halt and invoke the console program after the image is loaded and the page tables and other data structures are set up.
boot_device	Specifies a device path or list of devices that the firmware will attempt to boot.  Use the set bootdef_dev command to set an environment variable that specifies a default boot device.
-arc	Not used in the AlphaServer 300.


SRM Boot Command Examples
Boot Command Examples


Boot Command Examples

>>>boot	Boots the system from the default boot device.
>>>boot ewa0	Boots the system from Ethernet port ewa0.
>>>boot -file dec2.sys ewa0	Boots the file named dec2.sys from Ethernet port ewa0.
>>>boot -protocol bootp ewa0	Boots using TCP/IP BOOTP protocol from Ethernet post ewa0.  (Make sure the environment variables ewa0_protocols and ewa0_inet_init are both set to BOOTP before booting.)
>>>boot -flags 0,1	Boots the system from the default boot device using flag settings 0,1.
>>>boot -halt dka0	Loads the image from disk dka0, but remains in console mode.


SRM Examine Command
AlphaServer 300 Console Commands
Examine Command

examine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address

Description

The examine command displays the contents of an address you specify.  The address can be a memory location, register, device, or file.

Where:

-b	Byte of data.
-w	Word of data.
-l	Longword of data.
-q	Quadword of data.
-o	Octaword of data.
-h	Hexaword of data.
-d	Display data as a decoded macro instruction.
-physical	Reference physical address space.
-virtual	Reference virtual address space.
-gpr	Reference general purpose register address space.
-fpr	Reference floating point register address space.
-ipr	Reference internal processor register address space.
-n count	Specifies the number of consecutive locations to examine.
-s step	Specifies the address increment as a hexadecimal value.  This option allows you to override the increment that is normally derived from the data size.
[device:]	Selects the device to access.
address	Specifies the address of the first location to examine within the current device.


SRM Examine Examples
Examine Command Examples


Examine Command Examples

>>>e r0 gpr: 0(R0) 0000000000000002	Examine R0 by symbolic address
>>>e -g 0 gpr: 0(R0) 0000000000000002	Examine R0 by address space
>>>e gpr:0 gpr: 0(R0) 0000000000000002	Examine R0 by device name
>>>examine pc PC psr: 0(PC) 0000000000040A48	Examine the PC
>>>examine -n 5 r7 gpr:38 (R7) 000000000015CC00 gpr:40 (R8) 0000004E20006345 gpr:48 (R9) 0000000000000020 gpr:50(R10) 0000000000000000 gpr:58(R11) 0000000000000020 gpr:60(R12) 0000000000004200	Examine R7 and the next five registers.
>>>examine ipr:11 ipr: 11(KSP)0000000000400000	Examines IPR 11, the kernel stack pointer.


SRM Deposit Command
AlphaServer 300 Console Commands
Deposit Command

deposit [-{b,w,l,q,o,h}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address data

Description

The deposit command writes data to an address that you specify.  The address can be a memory location, register, device, or file.

Where:

-b	Byte of data.
-w	Word of data.
-l	Longword of data.
-q	Quadword of data.
-o	Octaword of data.
-h	Hexaword of data.
-physical	Reference physical address space.
-virtual	Reference virtual address space.
-gpr	Reference general purpose register address space.
-fpr	Reference floating point register address space.
-ipr	Reference internal processor register address space.
-n count	Specifies the number of consecutive locations to examine.
-s step	Specifies the address increment as a hexadecimal value.  This option allows you to override the increment that is normally derived from the data size.
[device:]	Selects the device to access.  The following devices are supported: pmem: Physical memory vmem: Virtual memory. All access and protection checking will occur.
address	An address that specifies the offset within a device into which data is deposited.  The address may also be any legal symbolic address.  Valid symbolic addresses are: gpr-name - symbol representing General Purpose Register ipr-name - symbol representing Internal Processor Register PC - Program Counter + - The location immediately following the last location referenced by an examine or deposit. - - The location immediately preceding the last location referenced by an examine or deposit. * - The location last referenced by an examine or deposit. @ - The location addressed by the last location referenced by an examine or deposit.
data	The data to be deposited.


SRM Deposit Command Examples
Deposit Command Examples


Deposit Command Examples

>>>d -n 1FF pmem:0 0	Clear the first 512 bytes of physical memory.
>>>d -l -n 3 vmem:1234 5	Deposit 5 into four longwords starting at virtual memory address 1234.
>>>d -n 8 R0 FFFFFFFF	Loads GPRs R0 through R8 with -1.
>>>d -l -n 10 -s 200 pmem:0 8	Deposit 8 in the first longword of the first 17 pages in physical memory.


SRM Set Command
AlphaServer 300 Console Commands
Set Command

set envar value [-default] [-integer] [-string]

Description

You use the set command to set or modify the value of an environment variable.  Use environment variables to pass configuration information between the console and the operating system.

Where:

envar	The environment variable to be assigned a new value.    Click here to see a list of SRM environment variables.
value	The value that is assigned to the environment variable.  It can be either a numeric value or an ASCII string.
-default	Restores an environment variable to its default value.
-integer	Creates an environment variable as an integer.
-string	Creates an environment variable as a string.


SRM Set Command Examples
Set Command Examples


Set Command Examples

>>>set bootdef_dev ewa0	The default boot device is set to ewa0.
>>>set auto_action boot	The console will attempt to boot following an error, halt, or power-up.
>>>set boot_osflags 0,1	The default boot flags are set to 0,1.
>>>set console serial	The display device is switched from a graphics monitor to a serial terminal.
>>>set os_type nt	After the next power cycle, the ARC console will be loaded
>>>set language 0	After initializing, the system will prompt you for the language.
>>>set ewa0_inet_init bootp >>>set ewa0_protocol bootp	Sets the system up for a network boot, such as from a Digital UNIX RIS server.


SRM Environment Variables
Environment Variables


AlphaServer 300
SRM Environment Variables

auto_action	Sets the console action following an error, halt, or power-up.  The action can be halt, boot, or restart.  Halt is the default.
bootdef_dev	Sets the default device or device list from which the system will attempt to boot.  If the system shipped with its software installed, the variable is preset to point to the device containing the software.  Otherwise, the default value is null.
boot_file	Sets the file name to be used when a bootstrap requires a filename.  The default setting is null.
boot_osflags	Sets additional parameters to be passed to system software.  The default setting is 0,0.   OpenVMS boot flags.   Digital UNIX boot flags.
console	When set to graphics, this variable routes the console output to the graphics controller.  When set to serial, it routes the console output to the serial line port.
control_disfd	When set to enable, this variable write protects the floppy diskette drive.  When set to disable, writes are enabled.
control_irq11	This variable controls the source of IRQ11.  When set to irq11, the interrupt is from an ISA IRQ11 device.  When set to scsi, the SCSI controller is the source.
control_irq12	This variable controls the source of IRQ12.  When set to irq12, the interrupt is from an ISA IRQ12 device.  When set to mouse, the mouse controller is the source.
control_scsi_term	Unused in the AlphaServer 300.
control_idema	When set to enable, IDE devices are allowed to make requests.  When set to disable, IDE device requests are blocked.
ewa0_inet_init	Used when booting over a TCP/IP network.  The value is normally BOOTP.
ewa0_mode	Possible values are twisted, AUI, or auto (currently auto is not supported).
ewa0_protocols	The possible values are BOOTP and MOP.
language	The language environment variable associates a language with the console.  Type set language 0, and the system will prompt you for the language setting.  The possible language values for each language are the following: 0 display menu 30 Dansk 32 Deutsch 34 Deutsch (Schweiz) 36 English (American) 38 English (British/Irish) 3A Espanol 3C Francais 3E Francais (Canadian) 40 Francais (Suisse Romande) 42 Italiano 44 Nederlands 46 Norsk 48 Portugues 4A Suomi 4C Svenska 4E Vlaams
os_type	Set to the operating system running on the system.  The possible values are NT, OpenVMS, and Digital UNIX or OSF.  Use this variable to determine which console firmware should be loaded: ARC or SRM.
pci_parity	The pci_parity variable controls PCI parity checking at the PCI bridge chip.  The new value becomes effective after an init or power cycle. The possible values are: On - parity checking is performed Off - parity checking is disabled Sniff - parity checking will be on for SCSI controllers (NCR53C810) at rev 2.  Otherwise, parity checking is off.
pka0_fast	A value of 0 sets the SCSI to "slow" mode (5MB/sec).  A value of 1 sets the SCSI to "fast" mode (10MB/sec).  For OpenVMS systems, changing the value of pka0_fast is the only action required to change modes.  For Digital UNIX systems, the system configuration files must be modified and the kernel rebuilt.
tga_sync_green	This variable is used to control the composite video signal for  3-wire (RGB) monitors that cannot detect the presence of composite video or v/h signals.  The possible values are: 1 - Composite video for.first PBXGA (ZLXp)  2 - Composite video for second PBXGA 3 - Composite video for first and second PBXGA


SRM Show Command
AlphaServer 300 Console Commands
Show Command

show [{config, device, hwrpb, memory, pal, version,...}] [envar]

Description

The show command displays the current value of a specified environment variable. The show command also displays information about the system, according to the arguments entered.

Where:

config	Displays the current system configuration.
device [device name]	Displays the devices and controllers in the system.  Specifying a device name returns information on that device only.
envar	Displays the value of the environment variable specified.   Click here to see a list of SRM environment variables.
error	Displays error log information.
hwrpb	Display the Alpha HWRPB.
map	Displays the system virtual memory map.
memory	Displays the memory module configuration.
pal	Displays the version of OpenVMS and Digital UNIX PALcode.
version	Displays the version of the console firmware.


SRM Show Command Examples
Show Command Examples


Show Command Examples

>>>show config	Firmware SRM Console:   V6.2 ARC Console:   V4.49 PALcode:       VMS PALcode X5.48-85,                 OSF PALcode X1.35-55 Serial ROM:    V4.4 Diag ROM:      V1.2 Processor DECchip (tm) 21064-2    266MHz 2MB Cache MEMORY   32 Meg of System Memory   Bank 0 = 32 Mbytes(8 MB Per Simm)            Starting at 0x0   Bank 1 = 32 Mbytes(8 MB Per Simm)            Starting at 0x2000000   Bank 2 = No Memory Detected PCI Bus   Bus 00 Slot 06: NCR 810 Scsi Controller               pka0.7.0.6.0   SCSI Bus ID 7               dka0.0.0.6.0   RZ26L               dka400.4.0.6.0 RRD43   Bus 00 Slot 07: Intel SIO 82378   Bus 00 Slot 10: Digital Network                   Controller        ewa0.0.0.10.0      08-00-2B-E2-1C-25   Bus 00 Slot 11: Digital ZLXp Graphics                   Controller ISA Slot Dev Name Type   Enable BaseAd  IRQ DMA 0       0 MOUSE  Embedded Yes  60     12       1  KBD   Embedded Yes  60      1       2  COM1  Embedded Yes  3f8     4       3  COM2  Embedded Yes  2f8     3       4  LPT1  Embedded Yes  3bc     7       5 FLOPPY Embedded Yes  3f0     6   2 2       0 PCXBJ Singleport Yes 530     9   0
>>>show device	dka0.0.0.6.0    DKA0   RZ25L          0006 dka400.4.0.6.0  DKA400 Toshiba CD-ROM 3213 dva0.0.0.0.1    DVA0 ewa0.0.0.0.1    EWA0   08-00-2B-33-40-8F pka0.7.0.6.0    PKA0   SCSI Bus ID 7
>>>show memory	64 Meg of System Memory Bank 0 = 32 Mbytes Starting at 0x2000000 Bank 1 = 32 Mbytes Starting at 0x0
>>>show version	X3.8-5 Dec 7 1996 15:22:35


OpenVMS Boot Flags

The OpenVMS boot flags consist of two portions separated by a comma: root , bootflag.  The value may be stored in the boot_osflags variable or typed in when booting.  The default value is 0,0.  The left half specifies the directory to boot from (0 = [SYS0], 1 = [SYS1] and so forth).  The right half can be used to enable specific functions during booting as shown below:

Value	Bit	Description
1	0	Conversational boot (SYSBOOT>).
2	1	Maps XDELTA to a running system.
4	2	Stops at the initial system breakpoint.
8	3	Performs a diagnostic bootstrap.
10	4	Stops at the bootstrap breakpoints.
20	5	Omits header from secondary boot image.
80	7	Prompts for the name of the secondary bootfile.
100	8	Halts the system before secondary bootstrap.
2000	13	Marks corrected read data error pages as bad.
10000	16	Displays extensive debug messages during booting.
20000	17	Displays selected user messages during booting.


Digital UNIX Boot Flags

The Digital UNIX boot flags can be stored in the boot_osflags variable or typed in along with the boot command.  The possible Digital UNIX boot flags are:

Flag	Description
a	Load operating system from the specified boot device. Boot to multiuser mode.
i	Prompt for the name of a file to load and other options (Boot interactively). Boot to single user mode.
s	Stop in single user mode. Boot /vmunix to single user mode and stop at the # (root) prompt.
D	Full dump, implies "s" as well


ISACFG Utility
AlphaServer 300 Console Commands
ISA Configuration Utility (ISACFG)

isacfg [-slot <slot#>] [-dev <device#>] [-all|-rm|-mk|-mod] [-<field> <value>] . . .

Description

ISA devices cannot be probed for configuration information by the Digital UNIX or OpenVMS operating systems.  Therefore, you must configure ISA options manually before installing a new ISA option module on a AlphaServer 300 system running either Digital UNIX or OpenVMS.

The ISACFG utility is a full command line utility.  It is useful for configuring more than one ISA module of each type, for example a second DE205 card or two non-Digital ISA options.

Where:

-all	Shows the entire configuration table.  Overrides all other commands.
-dev <dev#>	Optional, defaults to 0 if not entered.  On a multifunction or multiport adapter, this specifies the device on the adapter.
-dmachan{0-3} <#>	Allows you to specify up to four DMA channels for the device.
-dmamode{0-3} <#>	Allows you to specify the DMA type for -dmachan{0-3}. DMA modes are: 1 = Block 2 = Demand 4 = Single 8 = Cascade
-enadev	Allows you to specify whether an entry is enabled or disabled.  Disabled devices are not used in resource allocation calculations.  The possible values are: 0 - No (disabled) 1 - Yes (enabled)
-etyp <#>	Defines an entry type for this entry.  The <#> can be: 0 - Unused 1 - Single option 2 - Embedded multiport device 3 - Multiport option device
-handle {string}	Binds a name to the driver (up to 15 characters).
-init	Initializes the configuration table to the default settings.
-iobase{0-5} <#>	Specifies up to 6 I/O base registers for a particular device entry (in hexadecimal).
-irq{0-3} <#>	Allows you to assign up to four IRQ channels to the device (in decimal).
-membase{0-2} <#>	Specifies up to 3 R/W ISA memory regions (in hexadecimal).
-memlen{0-2} <#>	Specifies the length corresponding to membase{0-2} (in hexadecimal).
-mk	Adds an entry into the table.
-mod	Modifies an entry in the table.
-rm	Deletes an entry from the table.
-rombase <#>	Specify an address for ISA BIOS ext. ROM (in hexadecimal).
-romlen <#>	Specifies length of ROM (in hexadecimal).
-slot <slot#>	Allows you to enter a unique slot number for each ISA adapter.  You may assign the numbers in any order.  The slot number does not relate to a physical ISA adapter position in the motherboard.  Slot 0 is reserved for the local multiport adapter.
-totdev <#>	Placeholder for you to keep track of number of devices at this slot.  Modify this for your own use.


ISACFG Command Examples


ISACFG Command Examples

Add the DE205 Ethernet controller option by typing its script name:

>>>add_de205

or the full command:

>>>isacfg -slot 1 -dev 0 -mk -handle DE200-LE \
_> -irq0 5 -iobase0 300 -membase0 d0000 -etyp 1 -enadev 1

Display the full configuration database:

>>>isacfg -all

Modify the IRQ0 entry of an option:

>>>isacfg -mod -slot 1 -irq0 14

Remove an entry:

>>>isacfg -rm -slot 1 -dev 0


ICONFIG Utility
AlphaServer 300 Console Commands
ICONFIG

Description

ISA devices are not capable of being probed for configuration information by the Digital UNIX or OpenVMS operating systems.  Therefore, you must configure ISA option information manually before installing a new ISA option module on an AlphaServer 300 system running either Digital UNIX or OpenVMS.

The ICONFIG utility is a subset of the ISACFG utility.  To start the ICONFIG utility, type iconfig at the SRM console prompt.  The following display appears.  Note that the ISA options shown below are factory configured and cannot be deleted.

ISA CONFIGURATION UTILITY

Name             I/O IRQ DMA Mem      Length   Enabled

MOUSE            60  12                        Y
KBD              60  1                         Y
COM1             3f8 4                         Y
COM2             2f8 3                         Y
LPT1             3bc 7                         Y
FLOPPY           3f0 6   2                     Y

HELP: Enter up to 15 char device name

KEY HELP: Arrows/TAB to move, RET once to submit entry, RET 2nd time to exit

ICONFIG has built-in scripts for configuring the DE205 Ethernet module, PBXJA-AA sound module, and PB2GA-FB graphics module (MACH 64).  You can use a script to configure only one module of each type.  Click on the Examples button for instructions.

If you are configuring more than one of the same type of ISA option (for example, two non-Digital Ethernet options), you must enter the configuration information manually.  Click on the Examples button for instructions.


ICONFIG Command Examples

Using the Built-in ICONFIG Scripts

Enter the help scripts command to view the available scripts.  (Note that the PCXDF-AA fax/modem module is not supported on the AlphaServer 300.)

>>>help scripts

NAME

scripts

FUNCTION

These scripts are used to set up the system configuration.

SYNOPSIS

Available scripts:

add_de205	Adds DE205 module

add_fax	Adds FAX module

add_sound	Adds SOUND module

add_mach64	Adds ATI-MACH64 module

To add a module, type the script name.  You must also type init to submit the entry.  For example, add a PB2GA-FB (MACH64) graphics module  as follows:

>>> add_mach64

>>> init

After the system initializes, type iconfig to view the configured options.  The MACH64 module now appears in the display, and you can turn off the system and install the module.

Adding Options Manually

If you are configuring more than one of the same type of ISA option (for example, two non-Digital Ethernet options), you must enter the configuration information manually.

NOTE: Type information carefully.  If you make a typing error, you cannot correct it.  Type Ctrl/X to exit the utility.  Then type iconfig and begin again.  To delete an entry you created, position the cursor on the first column of the entry and press the Backspace key.

To add a second ISA option, invoke the ICONFIG utility.  Enter the device name, then tab to the next field and enter the I/O address, and so forth.  For example, to add a second DE205 Ethernet controller to the database, follow these steps:

1.   Enter up to 15 chars device name.	DE200-LE [TAB]
2.   Enter I/O address in hex.	300 [TAB]
3.   Enter IRQ channel in decimal.	5 [TAB]
4.   Enter dma channel in decimal.	[TAB]
5.   Enter memory address in hex.	d0000 [TAB]
6.   Enter length of memory in hex.	10000 [TAB]
7.   Enter N to disable, Y to enable.	Y [RETURN]
8.   Initialize the system.	>>>init
9.   View the new entry.	>>>iconfig
10.  Turn off the system and install the new module.

NOTE:  The available IRQ values for ISA options are 5, 9, 10, 14, and 15.  On Windows NT systems, IRQs 9, 10, 11, and 15 are preassigned to PCI options, if such options are installed.

If IRQ conflicts exist, a message is displayed.  For example, if you entered an IRQ value of 8 instead of 5, the following message is displayed:

ISACFG MESSAGE:  ERROR:  IRQ conflict with reserved IRQ values (0,2,8,11 or 13)

If you entered a DMA value of 2 rather than nothing, the following message is displayed:

ISACFG MESSAGE:  ERROR:  DMA conflict with slot 0 dev 5


EWRK3 Configuration Utility
AlphaServer 300 Console Commands
EWRK3 Configuration Utility (EWRK3_CONFIG)

ewrk3_config [-curaddr <I/O base address>] . . .

Description

The DEC EtherWORKS 3 Turbo Plus Ethernet controller (DE205) uses on board EEROM to store information such as the I/O base address, IRQ, memory base address, and so forth.  For more information on the DE205 option refer to the DEC EtherWORKS 3 Turbo User Information (EK-LEMAC-OM).

Invoking ewrk3_config with no parameters searches the entire address space for DE205 modules and displays the addresses of all modules found.

Where:

<none>	Find all DE205 boards and display their I/O base address
-curaddr	The current hex I/O base address of the module being changed
-ioaddr	The hex I/O base address to change the current module to
-irq	The decimal IRQ value (valid values are 5, 10 or 15)
-fbus	Fast bus enable
-ena16	16 bit bus enable
-memaddr	Base memory address the board should respond to
-bufsize	Buffer size of the memory address (2K, 32K or 64K)
-swflag	Software flag field
-netmgt	Net management field
-default	Set the board back to the default settings
-show	Displays the entire EEROM for the board


EWRK3_CONFIG Command Examples


EWRK3_CONFIG Command Examples

Locate the DE205 boards currently installed:

>>>ewrk3_config

found board addr=300

Change the address of the DE205 board at I/O base address 300h:

>>>ewrk3_config -curaddr 300 -ioaddr 320

Change the IRQ of the DE205 to 10:

>>>ewrk3_config -curaddr 300 -irq 10


Console Firmware Update Procedure

AlphaServer 300 Console Commands

Console Firmware Update Procedure

The AlphaServer 300 ARC and SRM console code resides in four flashROMs.

The Update utility (APU) contains three images: the utility itself, the SRM image, and the ARC image.  The Update utility can be run from either the ARC or SRM firmware.  The utility uses the existing console port (either the graphic port or the serial line port). The update is distributed on the Alpha Systems Firmware Update CD-ROM in conjunction with operating system updates.  Or, you can create an update floppy. The SRM console uses an update floppy with an Alpha boot block.  The ARC console uses a FAT formatted update floppy.  In addition, you can access the latest firmware updates from the Internet.

The following procedure shows the update occurring from the SRM console:

	Action	Response
1.	Make sure the Flash write enable jumper, J4 on the motherboard is inserted across pins 1 and 2.  This is the default position.  Also, jumper J1 should be in the default position (2 to 3).	None.
2.	Insert an update floppy (must have an Alpha boot block) or the Firmware Update CD-ROM.	None.
3.	Use the show device command to identify the device ID of the CD-drive. >>>show device	dka0.0.0.6.0   DKA0   RZ26L  440C dka400.4.0.6.0 DKA400 RRD43  0064 dva0.0.0.0.1   DVA0 ewa0.0.0.1.1   EWA0   08-00-2B-38-67-6B pka0.7.0.6.0   PKA0   SCSI Bus ID 7
4.	If floppy, type >>>boot dva0  or if CD-ROM, type >>>boot dka400	The following information displays: apu-version 959328854  ** Firmware Update Utility V5.7 ** ** System Type: AlphaServer 300 ** Update VERify List Show DUmp VERBose NVerbose DEbug NDebug ? Apu->
5.	Start the firmware update by typing: Apu-> update	APU-I *** ROM 0,1 Contents will be destroyed *** APU-I Are you ready to Program Device? (y/n)
6.	If you are ready, enter: y	APU-I Programming device APU-I Programming device completed APU-I Programming device APU-I Programming device completed Apu->
7.	Power cycle the system	The system restarts with the updated firmware.
NOTE:  The update command must be entered in full.  The other APU commands can be abbreviated.  The minimum characters required are shown in capital letters. Commands such as Dump, List, Show, and Verify must have verbose mode enabled for the output to be displayed.  Type the Verbose command at the Apu-> prompt to enter verbose mode.


Firmware Updates from the Internet

Using ftp, open a connection to ftp.digital.com, then go to:

/pub/Digital/Alpha/firmware/

Using a World Wide Web browser, enter the following URL:

http://ftp.digital.com/pub/Digital/Alpha/firmware/

The readme.html or readme.txt file explains how to download and use the firmware files.  New firmware released between shipments of the CD-ROM are available in an interim directory:

pub/Digital/Alpha/firmware/interim/


PCI Option Firmware Update Procedure

AlphaServer 300 Console Commands

PCI Option Firmware Update Procedure

Some PCI options have firmware on board that should be updated when the system firmware is updated.  Examples include the DFPAA FDDI controller (device name fwa0) and the KZPSA SCSI controller (device name pka0).  The options can be updated in either of two ways:

1.  Booting the PCI Loadable Firmware Update Utility from the Alpha Systems Firmware CD-ROM.  This procedure is described below.

2.  Booting the PCI Loadable Firmware Update Utility from the network.  (This procedure is described in the firmware release notes for this system, available on the Internet.)

	Action	Response
1.	Insert the Alpha Systems Firmware Update CD-ROM.	None.
2.	Use the show device command to identify the device ID of the CD-ROM drive. >>>show device	BOOTDEV  ADDR         DEVTYPE. . . ESA0        08-00-2B-12-00-9C DKA100    A/1/0           Disk DKA400    A/4/0           RODISK ..HostID..  A/7               INITR DKB400    B/4/0            RODISK ..HostID..  B/7               INITR
3.	Boot the CD. >>>boot -fl 0,A0 dka400 or >>>boot -fl 0,A0 dkb400 (Either device can be used.)	INIT-S CPU. . . AUDIT_CHECKSUM_GOOD AUDIT_LOAD_BEGINS AUDIT_LOAD_DONE BOOTFILE:
4.	Enter the name of the PCI update directory and filename. BOOTFILE: [ALPHA200]AS200_PCI_V1_2.EXE Note:  The file name may change with new firmware releases.  Refer to the documentation that comes with the Alpha Firmware Update CD-ROM. The boot file is loaded and the system displays the PCI Loadable Firmware Update Utility banner, utility commands, and then the UPD> prompt.	*** PCI Loadable Firmware Update Utility V1.2 *** ----------------------------------------------------------------- Function Description ------------------------------------------------------------------ Display Displays the system's configuration table Exit Done exit LFU (reset.) List Lists the device, revision, firmware name, and update revision Update Replace current firmware with loadable data  image Verify Compares loadable and hardware images. ? or Help  Scrolls this function table. -------------------------------------------------------------------- UPD>
5.	List the devices and revisions: UPD> list	Device Current Revision Filename     Update Revision pka0 A06 dfpaa_fw A07 fwa0 2.45 kzpsa_fw 2.46
6.	Update the PCI firmware: UPD> update	WARNING: updates may take several minutes to complete for each device. DO NOT ABORT! pka0 Updating to A06. . .Verifying A07. . .   Passed. fwa0 Updating to 2.45. . .Verifying 2.46. . .Passed. UPD>
7.	UPD> exit	>>>


Setting the Default Console

AlphaServer 300 Console Commands

Setting the Default Console

The default console can be switched from SRM (command line interface supporting Digital UNIX and OpenVMS) to ARC (menu interface supporting Windows NT) or back using one of the following two procedures:

From SRM to ARC:

	Action	Response
1.	At the SRM prompt, type:  >>>set os_type nt	>>>
2.	Power off the system.
3.	Power on the system.	ARC Boot menu appears.

From ARC to SRM:

	Action	Response
1.	Power on the system.	ARC Boot menu appears.
2.	Select the Supplementary menu.	The Supplementary menu appears.
3.	Select Setup the system... .	The Setup menu appears.
4.	Select Switch to OpenVMS or Digital UNIX.	Which operating system should be launched at the next power cycle? Boot selection is currently NT. Switch to NT Switch to OpenVMS Switch to Digital UNIX Setup menu... Use the arrow keys to select, then press Enter.
5.	Select the Setup menu.
6.	Power cycle the system.	>>>


Troubleshooting

Troubleshooting Menu


Troubleshooting Strategy


AlphaServer 300
Troubleshooting Strategy

A successful troubleshooting strategy requires a plan.  Gathering information is the first action to perform.  Use the site log to review the system's service history.  Ask the user or customer contact the following questions:

	What first alerted the user to the problem?
	Were there any recent changes or upgrades to the operating system, firmware, or application software?
	What symptoms did the user notice?
	Did the user make any initial troubleshooting efforts?  What were the results?
	Is the operating system functioning? If the answer is no, use power-on self-test (POST) and other loadable diagnostics. If the answer is yes, use it to gather information from log files such as the error log , operator log, and crash dump files.  Run operating system-based diagnostics, such as DEC VET for the Digital UNIX system or UETP for the OpenVMS system.


Troubleshooting Process
A Troubleshooting Strategy


AlphaServer 300
Power System Troubleshooting

Click on the arrows for information about power-related indicators.  A power troubleshooting checklist will be displayed if you click on the checklist button.


LEDs Lit?

Do the LEDs appear to be decrementing when the power is switched on?  If they are, the motherboard is likely getting the proper voltages.  If the LEDs do not light at all or appear dim, check the voltages. (The LEDs can be seen through viewing ports at the rear of the system unit.)


Indicator Panel

There are two indicators on the control panel.  The upper indicator should be ON when the system is switched on.  The lower indicator lights during disk activity.


Power  Button
Power Switch

The power switch must be pushed in to turn on the system.  If the switch is bad, replace the power supply (the switch is hardwired to the power supply).


AlphaServer 300
Power Troubleshooting Checklist

Symptom	Check

Control panel power indicator is OFF.	Front panel power switch pushed in.
	Power at wall receptacle.
	AC cord.
	Voltage selection switch.
Control panel power indicator is ON for a few seconds and then goes OFF.	There are two fans.  One is near the DECchip 21064 and the other is in the power supply. Caution: The 210W power supply shuts OFF if it senses that either fan has failed.  The 180W power supply does not sense fan failures.
Control panel power indicator is ON and display monitor is blank.	Monitor power indicator is ON. Raster present if brightness is turned up.
	Fuses and circuit breakers.
	Video controller cable properly connected.
	SROM error-code indicators.
	Power present at system board.  Click here for pinouts.


Power Supply Pinouts


Power Supply Pinouts

Power 	Pin	Wire 	Voltage
Supply 	Number	Color
Connector

P10 and P11 (Disk Drive)	1 2 3 4	Red Black Black Blue	+5V GND GND +12V
P14 and P12 (Disk Drive)	1 2 3 4	Blue Black Black Red	+12V GND GND +5V
P13 (Disk Drive)	1 2 3 4	Blue Black Black Red	+12V GND GND +5V
P8 (motherboard)	1 2 3 4 5 6	White Red Blue Yellow Black Black	POK_H +5V +12V -12V (key) GND GND
P9 (motherboard)	1 2 3 4 5 6	Black Black Gray Red Red Red	GND (key) GND -5V +5V +5V +5V
P3 (motherboard)	1 2 3 4 5 6	Black Black Black Orange Orange Orange	GND GND GND +3.3V +3.3V(key) +3.3V
P4 (motherboard) (not present on the 180W supply)	1 2 3 4 5 6	Orange Orange Orange Black Black Black	+3.3V +3.3V +3.3V GND GND GND(key)
Fan Connector Variable (8.5-15.2V) (not present on the 180W supply)	1 2	Red Black	+Fan Fan Rtn


Cooling Problems
Thermal Problems


AlphaServer 300
Thermal Problems

The AlphaServer 300 system operates in an ambient temperature range of 10 to 40C.  The system unit is cooled by two speed-controlled fans.  One fan is in the power supply, and one is in front of the CPU.

The 210W power supply varies the fan voltage based on the feedback from a temperature sensor located in the fan/speaker assembly.  The voltage may range from 7.0 to 13.0V.  The power supply contains a fan-fail detector that shuts down power after a one-second delay if either fan fails.  Fan failures are detected by monitoring fan ripple current.  In systems with the 180W power supply, the fan near the CPU control its own speed and is powered by +12 VDC.  The 180W supply will not detect a CPU fan failure.

Intermittent problems could result from overheating.  Check that the air flow path is clear.  Make sure there are not any materials blocking the input grill.  Also check to see that the cables inside the system are properly dressed and not impeding the airflow.


Initialization and POST Errors


AlphaServer 300
Initialization and POST Errors

The symptoms of an initialization or power-on self test (POST) problem are displayed in the diagnostic LEDs, or for some problems heard as a beep code.

When power is turned on, SROM code initializes the CPU, core logic, and memory.  After a successful initialization, the SROM code loads the POST code from the DROM.  The DROM POST code primarily performs data-path verification along with some functional testing.  Typically, POST reports errors that would prevent the main console from coming up.  The consoles (ARC and SRM) also display status codes in the LEDs.

If a test fails, the display does not change.  Therefore, when a failure occurs , the LED code is pointing to the test that last passed.


SROM Initialization Steps and LED Codes
SROM Initialization and LED Codes


AlphaServer 300
SROM Initialization and LED Codes  [image] =On,  [image] =Off

Initialization Steps                                              LED Codes

Initialize CPU (BIU_CTL and ABOX registers initialized).	(FF)
Initialize bank 8 logic. Executing memory sizing code.	(FE)
Memory sizing completed. Configuring memory.	(FD)
Memory configuration successful. Bcache initialization started. Initializing all memory to zeroes.	(FC)
Bcache initialization successful. Bcache references OFF and Dcache OFF. Initialize the low 8MB of memory to zero. Executing memory test 1 of 4.	(FB)
Memory test 1 of 4 complete. Executing memory test 2 of 4. Bcache references ON and Dcache OFF.	(FA)
Memory test 2 of 4 complete. Executing memory test 3 of 4. Bcache references OFF and Dcache ON.	(F9)
Memory test 3 of 4 complete. Executing memory test 4 of 4. Bcache references ON and Dcache ON.	(F8)
Memory test 4 of 4 complete.	(F7)
Initialize the core logic registers.	(F6)
Reserved for future.	(F5)   (F4)
Load the DROM code into memory.	(F3)   (F2)
Successful load and checksum of DROM	(F1)
Initialize registers required by console firmware and the PAL_BASE and EXEC_ADDR registers.	(F0)
Check J3: If "normal", then HW_REI to PAL.  If J3 is set to S-Port, go to the SROM mini-console.


DROM POST Steps and LED Codes


AlphaServer 300
DROM POST Steps and LED Codes  [image] =On,  [image] =Off

POST Sequence                                                 LED Codes

DROM code entered.	(DF)
PCI bridge core logic errors cleared.	(DE)
Memory test passed.	(DD)
FlashROM ID test passed.	(DC)
NVRAM test passed.	(DB)
SCSI controller (53C810) test passed.	(DA)
System I/O (82378) test passed.	(D9)
TOY (3287) test passed.	(D8)
Keyboard controller (8242) test passed.	(D7)
Super I/O (87332) test passed.	(D6)
Interrupts test passed.	(D5)
Floppy loader called.	(D4)
Jumping to floppy code.	(D3)
Flash loader called.	(D2)
Jumping to flash code.	(D1)
DROM console running.	(D0)
Floppy loader failed	(E2)
Flash loader failed	(E1)
Machine check occurred.	(20)


Console Initialization Steps and LED Codes
Console Initialization and LED Codes (ARC and SRM)


 AlphaServer 300
Console Initialization and LED Codes  [image] =On,  [image] =Off

Initialization Steps                                              LED Codes

Note:  The console codes reuse codes that were used by the SROM.
ARC Console Codes
ARC: environment loaded.	(FD)
ARC: console initialized (normal final state).	(FC)
ARC: serial port initialized.	(FA)
ARC: initialize keyboard controller.	(F9)
ARC: video okay.	(F7)
ARC: broken video or keyboard.	(F6)
ARC: fatal firmware error.	(F4)
SRM Console Codes
SRM: console starting.	(FF)
SRM: initialize idle PCB.	(FE)
SRM: initialize semaphores.	(FD)
SRM: initializing heap (dynamic memory).	(FC)   (FB)   (FA)
SRM: initializing driver structures.	(F9)
SRM: initializing idle process PID.	(F8)
SRM: initializing file system.	(F7)
SRM: initializing timer data structures.	(F6)
SRM: lower the IPL.	(F5)
SRM: enter the idle loop.	(F4)
SRM: memory configuration.	(EF)
SRM: initialize IRQ vector table and configure PCI bus.	(DF)
SRM: DDB startup parts 1, 2, and 3, and locate HWRPB	(EE)   (ED)   (EC)
SRM: test memory greater then 8 MB.	(EB)
SRM: DDB startup part 4.	(EA)
SRM: set keyboard type according to language variable.	(E9)
SRM: initialize environment variables.	(E8)
SRM: initialize SCSI.	(E7)
SRM: DDB startup part 5.	(E6)
SRM:show version and console idle (normal final state).	(E5)


Beep Codes


AlphaServer 300
Beep Codes

Beep Code     Meaning

1-1-4	The SROM code could not be read from the DROM or flashROM header, or there was a checksum failure.
1-2-4	The SROM code detected a hard failure (for example, a Bcache failure).
1-2-1	The DROM code detected a real-time clock (BQ3287) failure, or the real-time clock interrupt did not occur.
1-3-3	The SROM could not find 2 MB of good memory, or no memory is present.
3-2-4	The DROM code detected a keyboard/mouse controller failure.
3-2-1	The DROM code was unable to read the header of the flashROM or the flashROM checksum failed.  Therefore the DROM code attempted to boot from the floppy diskette.  The attempt failed due to either: 1. No floppy in the drive. 2. The Alpha boot block is missing from the floppy.
3-2-3	The DROM code was directed by the position of J5 to load the floppy, but there is no floppy in the drive.
3-3-1	The DROM code detected a hard failure during testing.  The LEDs display the failure code.


What Is a Beep Code?

Beep codes are heard from the system's speaker as three groups of beeps.  For example, if the SROM code could not find any good memory, you would hear a 1-3-3 beep code (one beep, a pause, a burst of three beeps, a pause, and another burst of three beeps).


SROM Mini-Console
SROM and DROM Mini-Consoles

The SROM and DROM mini-consoles are provided for use by manufacturing.  The SROM serial port adapter module (54-21827-01) is connected to J8 on the motherboard.  A terminal can then be connected to the port adapter.  Both consoles feature a set of basic commands.


DROM Load or Checksum Failure

If the code from the DROM fails to load properly or the SROM detects a DROM checksum error, the SROM will attempt to load the ARC or SRM firmware (whichever is specified in a non-volatile location).  If the ARC or SRM console firmware also failed to load properly, the SROM code jumps to the mini-console.


DROM Unable to Load Flash Code
Flash Code Fails to Load

If the SROM code is unable to load the DROM code and is also unable to load the flash code (ARC or SRM console firmware), or there is a checksum error after loading the flash code, the SROM will jump to its mini-console.

The DROM code has a built-in fail-safe mechanism that will attempt to load from a floppy if flashROM problems are detected.  The floppy should have an Alpha boot block and contain the Update utility.  If the boot block is not present, the DROM code will jump to its mini-console.


DROM Floppy Load Failed
Floppy Load Failure

If the flashROMs are corrupted, the DROM code will use its fail-safe mechanism and attempt to load a floppy.  The floppy should have an Alpha boot block and contain the Update utility.  If the floppy boot block is not present, the DROM code will jump to its mini-console.


Console Troubleshooting


AlphaServer 300
Console Troubleshooting

The AlphaServer 300 contains two console firmware systems.  The ARC console supports the Windows NT system and the SRM console supports the Digital UNIX and OpenVMS systems.  The SRM console in the flashROM does not contain diagnostics.  (Manufacturing has a superset of the SRM console that contains loadable diagnostics to support their environment.)

The flashROM (console firmware) is typically loaded by DROM's flash loader code.  If the flashROM is corrupted, or the checksum verification failed, the DROM flash loader will fail (LED code E1).  If a power failure occurs while the firmware update utility was being used to upgrade the flashROMs, it could corrupt the contents of the flashROMs.

When the system is powered on, the DROM code, sensing the flashROM corruption, will attempt to load from the floppy drive.  If the DROM code fails to load the floppy, it will start executing the DROM mini-console.

If the POST countdown display fails to appear on the graphics monitor, press the return key a few times.  If the >>> prompt appears, the console variable is set to serial.  Type the following:

>>> set console graphics

>>> init.

The countdown should now be displayed.  The console variable is stored in the NVRAM.  If the NVRAM gets zeroed out, the console variable will be set to serial.  (This happens when the battery goes dead or is replaced.)

If you are unable to get to the console prompt (>>>) because the system is set to autoboot, you can try the following:

1.  Type Ctrl C's during POST testing,

2.  Type Ctrl P before the windowing system is up, or

3.  Disconnect the disk.

Once you are at the prompt, type set auto_action halt to prevent autobooting.

If the monitor is unreadable because it is out of sync, the monitor may require the sync signal on the green signal.  This is the case with some older 3-wire monitors (RGB) that have a PXBGA (ZLXp-En) controller.  For a monitor with PBXGA controllers, set the tga_sync_green environment variable to 1 for the first PBXGA controller, 2 for the second, or 3 for both the first and second.  To set the variable, temporarily put on a five-wire monitor or hook a terminal to the COM1 port and use the serial console.  At the SRM prompt, type:

>>>set tga_sync_green value

where value is 1, 2, or 3 as described above.


Boot Troubleshooting


AlphaServer 300
Boot Troubleshooting

Possible Cause	Action

Will not boot from an IDE hard disk drive.	Configuration not supported.
Operating system software is not installed on the hard disk drive.	Install the appropriate operating system.
System cannot find the boot device.	Check the system configuration for correct device parameters. Digital UNIX and OpenVMS: Use the SRM show device command.  Use the displayed information to identify target devices for the boot command, and verify that the system sees all of the installed devices.  If you are attempting to use bootp, first set the following variables: >>>set ewa0_inet_init BOOTP >>>set ewa0_protocols BOOTP Windows NT: Use the ARC console to display the available boot devices.  First, from the Boot menu, select the Supplementary menu..., then select Display hardware configuration.  Verify that the target boot device is listed.
Environment variables incorrectly set. (This could happen if the battery or the entire motherboard was replaced, thereby losing the previous configuration information.)	Check and set the environment variables, if necessary. Digital UNIX and OpenVMS: Use the SRM console show and set commands to check and set the values assigned to boot-related variables such as auto_action, bootdef_dev, and boot_osflag. Windows NT: From the Boot menu, select Supplementary menu..., then select Set default environment variables.
Hard disk drive is not correctly formatted or the requested partition does not exist.	Format the hard disk drive or correctly partition the hard disk drive using appropriate tools (for example, ARCINST for Windows NT).
There is no software on the requested partition.	If the command is pointing to the correct partition, install the software.  Otherwise, change the variables to point to the correct partition.
Target boot device is not listed in the show device, show config (SRM), or the Display hardware configuration menu item (ARC) due to a SCSI bus problem.	Check the cables.  Are the cables oriented properly and not cocked? Are there bent pins? Check all the SCSI devices for incorrect or conflicting IDs.  Refer to the device's documentation. SCSI termination: The SCSI bus must be terminated at the last internal and the last external SCSI peripherals.  The last internal SCSI device must provide termination. If no external SCSI cable or devices are plugged into the rear SCSI connector, the external portion is automatically terminated.  If a SCSI cable is plugged in, the automatic termination is disabled and the last device on the bus must provide termination.


Troubleshooting Errors and Machine Checks
Machine Checks


AlphaServer 300
Machine Checks

When an error exception occurs, the CPU does the following:

1.	Drains the pipeline.
2.	Loads the program counter (PC) into the EXC_ADDR register.
3.	Dispatches to a PALcode exception routine located at PAL_BASE plus an offset.  The offset for machine checks is 0x0020.
4.	The PALcode then gathers information and builds a machine check stackframe.

  Click here to see one approach to analyzing a machine check.


Error Checking Map


Error Checking Map (Hot spotted)


DECchip 21064A Error Detection

Error detection in the DECchip 21064A is concentrated in the Bus Interface Unit (BIU).  The AlphaServer 300 CPU uses parity mode (one parity bit per longword).  Click on an error for more information.

Tag Address Parity Error

Tag Control Parity Error

System External Transaction Terminated with CACK_SERR

System Transaction Terminated with CACK_HERR

I-stream Parity Error (Parity mode only)

D-stream Parity Error (Parity mode only)

Icache Parity Error and Dcache Parity Error (21064A only)


Tag Address Parity Error

When the CPU performs a tag probe operation, the tag address [33:17] and its parity bit are checked for even parity.  If the parity is wrong, the tag probe is forced to miss, an external transaction is initiated, and if machine checks are enabled, the 21064A traps to PALcode.

BC_TAG: holds the result of the external cache probe

BIU_STAT: BC_TPERR bit is set

BIU_ADDR: holds the address.

The tag address [33:17] and its parity are never written by the CPU, they are written by the memory control logic during a Bcache miss transaction.  If you see this error, check the CPU module and cable dressing (cables blocking airflow might cause component overheating).

  Return to the CPU error detection window


Tag Control Parity Error

The Tag Control RAM is written by the memory control logic during cache refills and DMA writes that hit in the Bcache, and the CPU during CPU writes that hit in the Bcache.  Therefore, depending on the type of transaction, both the 21064A and the memory control logic are capable of computing the even parity.  When the CPU performs a tag probe operation, the tag control bits (Valid, Shared, and Dirty) and the associated parity bit are read and checked for even parity.  If the parity is wrong, the tag probe results in a miss, an external transaction is initiated, and if machine checks are enabled, the 21064A traps to PALcode.

BC_TAG: holds the result of the external cache probe

BIU_STAT: BC_TCPERR bit is set

BIU_ADDR: holds the address.

If you see this error, check the CPU module and cable dressing (cables blocking airflow might cause component overheating).

  Return to the CPU error detection window


System External Transaction Terminated with CACK_SERR
System External Transaction Terminated with CsACK_SERR

When the 21064A requests an external cycle, its external interface will keep the cycle until it is acknowledged by the external logic.  The CACK_SERR (soft error) indicates that a failure occurred during the cycle, but the failure was corrected.  The memory control logic in the AlphaServer 300 does not use the soft error acknowledge; therefore you should not see this error.

BIU_STAT: BIU_SERR bit is set, BIU_CMD holds CREQ (the cycle type)

BIU_ADDR: holds the address.

  Return to the CPU error detection window


System External Transaction Terminated with CACK_HERR

When the 21064A requests an external cycle, its external interface will keep the cycle until it is acknowledged by the external logic (memory control).  The CACK_HERR indicates that a catastrophic failure occurred during the cycle.  A machine check will be initiated if enabled.

BIU_STAT: BIU_HERR bit is set, BIU_CMD holds CREQ (the cycle type)

BIU_ADDR: holds the address.

On CPU initiated read transactions addressed to the PCI bridge or the PCI bus, this error indicates a PCI-related error occurred. (No error interrupt will be issued since the CPU received the error status directly.)  CPU write transactions to the PCI are always acknowledged as okay (write and run feature).  If there is a write problem, it will be reported later through an interrupt.

  Return to the CPU error detection window


I-stream Parity Error

The 128-bit data bus to and from the CPU is protected by four even parity bits (one for each longword).  When the 21064A receives external I-stream data with bad parity, the 21064A puts the data into the Icache unchanged and validates the block.  A machine check will be initiated if enabled.

BIU_STAT: FILL_DPERR bit is set, FILL_IRD bit is set

FILL_ADDR [33:5] and BIU_STAT [FILL_QW] give the bad quadword's address

FILL_SYNDROME identifies failing longword(s)

BIU_ADDR, BIU_STAT [6:0] are locked - contents are unpredictable

BC_TAG holds external cache tag probe results, if external cache was enabled

  Return to the CPU error detection window


D-stream Parity Error

The 128-bit data bus to and from the CPU is protected by four even parity bits (one for each longword).  When the 21064A receives external D-stream data with bad parity, the 21064A puts the data into the Dcache unchanged and validates the block.  A machine check will be initiated if enabled.

BIU_STAT: FILL_DPERR bit is set, FILL_IRD bit is clear

FILL_ADDR [33:5] and BIU_STAT [FILL_QW] give the bad quadword's address

FILL_ADDR [4:2] contain PA bits [4:2] of the location which the failing load
instruction attempted to read

FILL_SYNDROME identifies failing longword(s)

BIU_ADDR, BIU_STAT [6:0] are locked - contents are unpredictable

BC_TAG holds external cache tag probe results, if external cache was enabled

  Return to the CPU error detection window


Icache and Dcache Parity Errors (21064A only)
Icache and Dcache Parity Errors

The 21064A supports cache parity for data and tag on both the on-chip Icache and Dcache.  Icache and Dcache errors are non-recoverable.

An Icache parity error will cause C_STAT [IC_ERR] to be set and a machine check will be initiated if enabled.

A Dcache parity error will cause C_STAT [DC_ERR] to be set and a machine check will be initiated if enabled.

  Return to the CPU error detection window


Serial ROM (SROM)

The SROM and the SROM interface to the 21064A do not have error checking capability.


Memory Control Logic Error Detection

The memory control logic provides control for: filling the Bcache, extracting victims on CPU initiated transactions, probing the Bcache on DMAs, and invalidating the Bcache when a DMA write hit occurs.  The memory control logic is capable of detecting the following errors:

Bcache Tag Address Parity Error (bc_TAPErr)

Bcache Tag Control Parity Error (bc_TCPErr)

Nonexistent Memory Error (nxMErr)

When one of the above errors is detected, the memory control logic signals the CPU with Hard Error or the PCI bridge (for DMA operations, in which case the CPU is notified through an interrupt).  Error information is captured by:

Loading the current sysAdr<33:5> into the Error Address Register.

Setting the appropriate bits in the Error and Diagnostic Status Register (EDSR)

If another error occurs when the above registers are locked, the LostErr bit in the EDSR will be set and the error information of the lost error will not be captured.


Bcache Error Detection

The Bcache does not detect errors, but it does furnish information though parity bits to error detection networks in the CPU, memory control, and memory data path.  Parity bits include:

Longword even parity on the data (from memory).

Tag address even parity (written by the memory control logic)

Tag control even parity (written by memory control or CPU)

Keep your cache cool.  Dress the cables properly to let the air flow without blockage.


ROM Error Detection

The ROM section of the system uses checksums to protect the data.  Initially the SROM code, then the DROM code will verify ROM data through checksums.


Memory Data Path Error Detection

The CPU performs its own data checking for CPU initiated transactions.

The memory data path performs error detection for DMA initiated transactions.  When the Bcache or memory is read because of a DMA transaction (DMA read or DMA write masked), the data is checked for parity errors.  If there is a parity error, the data path notifies the PCI bridge.  If the PCI bridge was actually going to transfer the bad word onto the PCI, the CPU will be interrupted and the PCI transaction terminated.

If there is bad parity on data being written to memory during a DMA write, the data path will write the bad data to memory.  If the data is later used, an error will be detected and handled. (This is called write and run.)


Memory Error Detection

The memory SIMMs do not detect errors, but they do furnish information though parity bits to error detection networks in the CPU and memory data path.  The memory SIMMs store longword even parity on the data.  During CPU initiated transactions, parity is typically generated by the CPU (in the case of a write Bcache victim to memory, the parity is from the Bcache).  For DMA write transactions, parity is generated in the PCI world.

If there is bad parity on data being written to memory during a DMA write, the data path will write the bad data to memory.  If the data is later used, an error will be detected and handled. (You need not worry about the error unless the system is actually going to use the data.)


PCI Bridge Detected Errors

When the PCI bridge detects errors, the PCI Error Address register (PEAR) logs addresses sent or received on the PCI, and the sysBus Error Address register (SEAR) logs addresses sent or received on the sysBus.  Pick an error and click on it for information about the error and the actions taken as a result of the error.

CPU-Initiated Transaction Errors:

No device error	Target abort errors
Address parity errors	Read data parity errors
Write data parity errors	Retry timeout
DMA-Transaction Errors (DMA transaction errors are flagged by interrupting the CPU):

Address parity error	Read data parity error
Write data parity errors	Memory errors
Uncorrectable data error	Scatter/gather invalid errors
Write uncorrectable errors	Scatter/gather read uncorr. errors
Scatter/gather errors


No Device Error

On an I/O transaction initiated by the PCI bridge, if DEVSEL# is not asserted within five cycles, the PCI bridge assumes that no PCI device is going to respond to this transaction.  The following actions are taken:

  The nDev bit in the DCSR is set and the pciCmd field is set appropriately.

  PEAR contains the address sent out at the beginning of the transaction and is locked.

  On writes, intHw0 is asserted to interrupt the CPU.

  On reads, the PCI bridge sends 101=HARD_ERROR on the ioCMD<2:0> lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Target Abort Error

On an I/O transaction initiated by the PCI bridge, if the target device terminates the PCI transaction using target-abort protocol, then:

  DCSR tAbt bit is set and pciCmd set appropriately.

  PEAR is locked.

  On writes,  intHw0 is asserted to interrupt the CPU.

  On reads, the PCI bridge sends 101=HARD_ERROR on the ioCMD<2:0> lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Address Parity Error
Address Parity Errors

On I/O transactions, there is no way for the PCI bridge to determine that an address parity error occurred because the PCI bridge has no way to monitor the PCI Bus SERR signal.  (PERR is not used to convey address parity error information.)  Therefore the PCI bridge can take no action, however, the ISA bridge will assert SERR and send the CPU a non-maskable interrupt (NMI) if there is an address parity error.

  Return to the PCI bridge error detection window


Read Data Parity Error
Read Data Parity Errors

On I/O read transactions initiated by the PCI bridge chip, if the parity of the incoming data (PCI AD lines), the byte enables driven by the PCI bridge, and the parity bit (PAR) is not even, a read data parity error has occurred.  Actions taken are:

  Transaction continues normally.

  PCI bridge asserts PERR# on the PCI.

  iOPE bit set in the DCSR and ioCmd set appropriately.

  PEAR is locked. (If an error occurs on both longwords of a QW transactions, then lost is set.)

  HARD_ERROR returned to CPU.

  Return to the PCI bridge error detection window


Write Data Parity Error

On an I/O write transaction initiated by the PCI bridge, if PERR is asserted by the slave device for any longword of data, a write data parity error has occurred.  The following actions are taken:

  Transaction continues normally.

  iOPE bit set in the DCSR and ioCmd set appropriately.

  PEAR is locked. (If an error occurs on more than 1 longword of a single-write burst, then lost is set.)

  intHw0 is asserted to interrupt the CPU.

  Return to the PCI bridge error detection window


Retry Timeout

On an I/O transaction initiated by the PCI bridge, if the retry timeout overflows (this happens when the PCI bridge has been retried 2 to the 24th times by the target), then:

  The PCI bridge does not retry the transaction.

  ioRT bit in DCSR is set and pci_Cmd is set appropriately.

  PEAR is locked.

  intHw0 is asserted to interrupt the CPU.

  On reads, HARD_ERROR is sent to CPU on ioCmd lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Address Parity error (DMA)

On any DMA (PCI-initiated) transaction address phase, if the parity of the incoming address (PCI AD), command (C/BE),and parity (PAR) is not even, an address parity error occurred.

The PCI bridge will not respond to the transaction. ( This could be a bad command or address.) (PERR is not asserted because it is intended for data-parity errors on the PCI.)

  Return to the PCI bridge error detection window


Read Data Parity Error (DMA)

On a DMA read transaction (data phase), if there is a parity error it might be detected by the PCI master device.  Even if the device asserts PERR and the PCI bridge takes no action, it is the master's responsibility to handle the error.

  Return to the PCI bridge error detection window


Write Data Parity Error (DMA)
Write Date Parity Error (DMA)

On any DMA write transaction (data phase), if the parity of the incoming data (PCI AD), byte enables (C/BE), and the parity bit (PAR) is not even, a data parity error occurred.  The following actions occur:

  PCI bridge asserts PERR for one cycle on the PCI two cycles after the data was on the bus.

  dDPE bit in DCSR is set.

  PEAR is locked.

  intHw0 is asserted.

  The write will continue normally on the PCI.

  That particular cache line entry will not be written to memory.

  Return to the PCI bridge error detection window


Memory Error (DMA)

On a DMA transaction, if the memory controller logic detects an error (nxm, tag address parity, or tag control parity), it will log the address and specific error bit and terminate the sysBus transaction by signaling a DMA cycle error on ioAck<1:0>.

  mErr bit is set.

  SEAR is locked (contains the address that caused the memory error).

  intHw0 is asserted.

  On reads, the PCI bridge terminates the PCI transaction using the target-abort protocol.

  On writes, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Read Uncorrectable Data Error (DMA)

On a DMA read transaction, if there is a parity error in memory (or cache), the data path chips will inform the PCI bridge chip over the epiData bus.

If and when this longword is sent to the PCI bridge, along with the data on the epiData bus, epiBEnErr<0> will contain information whether this longword had an uncorrectable error or not. If the longword was going to be transferred on the PCI:

  intHw0 is asserted.

  uMRD bit in the DCSR is set.

  SEAR is locked

  If the bad data is requested by the PCI, the PCI bridge terminates the PCI transaction using the target-abort mechanism.

  Return to the PCI bridge error detection window


Scatter/Gather Entry Invalid Error

On scatter/gather mapped DMA transactions, the scatter/gather entry being accessed might be invalid.  The actual write to or read from memory will not occur.  The following actions are taken:

  iPTL bit set in DCSR

  PEAR is locked.

  intHw0 is asserted

  On reads, the transaction will terminate on the PCI with target-abort protocol.

  On writes, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Write Uncorrectable Data Error (DMA)
Write Uncorrectable Data Error

If a DMA write is not a full hexaword, the memory controller logic performs a read-modify-write.  If an error is detected on the read from memory before the write is done, the PCI bridge does not perform any action.  The data path core logic will proceed with the merge, but write incorrect parity back into memory.  When this location is read from later, an error will be detected.

  Return to the PCI bridge error detection window


Scatter/Gather Read Uncorrectable Error (DMA)
Scatter/Gather Read Uncorrectable Error

Just as in DMA read data transactions, if an uncorrectable data error (parity error) occurs when accessing a scatter/gather map entry in memory or Bcache, the PCI bridge is notified of the error when the longword is sent to it from the data path.  The following actions are taken:

  The uMRD bit is set in the DCSR

  The address is logged in the SEAR

  intHw0 is asserted.

  If the scatter/gather read was for a DMA read, the PCI bridge will terminate the PCI transaction with target-abort protocol.

  If the scatter/gather read was for a DMA write, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Scatter/Gather Memory Error (DMA)

On a DMA transaction, if the memory controller detects an error (nxm, tagape, or tagcpe) during a scatter/gather read transaction, it will terminate the sysBus transaction.  The memory controller will log the address and specific error bit, and terminate the sysBus by signaling a DMA cycle error on ioCAck<1:0>. Actions are:

  mErr bit in DCSR set.

  SEAR is locked.

  intHw0 asserted.

  If the scatter/gather read was for a DMA read, the PCI bridge terminates the PCI using target-abort.

  If the scatter/gather read was for a DMA write, the PCI bridge dismisses the write buffer entry (single cache line).  Notice that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


PCI Bus Error Detection

Not all PCI devices are required to detect and report parity errors, but all are required to generate parity on all of their transactions. Some do this more successfully then others.  See Disabling PCI Parity.

During the address phase, the PAR bit provides even parity for AD [31:0} and C/BE[3:0] regardless of whether or not all the lines carry meaningful information.

Master devices drive PAR for the address and data phases on write transactions. Target devices drive PAR during the data phase of read transactions.

The PCI contains PERR and SERR to signal errors.  PERR reports data parity errors for all transactions except special cycle commands.  PERR can only be driven by one device at a time.  Targets signal data parity errors back to the master using PERR.

SERR reports address parity errors and data parity errors on special cycles.  It is a wire-OR'd signal that can be driven by multiple devices at any one time.  SERR will be sent to the CPU as an NMI.


ISA Bus Error Detection

The ISA bus uses I/O Channel Check (IOCHK) to signal that some ISA device detected a parity error on the ISA bus.  The assertion of IOCHK will cause an NMI to be sent to the CPU.


SCSI Controller Error Detection

The SCSI controller is an NCR 53C810 chip.  On the PCI side, if the SCSI controller detects an address parity error, it asserts SERR which results in a non-maskable interrupt (NMI).

On the SCSI bus side, if the controller detects a parity error while receiving or sending SCSI data, and the appropriate interrupt enable bits in the controller are set, an interrupt will be asserted.


Ethernet LAN Controller Error Detection

The Ethernet LAN Controller (DECchip 21040) is mounted on the riser card.  When a data parity error on the PCI bus is detected, the controller asserts PERR.  When the controller detects a PCI address parity error, SERR is asserted.

Errors on the attachment unit interface (AUI) side are typically handled by interrupting the CPU (for example, a link fail occurred in the twisted pair lines).

The media adapter unit (MAU) contains two LEDs. One is asserted for at least 300 milliseconds when LinkPass is detected.  The other asserts for at least 300 milliseconds when any activity is detected on the network.


Analyze a Machine Check
Analyzing Machine Checks


AlphaServer 300
Analyzing Machine Checks

Here is an example of one approach to analyzing a machine check.

First, check the BIU_STAT register to see if there was a data parity error during a fill operation.  This is reflected in BIU_STAT <10>.  If bit 10 is set (1), the error occurred during a fill, so check the following:

BIU_STAT<14>=1	Parity error while FILL_DPERR already set.
BIU_STAT<11>=1	Error during Icache fill.
BIU_STAT<11>=0	Error during Dcache fill.
BIU_STAT<13:12>	Quadword that caused the error.
FILL_SYNDROME<00>=1	Indicates the low longword was corrupted.
FILL_SYNDROME<07>=1	Indicates the high longword was corrupted.
BC_TAG<0>=0	Bcache had a miss.

Since the Bcache had a miss, the error is caused by bad parity coming from the memory SIMMs.  The next question is, which SIMM is causing the trouble?  Click here to isolate the failing SIMM.

If BIU_STAT<10> is set to a zero (the error did not occur during a fill operation), check the following bits:

BIU_STAT<7>=1	A hard error occurred while a bit in BIU_STAT<3:0> was already set.
BIU_STAT<3>=1	Bcache tag control parity error.
BIU_STAT<2>=1	Bcache tag parity error.
BIU_STAT<1>=1	Soft error (correctable).
BIU_STAT<0>=1	Hard error (uncorrectable).
For the above errors, look at BIU_STAT<6:4> to determine the cycle type.


Failing SIMM Isolation


AlphaServer 300
Failing SIMM Isolation

If a parity error occurred during a primary cache fill operation, FILL_DPERR should be set (BIU_STAT<10>=1), and Bcache hit is clear (BC_TAG<0>=0).  To isolate the suspect SIMM, you must gather the following information:

1.	If FILL_IRD=1, then record FILL_ADDR<33:05>	Physical address of the 32-byte cache block that the CPU was attempting to read when the error occurred.
	If FILL_IRD=0, then record FILL_ADDR<33:02>.	Physical address generated by the load instruction that triggered the cache fill.
2.	Record BIU_STAT<13:12>.  This represents physical address <4:3>.	When FILL_DPERR is set, this field indicates the quadword within the hexaword fill block that caused the error.  Use with FILL_ADDR<33:05> to get the complete address of the failing quadword.
3.	Determine the system's memory configuration.  If the system is using the ARC console, first switch to the SRM console and then issue a SHOW MEMORY command at the SRM console prompt.  Bank 2 is unused on the AlphaServer 300.	The SHOW MEMORY command will display the memory configuration.  For example, >>>show memory 64 Meg of System Memory Bank 0 = 32 MB starting at 0x2000000 Bank 1 = 32 MB starting at 0x0 Bank 2 = No Memory Detected
4.	Compare the failing address with the memory configuration to identify the failing bank. Now that we know which bank is failing, the next step is to identify which SIMM in the bank is bad.	In the previous example, a failing address of 0x2B7BF8 would be located in bank 1, quadword 3.  Click here to see the AlphaServer 300 logical bank layout.
5.	Use the FILL_SYNDROME register to identify which SIMM in a bank is failing.
	FILL_SYNDROME<0>=1	The parity error is in the low longword of the failing quadword.
	FILL_SYNDROME<7>=1	The parity error is in the high longword of the failing quadword.
6.	Assuming that FILL_SYNDROME<7>=1, then the high longword SIMM is suspect.	You have now isolated the failing SIMM.  Reseat or replace the SIMM in connector J16.


Memory Bank Layout


Disabling PCI Parity Checking


AlphaServer 300
Disabling PCI Parity Checking

AlphaServer systems are engineered to protect the customer's data.  Parity protection is one method to help accomplish this.  In the PC market, parity protection is relatively rare.  Even with PCI options, parity is not consistently being implemented.  In fact, some PCI devices have a parity-generating scheme in which the parity is incorrect.  The device functions properly as long as parity is not checked.

To work around this problem, the ARC and SRM consoles have an option that allows you to turn off PCI parity checking at the PCI bridge portion of the core logic.

In the ARC console, the PCI parity-checking option is located in the Machine specific setup menu.  You can reach it by taking the following path:

1.	From the Boot Menu, select the Supplementary Menu.
2.	From the Supplementary Menu, select the Set up the system... menu
3.	From the Set up the system... menu, select the Machine specific menu.
4.	Choose the appropriate setting.

In the SRM console, you can control the PCI parity checking with the set pci_parity command. For example: >>>set pci_parity off.  See the list of environment variables for more details.


Non-Maskable Interrupts (NMI)

The non-maskable interrupt (NMI) originates on the ISA bridge chip (NCR 82378).  NMI will be asserted for the following conditions:

	SERR#: An address parity error has been detected on the PCI bus by the ISA bridge chip.  The ISA bridge chip takes no action other than reporting the error to the CPU.
	IOCHK#: A parity error has been detected on an expansion module plugged into the ISA bus.


Troubleshooting Tools


AlphaServer 300
Troubleshooting Tools

The DEC Verifier and Exerciser Tool (DEC VET) is an on-line tool for verifying system installations and acceptance.  It is also used to maintain and troubleshoot systems and perform load and stress tests on single devices, systems, and networks.  There are versions of DEC VET for each operating system.  For more information see the following guides:

DEC Verifier and Exerciser Tool User's Guide for Digital UNIX

DEC Verifier and Exerciser Tool User's Guide for OpenVMS

DEC Verifier and Exerciser Tool User's Guide for Windows NT

Each operating system has a specific mechanism for capturing and logging error information.  To access an operating system error log, click on one of the following buttons:

Windows NT

Digital UNIX

OpenVMS


Accessing the Windows NT Error Log

Windows NT maintains an event log file. The event logging service starts automatically when Windows NT is started. The Event Viewer is used to view and manage the event logs.

Start the Event Viewer by clicking on its icon. The icon is located in the Administrative Tools group in Program Manager. Windows NT uses three logs:

System log	Tracks events logged by Windows NT system components: for example, the failure of a driver to properly load.
Application log	Tracks events logged by applications.
Security log	Tracks changes to the security system and identifies possible security breaches.

Use the Log menu of the Event Viewer to select the log you need to view.

For more information, see the Event Viewer chapter in the Microsoft Windows NT System Guide or use online help.


Accessing the Digital UNIX Error Log

The event report formatter for Digital UNIX is uerf.  The syntax of the command is:

 /usr/sbin/uerf [ options ... ]

The uerf command uses the uerf.bin, uerf.hlp, and uerf.err data files.  The uerf.bin file is the event information database. The uerf.hlp file is the help file. The uerf.err file is the event message file.  The uerf command expects to find the data files in the /usr/sbin directory.

By default, the uerf command outputs the contents of the event log file specified by the *.* entry in the /etc/binlog.conf configuration file.  To report on any other event log file or if there is no *.* entry, you must use the uerf command with the -f option.

  Click here to see a few command examples.

Note: For further information, see the uerf Man pages. (Type "man uerf" at the Digital UNIX prompt.)


Digital UNIX Error Log Command Examples

Digital UNIX Error Log EXAMPLE Commands

The following example produces a report containing all event events, excluding logged operating-system events and operator and maintenance-class events:

uerf -O -x -c oper,maint

The following example produces an event report from the /usr/adm/binary.errlog.old file:

uerf -f /usr/adm/binary.errlog.old

The following examples produce event reports for the specified record codes:

uerf -r 100,102

uerf -r 100-109

The following example produces a report of all the events that occurred between 10:47 a.m. on December 13, 1996 and 5:30 p.m. on December 20, 1996:

uerf -t s:13-dec-1996,10:47:00 e:20-dec-1996,17:30:00

The following example produces an event report of the events that occurred on the current day and year, starting at 1:20 p.m. and ending at the current time:

uerf -t s:13:20

The following example produces a report of all logged events and displays it in reverse chronological order, starting with the current date and time:

uerf -R


Accessing the OpenVMS Error Log
Accessing the OpenVMS AXP Error Log

Access the OpenVMS Errorlog Report Formatter (ERF) with the ANALYZE/ERROR_LOG command.  The syntax is:

ANALYZE/ERROR_LOG [filespec[,...]]

For more information, see the VMS Error Log Utility Reference Manual.

EXAMPLES

The following example will use all the defaults:

$ ANALYZE/ERROR_LOG

The next example will limit the entry range generated from the file ERRLOG.SYS to entries from 1 to 18:

$ ANALYZE/ERROR_LOG/ENTRY=(START:1,END:18) ERRLOG.SYS

This example shows how to exclude a given class of event information (disk information, in this case):

$ ANALYZE/ERROR_LOG/EXCLUDE=(DISK)

The following example will furnish a report containing only disk-related information:

$ ANALYZE/ERROR_LOG/INCLUDE=(DISK)


FRU Replacement

FRU Replacement Menu

Removing the Top Cover

Memory SIMMs

Storage Options

ISA and PCI Options

Riser Card (and Ethernet controller)

Media Access Unit (MAU)

Battery

Motherboard

Power Supply

System Unit Fan

CAUTION: Remove the AC power cord and follow ESD procedures when working on the AlphaServer 300 System.


Removing the Top Cover

AlphaServer 300 FRU Replacement

Opening the Enclosure

To open the AlphaServer 300 enclosure, follow these steps:
1. Turn off the system.
2. Turn off any external peripheral devices.
3. Use the key to unlock the cover.
4. Slide the left side cover back and remove it.

HINT:  If the key is difficult to insert or turn, push the cover toward the front of the machine (during shipping the cover might have slipped back and jammed the lock).


Memory SIMM Replacement

AlphaServer 300 FRU Replacement

Memory SIMM Replacement

You may have to remove other SIMMs to gain access to the bad one.  To remove a SIMM:
1. Release the two clips (1)
2. Tilt the SIMM toward the power supply and lift the SIMM out of its socket.

To replace a SIMM:
1. Make sure the notch (3) is aligned with the protrusion in the bottom of the socket.
2. Insert the SIMM into its socket at an angle (4).
3. Tilt the SIMM upward (2) away from the power supply until both clips (1) engage the SIMM.
HINT:  Access to the SIMMs is sometimes improved by removing the drive bracket.

  Click here to see the memory configuration guidelines.


Storage Options Replacement

AlphaServer 300 FRU Replacement

Storage Options Replacement

Click on the bay area containing the device that you need to replace.


Inner Storage Bay

The inner storage bay may contain two 3.5-inch, half-height devices.  The lower position can be either accessible or non-accessible from the front, while the upper position is non-accessible from the front.  To replace an inner-bay option, follow these steps:

1.	Power off the system and disconnect the AC power cables.
2.	Remove the top cover.
3.	Loosen the mounting screws and remove the drive bracket assembly by sliding it to the rear and lifting.  Set the bracket on the power supply. HINT:  The height of some SIMMs may require that the SIMMs be removed before the drive bracket can be removed.
4.	Remove the cables from the faulty drive.
5.	Remove the failing drive's mounting screws from both sides of the bracket.
6.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
7.	Insert the replacement drive into the bracket and fasten it with the mounting screws.
8.	Connect the cables.
9.	Place the drive bracket back into the system unit while carefully guiding the cables. CAUTION: The cable clearances at the rear of the lower position are tight.
10.	Tighten the bracket mounting screws.
11.	Replace the top cover.
12.	Connect the AC power and turn on the system.


Inner Bay Drive Bracket Assembly


Removing Drives from the Bracket


Drive Bracket Cable Routing


Outer Storage Bay

The outer storage bay accommodates one 3.5-inch device (typically a floppy diskette drive), and one 5.25-inch device (such as a CD-ROM drive).  Due to thermal restrictions, the lower position does not support a hard disk.  Both the upper and lower positions are accessible from the front.  To replace drives in the outer bay, lower position, or the outer bay upper position, follow these steps:

1.	Turn off the system and disconnect the AC power cord.
2.	Unlock and remove the top cover.
3.	Remove the speaker to improve access.
4.	Remove the cables from the device you want to remove (either the upper [floppy] or the lower).
5.	Remove the faulty drive from the bay by removing the screws on the sides.
6.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
7.	Insert and mount the new drive into the outer bay.
8.	Connect the cables to the drive.  If you are replacing the floppy drive cable (1), make sure to insert the last connector of the cable (3) into the motherboard.  The last connector is the one with the shortest distance to the next connector (2).  Make sure the red stripe on the cable is facing the rear of the system.
9.	Replace the speaker.
10.	Replace the top cover.
11.	Connect the AC power and turn on the system.


Outer Bay Device Removal


Outer Bay Lower Device Removal


ISA and PCI Option Replacement

AlphaServer 300 FRU Replacement

ISA and PCI Option Replacement

To remove the ISA and PCI option boards, follow these steps:

1.	Disconnect any cables connected to the option board you are removing.
2.	Remove the screw at the rear end of the option card
3.	Gently pull out the option card.
4.	Configure the option by checking and setting switches and jumpers according to the option documentation.  If replacement option is ISA-based and set up differently than the original option on Digital UNIX or OpenVMS systems, use the ISA Configuration Utility, ISACFG, or ICONFIG to modify the SRM console configuration database.  For DEC EtherWORKS 3 Turbo Plus Ethernet controllers, use the EWRK3_CONFIG utility if you need to change the default settings on the replacement board.
5.	Plug the replacement card into the appropriate slot.  Make sure the card is fully seated.
6.	Fasten the card in with the mounting screw.
7.	Connect previously removed cables to the replacement card.


Expansion Board R and R


Riser Card (and Ethernet Controller) Replacement

AlphaServer 300 FRU Replacement

Riser Card (and Ethernet Controller) Replacement

The riser card contains PCI and ISA expansion slots, the ISA bridge logic, and the Ethernet LAN controller (DECchip 21040) along with the Ethernet ID ROM.

To replace the riser card, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover.
3.	Remove any cables from ISA and PCI options installed in the riser card.
4.	Remove the riser card mounting screws.
5.	Gently pull the riser card out of its slot in the motherboard.  Take care not to strain the MAU cable.
6.	Remove the MAU cable from J1 on the riser card.
7.	Using ESD precautions, remove the Ethernet ID ROM (EID) from the socket at E2.
8.	Plug the EID ROM into the replacement riser card at E2.
9.	Connect the MAU cable to J1 of the new riser card.
10.	Gently insert the new riser card into the motherboard, while making sure the MAU cable is not pinched.
11.	Fasten the riser card with the mounting screws.
12.	Re-insert and hook up the previously removed ISA and PCI options.
13.	Replace the top cover.
14.	Hook up the AC power cord and power on the system.


Riser Card


Media Access Unit (MAU) Replacement

AlphaServer 300 FRU Replacement

Media Access Unit (MAU) Replacement

The MAU takes the attachment unit interface (AUI) signals from the Ethernet LAN controller (DECchip 21040) and makes twisted pair and ThinWire network connections available on the rear panel.

To replace the MAU, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover.
3.	Remove the ThinWire or twisted pair cable from MAU connectors on the rear of the system.
4.	Remove the MAU mounting screw from the rear panel.
5.	Lift the MAU card out of the system and disconnect the ribbon cable.
6.	Connect the ribbon cable to the new MAU card.
7.	Position the MAU and fasten it with the mounting screw.
8.	Re-connect the network (ThinWire or twisted pair).
9.	Replace the top cover.
10.	Connect the AC cord and power on the system.


MAU


AlphaServer 300 FRU Replacement

Sound Card Replacement

To replace the AlphaServer 300 sound card, follow these steps:

1.	Power off the system and disconnect the power cord.
2.	Unplug any cables from the rear panel of the sound card.
3.	Remove the top cover.
4.	Remove the speaker cable ( at J5) and the CD-ROM drive audio cable (at J6).
5.	Remove the screw holding the sound card.
6.	Check that the jumpers on the new sound card are correctly configured.
7.	Install the new sound card into the motherboard.
8.	Replace the screw holding the sound card in place.
9.	Connect the speaker cable to J5 and the CD-ROM drive audio cable to J6 (if present).
10.	Replace the top cover.
11.	Connect the audio cables to the rear panel of the sound card.
12.	Connect the power cable and power on the system.


bmc soundcrd.bmp


Battery Replacement

AlphaServer 300 FRU Replacement

Battery Replacement

The battery supplies power to the real-time clock and the NVRAM.  Replace the battery with a Panasonic BR2032, CR2032, or equivalent.  After replacing the battery, you will have to re-enter the configuration and setup data using the ARC or SRM console.

Caution: Danger of explosion if battery is incorrectly replaced.  Replace only with the same or equivalent type recommended by the manufacturer.  Discard used batteries according to the manufacturer's instructions.

To replace the battery, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover.
3.	Gently pry the old battery from the battery holder.
4.	Insert the new battery, positive side up, into the holder.  Make sure the battery hold down contact does not get bent upward.  Poor electrical contact results if the contact is bent.
5.	Replace the top cover.
6.	Connect the AC cord and power the system on.
7.	Re-enter the configuration data.


Battery Holder


Motherboard Replacement

AlphaServer 300 FRU Replacement

Motherboard Replacement

NOTE: The motherboard contains the NVRAM and time-of-year (TOY) logic.  Both contain locations of battery supported RAM.  The RAM contains information used by the firmware (for example, the os_type variable, which determines whether the SRM or ARC console will be loaded).  When the motherboard is replaced, the information in the NVRAM and the TOY is lost.  Keep records of the configuration (IRQs, DMAs, I/O addresses, and so forth) to facilitate getting the system back into use.

To replace the motherboard, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cords at the rear of the system.
3.	At the unit's rear, disconnect the cables for the:   Keyboard   Mouse   Serial line units (2)   Printer   External SCSI bus   PCI or ISA options
4.	Remove the top cover.
5.	Remove any PCI and ISA options.
6.	Remove the MAU and riser board.
7.	Disconnect cables plugged into the main logic board (MLB).
8.	Remove the drive bracket assembly (set it on the power supply).
9.	Remove the motherboard-mounting screws (10).
10.	Gently slide the motherboard out the side of the enclosure.
11.	Before installing the new motherboard, check that the jumpers are configured properly.
12.	Reassemble by performing the steps in reverse order (10 to 1).


Motherboard


Speaker Replacement

Speaker Removal

You may want to remove the internal speaker for easier access to the drives in the outer storage bay.

1.	Turn off the system and remove the power cord.
2.	Remove the top cover.
3.	Loosen the speaker assembly mounting screw.
4.	Remove the speaker.  NOTE:  the speaker wire is connected to J20 on the motherboard.
5.	Access the drives in the outer storage bay as necessary.


bmc speaker.bmp


Power Supply Replacement

AlphaServer 300 FRU Replacement

Power Supply Replacement

The AlphaServer 300 may have either a 210W or a 180 W power supply.  The 180W supply does not have a thermal sensor or system fan power cable.

Note: If you are replacing a 210W supply with a 180W supply, you must also replace the system fan.

To replace the power supply, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cords at the rear of the system.
3.	Remove the top cover.
4.	Disconnect the power supply cables going to:   Motherboard (4) (3 for the 180W supply)   Outer storage-bay options (floppy and hard drive)   Inner storage-bay options
5.	Unfasten the thermal sensor (210W only) mounted in a clip on the front of the system fan holder.  The fan holder is held in by two clips at the top.
6.	Carefully free the thermal sensor cable (210W only).
7.	Disconnect and free the CPU fan power cable (210W only).
8.	Remove the mounting screw for the power switch.
9.	Pull the power switch out from the rear.  As you are removing the switch, the plastic power button on the front will pop off.
10.	Remove the power supply mounting screws.
11.	Carefully lift the power supply out of the enclosure while ensuring that the cables do not get hung up.
12.	Install the replacement power supply by repeating the above steps in reverse order.


Power Supply Location


System Fan Replacement

AlphaServer 300 FRU Replacement

System Unit Fan Replacement

The AlphaServer 300 may have either a 210W or a 180W power supply.  Systems with the 210W supply have a different fan than systems with a 180W supply.

Note: If you are replacing a 210W supply with a 180W supply, the system fan must also be replaced.  The fan for 180W systems has built-in speed control.

To replace the system unit fan, follow these steps:

1.	Turn off the power and remove the AC cord.
2.	Remove the top cover.
3.	Remove the fan/speaker housing by pressing in on the two snap clips at the top edge of the housing, while pulling the housing to the rear.  Exercise caution because the fan power cable and the thermal sensor (210W only) are still attached.
4.	Gently slide the thermal sensor (210W only) out of the clip on the front of the fan housing.
5.	Disconnect the fan power cable.
6.	Connect the replacement fan's power cable.  For systems with a 180W supply, the fan power cable plugs into J5 on the motherboard.
7.	Install the thermal sensor (210W only) into its original position.
8.	Mount the fan housing back into the enclosure by first inserting the fan housing into the two tabs at the bottom, and then snapping the housing in place.  Keep an eye on the cables while you are doing this.
9.	Replace the top cover.
10.	Connect the AC cord and power on the system.


System Unit Fan


Part Numbers

AlphaServer 300

Part Numbers

Field Replaceable Units (FRUs)

Ethernet Media Access Unit (MAU)	54-23252-01
Fan and holder assembly (for 210W power supply)	70-31222-01
Fan and holder assembly (for 180W power supply)	70-31222-02
Floppy diskette drive (3.5 in 1.44 MB)	RX23L-AA
Indicator and reset assembly (front panel)	70-31608-01
Memory (one 8 MB x 36 bit, 70ns SIMM)	ME534-DE
Memory (one 16 MB x 36 bit, 70ns SIMM)	ME644-BE
Memory (one 32 MB x 36 bit, 70ns SIMM)	ME654-DE
Motherboard	54-23787-02
Power supply   210 Watts   180 Watts (phase in after FRS)	30-40112-01 30-44170-01
Riser card	54-24119-01

AlphaServer 300 Cable Part Numbers

Ethernet - 20-conductor, flat ribbon cable from riser to MAU.	17-04071-01
Floppy - Motherboard to floppy drive, 34-conductor, slit flat ribbon with two FDD connectors	17-03937-01
Front panel - Motherboard to front panel, 6-conductor, twisted pair	70-31608-01
SCSI (internal) - Motherboard to internal SCSI drives, 50-conductor, slit flat ribbon daisy-chained with three drive connectors	17-03923-01
Speaker - 2-conductor, twisted pair terminated with 4 position headers.	70-31607-01


Connector Pinouts

AlphaServer 300

Connector Pinouts


Keyboard Port Pinouts


AlphaServer 300
Keyboard Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

Keyboard
1	KBData
2	N/C
3	Ground
4	+5 VDC
5	KBClock
6	N/C


Mouse Port Pinouts


AlphaServer 300
Mouse Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

Mouse
1	MSData
2	N/C
3	Ground
4	+5 VDC
5	MSClock
6	N/C


External SCSI
External SCSI Port Pinouts


AlphaServer 300
External SCSI Port Pinouts

50-pin high-density Honda-type receptacle

Pin	Signal		Pin	Signal/Meaning
1	Ground		26	DB(0) Data bus line 0
2	Ground		27	DB(1) Data bus line 1
3	Ground		28	DB(2) Data bus line 2
4	Ground		29	DB(3) Data bus line 3
5	Ground		30	DB(4) Data bus line 4
6	Ground		31	DB(5) Data bus line 5
7	Ground		32	DB(6) Data bus line 6
8	Ground		33	DB(7) Data bus line 7
9	Ground		34	DB(P) Data bus parity
10	Ground		35	Ground
11	Ground		36	Ground
12	Reserved		37	Reserved
13	Open		38	TERMPWR Terminator power
14	Reserved		39	Reserved
15	Ground		40	Ground
16	Ground		41	ATN Attention
17	Ground		42	Ground
18	Ground		43	BSY Busy
19	Ground		44	ACK Acknowledge
20	Ground		45	RST Reset
21	Ground		46	MSG Message
22	Ground		47	SEL Select
23	Ground		48	C/D Control/Data
24	Ground		49	REQ Request
25	Ground		50	I/O Input/Output


Communication Ports Pinouts


AlphaServer 300
Communication Ports Pinouts

9-Pin Sub D, plug, DB9 (Both serial line unit connectors have the same pinouts.)

Pin	Signal	Meaning
1 2 3 4 5 6 7 8 9	DCD RX TX DTR Ground DSR RTS CTS RI	Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal Ground Data Set Ready Request to Send Clear to Send Ring Indicator


Parallel Port Pinouts
Bi-Directional Parallel Port Pinout


AlphaServer 300
Bi-Directional Parallel Port Pinouts

25-position, Sub D, receptacle, DB25

Pin	Signal	Meaning
1		Strobe
2	PD0	Data bit 0
3	PD1	Data bit 1
4	PD2	Data bit 2
5	PD3	Data bit 3
6	PD4	Data bit 4
7	PD5	Data bit 5
8	PD6	Data bit 6
9	PD7	Data bit 7
10		Acknowledge
11	BUSY	Busy
12	PE	Paper End
13	SLCT	Select
14		Auto line feed
15		Error
16		Initialize printer
17		Select in
18-25	Ground	Ground


Jumpers

AlphaServer 300

Motherboard Jumpers

 (D) = Default

Pin 1 of each jumper is represented by the square pin.

Jumper           Setting                           Description

J1	1 to 2 2 to 3 (D)	Stay at SROM prompt Pass control to loaded flashROM image
J2	1 to 2 2 to 3 (D)	DROM loads an image from the floppy Normal
J3	1 to 2 (D) 2 to 3	Front panel generates: Reset Halt request CPU interrupt
J4	1 to 2 (D) 2 to 3	Enable flashROM writes Disables writes
J7	1 to 2 (D) 2 to 3	267 MHz CPU Not used
J21	Not installed	Currently not used.
J25	1 to 2 (D) Not installed	87332 super I/O chip 87312 super I/O chip
J26	1 to 2 (D) Not installed	87332 super I/O chip 87312 super I/O chip
J27	1 to 2 Not installed (D)	Disables sensing for presence of external cable, so an external SCSI terminator is required Senses the presence of an external SCSI cable, which then disables automatic SCSI termination.  If a cable is present, the SCSI bus must be terminated at the end of the external bus.
J32	1 to 2 (D) 2 to 3	267 MHz CPU Unused


 Sound Card Jumpers


AlphaServer 300

Sound Card Jumpers

(D) = Default

Jumper           Setting                           Description

J9	1 to 4 IN (D) 1 to 4 OUT	Motherboard beeps sent to speaker Motherboard beeps are ignored
J9	2 to 5   and   3 to 6   OUT             OUT   OUT              IN    IN                  OUT    IN                   IN (D)	Base Address: x604 xF40 xE80 x530


Watch this space!

You just know that a 250 Series motherboard is the foundation for the fastest CPUs in the world!  It's a safe bet that these buttons will contain their own graphics in the future.


LED and Beep Codes

AlphaServer 300

LED and Beep Codes

The AlphaServer 300 can signal problems to you before the video monitor is operational.  Two signaling methods are built into the system.  First is a LED display.  The LEDs are placed on the flashROM bus and visible from the rear of the system.

Beep codes are the second signaling method.  When certain problems are detected a beep code is sent to the speaker.  Since the speaker is driven from the ISA bridge chip, most of the system must be working to generate the beep codes.

  SROM Initialization Steps and LED Codes

  DROM POST Steps and LED Codes

  Console LED Codes (ARC and SRM)

  Beep Codes


Registers

AlphaServer 300

Registers


Machine Check Types


AlphaServer 300 Registers
Machine Check Types

PALcode Machine Check Errors

0x201	I/O read/write retry timeout
0x202	DMA data parity error
0x203	I/O data parity error
0x204	Slave abort PCI transaction
0x205	IDSEL not asserted
0x206	Correctable read error
0x207	Uncorrectable read error
0x208	Invalid page table lookup (scatter/gather)
0x209	Memory cycle error

Core Logic Machine Checks (0x220 PALcode entry)

0x20A	Bcache tag address parity error
0x20B	Bcache tag control parity error
0x20C	Nonexistent memory error

SIO Errors (IOCHECK in NMI Status Register) IRQ3

0x20D	SIO I/O check occurred PCI SERR asserted

CPU Errors

0x80	Tag parity error
0x82	Tag control error
0x84	Hardware error
0x86	Correctable ECC
0x88	Noncorrectable ECC
0x8A	Unknown error
0x8C	Cacksoft error
0x8E	Bugcheck
0x90	OS bugcheck
0x92	Dcache parity error
0x94	Icache parity error
0x96	C3 tag parity error


PAL Temp Registers

AlphaServer 300 Registers

PAL Temp Registers

Machine Check Frame Offset: + 0x018 through 0x108

There are 32 PAL temp registers of 64-bits each.  The registers are used by the PALcode.


Exception Mask Register

AlphaServer 300 Registers

Exception Mask Register

Machine Check Frame Offset: + 0x128


Instruction Cache CSR (ICCSR)

AlphaServer 300 Registers

Instruction Cache Control and Status Register

Address: IPR Ibox-Index=2, Machine Check Frame Offset: + 0x128

This register contains various CPU I-box hardware enable bits.

Click on the Description button to display the bit fields.


ICCSR Bit Descriptions
ICCSR Register Bit Descriptions

ASN <5:0>	<33:28>R <52:47>W	Address space number.
FPE	<23>R <42>W	If set, floating-point is enabled.
MAP	<22>R <41>W	If set, allows super-page I-stream memory mapping of VPC<33:13> directly to physical PC<33:13>.
HWE	<21>R <40>W	If set, allows the five PALRES instructions to be issued in kernel mode.
DI	<20>R <39>W	If set, dual issue is enabled.
BHE	<19>R <38>W	Used with BPE for branch-prediction selection. BPE BHE Prediction 0 X Not taken 1 0 Sign of displacement 1 1 Branch history table
JSE	<18>R <37>W	If set, allows pushing return addresses on the JSR stack.
BPE	<17>R <36>W	Used with BHE for branch prediction selection.  See BHE, bit <19>R for more details.
Pipe	<16>R <35>W	If set, pipeline operation is normal (The pipe will not drain for HW_MTPR, HW_REI, conditional branches, and instructions with R31 as the destination.)
PC MUX1 <2:0>	<15:13>R <34:32>W	Performance counter 1 input selection. Possible selections are: PC MUX1<2:0> Input 000 Dcache misses 001 Icache misses 010 Dual issues 011 Branch mispredicts 100 FP instructions 101 Integer operate 110 Store instructions 111 External events (PERF_CNT_H<1>)
PC MUX0 <3:0>	<12:09>R <11:08>W	Performance counter 0 input selection.  Possible selections are: PC MUX0<3:0> Input 000X Total issues divided by 2 001X Pipeline dry 010X Load instructions 011X Pipeline frozen 100X Branch instructions 1010 PAL mode 1011 Total cycles 110X Total nonissues divided by 2 111X External events (PERF_CNT_H<0>)
PC1	<02>R <00>W	If set, enables a performance counter 1 interrupt request after 256 events are counted.  If clear, the request occurs after 4096 events are counted.
PC0	<01>R <03>W	If set, enables a performance counter 0 interrupt request after 4096 events are counted.  If clear, the request occurs after 65536 events are counted.


Exception Address Register (EXC_ADD)

AlphaServer 300 Registers

Exception Address Register

Address: IPR Ibox, Index=4, Machine Check Frame Offset: + 0x110

The exception address register is used to restart the machine after exceptions or interrupts.

Click on the Description button to display the bit fields.


EXC_ADD Bit Descriptions
EXC_ADD Register Bit Descriptions

PC	<63:2>RW	Address of the instruction that has not completed execution.  This address will be used to return from the exception or interrupt.
PAL	<0>	This bit indicates PAL mode to the hardware.  When clear, the HW_REI instruction executes a jump to native (non-PAL) mode, enabling address translation.


Exception Summary Register (EXC_SUM)

AlphaServer 300 Registers

Exception Summary Register

Address: IPR Ibox, Index=10, Machine Check Frame Offset: + 0x118

This register contains various types of arithmetic traps that have occurred since the last time the register was written to (cleared).  Any write to the EXC_SUM register clears bits <08:02>.

Click on the Description button to display the bit fields.


EXC_SUM Bit Descriptions
EXC_SUM Register Bit Descriptions

MSK	<33>	Write mask IPR window.
IOV	<08>	If set, this bit indicates an F-box convert to integer overflow or integer arithmetic overflow.
INE	<07>	If set, this bit indicates a floating inexact error.
UNF	<06>	If set, this bit indicates a floating-point underflow.
FOV	<05>	If set, this bit indicates a floating-point overflow.
DZE	<04>	If set, this bit indicates a divide by zero.
INV	<03>	If set, this bit indicates an invalid operation.
SWC	<02>	If set, this bit indicates that software completion is possible.


Hardware Interrupt Enable Register (HIER)

AlphaServer 300 Registers

Hardware Interrupt Enable Register

Address: IPR Ibox, Index=16, Machine Check Frame Offset: + 0x138

The hardware interrupt enable register enables interrupts from the corresponding bits of the hardware interrupt request register (HIRR).

Click on the Description button to display the bit fields.


HIER Bit Descriptions
HIER Register Bit Descriptions

UAE	<32>R
SAE	<31>R
EAE	<30>R
KAE	<29>R
SIRR<15:01>	<28:14>R	Corresponds to software interrupt requests 15 to 1.
SLE	<13>R <32>W	When set, this bit enables interrupts from the serial line.
HIER<02:00>	<12:10>R <11:09>W
PC0	<09>R <08>W	When set, this bit enables interrupts from performance counter 0.
PC1	<08>R <15>W	When set, this bit enables interrupts from performance counter 1.
HIER<05:03>	<07:05>R <14:12>W
CRE	<04>R <02>W	When set, this bit enables interrupts due to correctable read errors.


Memory Management CSR (MM_CSR)

AlphaServer 300 Registers

Memory Management Control and Status Register

Address: IPR Abox, Index=4, Machine Check Frame Offset: + 0x148

The memory management control and status register is used latch and save information about data stream faults.

Click on the Description button to display the bit fields.


MM_CSR Bit Descriptions
MM_CSR Register Bit Descriptions

OPCODE	<14:09>R	This field contains the opcode of the faulting instruction.
RA	<08:04>R	The Ra field of the faulting instruction.
FOW	<03>R	This bit is set if the reference was a write and the PTE's FOW bit was set.
FOR	<02>R	This bit is set if the reference was a read and the PTE's FOR bit was set.
ACV	<01>R	This bit is set if the reference caused an access violation.
WR	<00>R	This bit is set if a write reference caused the error.


Hardware Interrupt Request Register (HIRR)

AlphaServer 300 Registers

Hardware Interrupt Request Register

Address: IPR Ibox, Index=12, Machine Check Frame Offset: + 0x140

The hardware interrupt request register is a read-only register that provides a record of all currently outstanding interrupt requests and summary bits at the time of a read.

Click on the Description button to display the bit fields.


HIRR Bit Descriptions
HIRR Register Bit Descriptions

USEK ASTRR	<32:29>R
SIRR<15:01>	<28:14>R	Corresponds to software interrupt requests 15 to 1.
SLR	<13>R	Serial line interrupt request.
HIRR<02:00>	<12:10>R	Corresponds to pins IRQ(H)<2:0>
PC0	<09>R	Performance counter 0 interrupt request.
PC1	<08>R	Performance counter 1 interrupt request.
HIRR<05:03>	<07:05>R	Corresponds to pins IRQ(H)<5:3>
CRR	<04>R	Correctable read error interrupt request.
ATR	<03>R	This bit is set if any AST request and corresponding enable is set.  This bit also requires that the processor mode is equal to or higher than the request mode, and that SIER<02> be set.
SWR	<02>R	Set if any software interrupt request and corresponding enable bit is set.
HWR	<01>R	Set if any hardware interrupt request and corresponding enable bit is set.


Data Cache Status Register (DC_STAT)

AlphaServer 300 Registers

Data Cache Status Register

Address: IPR Abox, Index=12, Machine Check Frame Offset: + 0x150

The data cache status register is a read-only register.  When an external parity error is recognized during a primary cache fill operation, the DC_STAT register is locked until the DC_ADDR register is read.

Click on the Description button to display the bit fields.


DC_STAT Bit Descriptions
DC_STAT Register Bit Descriptions

SEO	<14>R	Second error occurred.  Set when an error that normally locks the DC_STAT register occurs while the DC_STAT register is already locked.
STORE	<13>R	This bit indicates the error was caused by a store operation.
LOCK	<12>R	This bit is set to indicate that the error was caused by an LDLL, LDQL, STLC, or STQC instruction.
VAX_FP	<11>R	When INT is clear, this bit is set to indicate that a VAX floating-point format load or store caused the error.
LW	<10>R	When set, this bit indicates that the data length of the load or store was a longword.
INT	<09>R	When set, this bit indicates an integer load or store.
RA	<08:04>R	The RA field of the error-causing instruction.
DC_HIT	<03>R	Data cache hit.  The last load or store instruction processed by the A-box hit, if set, or missed if clear the data cache.


DC_ADDR Register

AlphaServer 300 Registers

DC_ADDR Register

Machine Check Frame Offset: + 0x158

The DC_ADDR register is a pseudo-register used for unlocking the DC_STAT register.  When the DC_ADDR register is read, the DC_STAT register is unlocked.


Bus Interface Unit Status Register (BIU_STAT)

AlphaServer 300 Registers

Bus Interface Unit Status Register

Address: IPR Abox, Index=10, Machine Check Frame Offset: + 0x168

The bus interface unit status register is a read-only register.  When the BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR bit is set, the BIU_STAT<6:0> register bits are locked until the BIU_ADDR register is read.

Click on the Description button to display the bit fields.


BIU_STAT Bit Descriptions
BIU_STAT Register Bit Descriptions

FILL_SEO	<14>R	Set when either a primary cache fill operation resulted in an uncorrectable EDC error or a parity error while the FILL_EDC bit was set, or the FILL_DPERR bit was already set.
FILL_QW	<13:12>R	When FILL_DPERR is set, this field identifies the quadword in the hexaword fill block that caused the error.
FILL_IRD	<11>R	If the I-cache was being filled when either the FILL_EDC or FILL_DPERR bit set, this bit is set.  It is clear when the error occurred during a D-cache fill operation.
FILL_DPERR	<10>R	Set if the primary cache fill data from outside the DECchip 21064 contained a parity error.
FILL_EDC	<08>R	Set if the primary cache fill data received from outside the DECchip 21064 contained an EDC error.
BIU_SEO	<07>R	Set when either an external cycle was terminated by the CACK(H) pins indicating HARD_ERROR, or an external cache tag probe encountered bad parity in the tag address RAM or tag control RAM while BIU_HERR, BIU_SERR, BIU_TPERR, or BIU_TCPERR was set.
BIU_CMD	<06:04>R	The cycle type on the cReq_h pins is latched in this field when a BIU_HERR, BIU_SERR, BIU_TPERR, or BIU_TCPERR error occurs.  Cycle types are: 0 0 0 IDLE 0 0 1 BARRIER 0 1 0 FETCH 0 1 1 FETCH_M 1 0 0 READ_BLOCK 1 0 1 WRITE_BLOCK 1 1 0 LDL_L/LDQ_L 1 1 1 STL_C/STQ_C
BIU_TCPERR	<03>R	Backup cache tag control parity error.
BIU_TPERR	<02>R	Backup cache tag parity error.
BIU_SERR	<01>R	Soft error.
BIU_HERR	<00>R	Hard error.


Bus Interface Unit Address Register (BIU_ADDR)

AlphaServer 300 Registers

Bus Interface Unit Address Register

Address: IPR Abox, Index=9, Machine Check Frame Offset: + 0x170

The bus interface unit address register is a read-only register.  It contains the physical address associated with errors reported by BIU_STAT<7:0>.  The BIU_ADDR register's contents are valid when BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR bit are set.  A read of the BIU_ADDR register will unlock both BIU_ADDR and BIU_STAT<7:0>.

If the BIU_CMD field of the BIU_STAT register indicates that the transaction that received the error was READ_BLOCK or load_locked, then BIU_ADDR<4:2> are unpredictable.  If the BIU_CMD contained any other command, then BIU_ADDR<4:2> will contain zeros.


Fill Syndrome Register

AlphaServer 300 Registers

Fill Syndrome Register

Address: IPR Abox, Index=19, Machine Check Frame Offset: + 0x180

The fill syndrome is a 14-bit read-only register.  If the DECchip 21064 is in ECC mode and an ECC error is recognized during a primary cache fill operation, the syndrome bits associated with the bad quadword are locked in this register.  The FILL_SYNDROME register is unlocked when the FILL_ADDR register is read.

Click on the Description button to display the bit fields.


FILL_SYNDROME Bit Descriptions
FILL_SYNDROME Register Bit Descriptions

HI	<13:07>R	Syndrome bits associated with the upper longword of the quadword.  If the DECchip 21064 is in parity mode, <07> indicates which longword in the quadword has bad parity (<13:08> are RAZ in parity mode).
LO	<06:00>R	Syndrome bits associated with the lower longword of the quadword.  If the DECchip 21064 is in parity mode, <00> indicates which longword in the quadword has bad parity (<06:01> are RAZ in parity mode).


Fill Address Register

AlphaServer 300 Registers

Fill Address Register

Address: IPR Abox, Index=13, Machine Check Frame Offset: + 0x188

The fill address register is a read-only register that contains the physical address associated with errors reported by BIU_STAT<14:08>.  Its contents are meaningful only when FILL_ECC or FILL_DPERR is set.  Reading the FILL_ADDR register unlocks FILL_ADDR, BIU_STATS<14:08>, and FILL_SYNDROME.

Click on the Description button to display the bit fields.


FILL_ADDR Bit Descriptions
FILL_ADDR Register Bit Descriptions

ADDRESS	<33:05>R	Address of the 32-byte cache block that the CPU was attempting to read when the error occurred.
ADDRESS	<04:02>	If the FILL_IRD bit in BIU_STAT is clear, indicating the error occurred during a D-stream cache fill, bits FILL_ADDR<04:02> contain physical address bits <04:02> of the load instruction that triggered the cache fill.  If the FILL_IRD bit is set, then FILL_ADDR<04:02> are unpredictable.


Virtual Address Register

AlphaServer 300 Registers

Virtual Address Register

Machine Check Frame Offset: + 0x190

The Virtual Address (VA) register latches the effective VA associated with D-stream faults or DTB misses.  The VA and the MM_CSR are locked against further updates until the software reads the VA register.


Backup Cache Tag Register (BC_TAG)

AlphaServer 300 Registers

Backup Cache Tag Register

Address: IPR Abox, Index=20, Machine Check Frame Offset: + 0x198

The backup cache tag register is a read-only register.  Unless locked, the BC_TAG register is loaded with the results of every backup cache tag probe.  When a tag or tag control parity error or primary fill data error (parity or ECC) occurs, this register is locked against further updates.  The software reads the LSB by using the HW_MFPR instruction.  Every read shifts the contents one position to the right, so a series of reads is needed.  The register is unlocked by using a HW_MTPR to the BC_TAG.

Click on the Description button to display the bit fields.


BC_TAG Bit Descriptions
BC_TAG Register Bit Descriptions

TAG_P	<22>R	Parity bit for the backup cache tag.  Even parity is used.
TAG<33:17>	<21:05>R	The backup cache tag field.
TAGCTL_V	<04>R	The tag valid bit.
TAGCTL_S	<03>R	The shared bit.  When clear, the entry is private.
TAGCTL_D	<02>R	The dirty bit.
TAGCTL_P	<01>R	Parity bit for the tag control bits.  Even parity is used.
HIT	<00>R	Hit.


Error and Diagnostic Status Register (EDSR)

AlphaServer 300 Registers

Error and Diagnostic Status Register

Address: 1 8000 0040, Machine Check Frame Offset: + 0x1A8

The error and diagnostic status register is a read-only register located in the core logic.  When an error occurs, an error bit will be set and the address will be locked in the Error Low and Error High Address Registers.  Any additional errors occurring after the address is locked will cause lostErr to be set.

Click on the Description button to display the bit fields.


EDSR Bit Descriptions
EDSR Register Bit Descriptions

wrPend	<15>R	When write pending is set, it indicates that valid write data is stored in the write buffer.
ldxlLock	<14>R	When LDx_L Locked is set, it indicates that the next STx_C may succeed.  Writing to any CSR or I/O space location clears this lock bit.
pass2	<13>R	Version of the DECchip 21071-CA.  Low indicates pass1, and high indicates pass2.
cReqCause	<08:06>R	This field indicates the cycle request that caused the error.  Depending on the DmaCause CSR, a copy of either the cpuCReq or the ioCmd lines will be placed in this field.  This field is valid only when bc_TAPErr, bc_TCPErr, or nxMErr error is indicated.
vicCause	<05>R	When the victim write caused error bit is set, it indicates that a NXM error was caused by a victim write transaction.  This is only valid when an error is indicated in bc_TAPErr, bc_TCPErr, or nxMErr.
dmaCause	<04>R	When set, this bit indicates that the bc_TAPErr, bc_TCPErr, or nxMErr was caused by a DMA transaction.
nxMErr	<03>RW	When set, the nonexistent memory error indicates that a read or write occurred to an invalid address that did not map to any memory bank, CSR, or I/O quadrant.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
bc_TCPErr	<02>RW	The Bcache tag control parity error bit indicates that a tag probe encountered bad parity in the tag control RAM.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
bc_TAPErr	<01>RW	The Bcache tag address parity error bit indicates that a tag probe encountered bad parity in the tag address RAM.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
lostErr	<00>RW	The multiple-errors bit indicates that an additional error occurred when the error address was already locked.  The bit is cleared by writing a one to it.


Diagnostic Control and Status Register (DCSR)

AlphaServer 300 Registers

Diagnostic Control and Status Register

Address: 1 A000 0000, Machine Check Frame Offset: + 0x208

The diagnostic control and status register provides control of operational and diagnostic modes.  It also reports status and error conditions relating to the PCI interface section of the core logic.

Click on the Description button to display the bit fields.


DCSR Bit Descriptions
DCSR Register Bit Descriptions

pass2	<31>R	Version of the DECchip 21071-DA.  Low indicates pass1 and high indicates pass2.
pCmd	<21:18>R	The pCmd field indicates the PCI cycle type when a PCI-initiated error is logged in the DCSR.  This field is only valid when an iPTL, nDev, tAbt, or iOPE error is set.
dByp	<17:16>RW	The disable read bypass field is used to control the ordering of PCI-initiated memory reads with respect to PCI-initiated memory writes.  The modes are: Value Mode 00 Full Bypass 01 Reserved 10 Partial Bypass 11 No Bypass
mErr	<15>RW	Memory error is set when the DECchip 21071-DA receives an error code in the ioCAck<1:0> field in response to a memory access.  The address, sysAdr<33:5>, of this transaction is locked in the SEAR <31:3>.  If another error occurs while the address register is locked, the lost bit will be set.
iPTL	<14>RW	The invalid page table lookup bit is set when the longword scatter/gather map entry being accessed is invalid.  The address, AD<31:0>, is locked in the PEAR.
uMRD	<13>RW	The unrecoverable memory read data bit is set when an uncorrectable error is encountered on data read from the DMA read buffer in the 21071-BA chip during a DMA read or a scatter/gather read transaction.
cMRD	<12>RW	The correctable memory read data bit is set when a correctable error is encountered on data read from the DMA read buffer in the 21071-BA chip during a DMA read or a scatter/gather read transaction.  Setting the dCEI bit will disable setting the cMRD bit.
nDev	<11>R	The no device bit is set when DEVSEL# is not asserted in response to an I/O read or write transaction initiated on the PCI by the 21071-DA chip.  The AD<31:0> for this transaction is logged in the PEAR.
tAbt	<10>RW	The target abort bit is set when a PCI slave device ends an I/O read or write transaction using the PCI target abort protocol.  AD<31:0> is put in the PEAR.
iOPE	<09>RW	The I/O parity error is set when a parity error occurs in the data phase of an I/O read or write transaction.  AD<31:0> is put in the PEAR.
dDPE	<08>RW	The DMA parity error is set when a parity error occurs in the data phase of a DMA transaction.  AD<31:0> is put in the PEAR.
lost	<06>RW	The lost bit is set when the address register corresponding to an error is already locked due to a previous error.
ioRT	<05>RW	The retry timeout error is set when a timeout occurs on CPU-initiated write or read transactions over the PCI.  AD<31:0> is put in the PEAR.
dPEC	<04>RW	When set, the dPEC bit disables PCI address and data parity error checking by the 21071-DA chip.  When clear, parity checking will be performed.
dCEI	<03>RW	When the disable correctable error interrupt bit is set, correctable errors on DMA read data are not logged in the cMRD bit and the address is not logged in the SEAR.
pEnb	<02>RW	When pre-fetch enable is set, the sysBus master machine will enable pre-fetching on DMA reads.
tEnb	<00>RW	When the translation buffer (TLB) enable bit is set, the entire TLB is enabled.  When tEnb is clear, the TLB is turned off and subsequent scatter/gather reads will not result in allocation of TLB entries.


PCI Error Address Register (PEAR)

AlphaServer 300 Registers

PCI Error Address Register

Address: 1 A000 0020, Machine Check Frame Offset: + 0x210

The PCI error address register is used to log the address of various errors relating to PCI bus transactions.

Click on the Description button to display the bit fields.


PEAR Bit Descriptions
PEAR Register Bit Descriptions

pci_Err	<31:00>R	The address sent out on the PCI bus (AD<31:0>) as the result of an I/O transaction is stored here.  This field logs the address of errors indicated by the nDev, tAbt, iOPE, dDPE, iPTL, and iORT bits in the DCSR. The register is valid only when one of these six error bits is set.  The type of error and the transaction determine how much of the pci_Err<31:0> field is valid. Condition Valid Field nDev and iPTL pci_Err<31:0> ioRT, tAbt, and iOPE during  dense memory writes pci_Err<31:5> ioRT, tAbt, and iOPE during  other transactions pci_Err<31:3> dDPE pci_Err<31:3>


sysBus Error Address Register (SEAR)

AlphaServer 300 Registers

sysBus Error Address Register

Address: 1 A000 0040, Machine Check Frame Offset: + 0x218

The sysBus error address register is used to log the address of various errors relating to sysBus transactions.

Click on the Description button to display the bit fields.


SEAR Bit Descriptions
SEAR Register Bit Descriptions

sys_Err <33:5>	<31:00>R	This field logs the address sent out on the sysBus.  Addresses are logged as the result of the mErr, uMRD, or cMRD bits in the DCSR being set.


PAL Base Address Register (PAL_BASE)

AlphaServer 300 Registers

PAL Base Address Register

Address: IPR Ibox, Index=11, Machine Check Frame Offset: + 0x130

The PAL base address register is a read/write register containing the base address for the PALcode.


Abox Control Register

AlphaServer 300 Registers

Abox Control Register

Address: IPR Abox, Index=14, Machine Check Frame Offset: + 0x160

The Abox control register is a write-only register!  It is included here so that you will know what it controls.

Click on the Description button to display the bit fields.


ABOX_CTL Bit Descriptions
ABOX_CTL Register Bit Descriptions

DC_FHIT	<11>W	When set, this bit forces all D-stream references to hit in the Dcache.  This bit takes precedence over DC_ENA.
DC_ENA	<10>W	When set, the DC_ENA bit enables the Dcache.  When cleared, the Dcache is disabled and flushed.
EMD_EN	<06>W	When set, the EMD_EN bit inverts physical address bit <2> for all D-stream references.  This provides limited support for big endian formats.
SPE_2	<05>W	When set, the SPE_2 bit enables one-to-one super-page mapping of D-stream virtual addresses(VA) with VA<33:13> directly to physical addresses PA<33:13>, if VA bits VA<42:41>=2.  VA bits <40:34> are ignored in this translation.  Access is allowed only in kernel mode.
SPE_1	<04>W	When set, the SPE_1 bit enables one-to-one super-page mapping of D-stream VA with VA<42:30>=1FFE to physical addresses with PA<33:30>=0.  Access is allowed only in kernel mode.
IC_SBUF_EN	<03>W	When set, the IC_SBUF_EN bit enables operation of a single-entry Icache stream buffer.
CRD_EN	<02>W	When set, the CRD_EN bit enables the Abox to generate an interrupt request whenever a pin bus transaction is terminated with a cAck_h code of SOFT_ERROR.
MCHK_EN	<01>W	When the MCHK_EN bit is set, the Abox generates a machine check when errors that are not correctable by the hardware are encountered.  When cleared, uncorrectable errors do not cause a machine check.  However, the BIU_STAT, DC_STAT, BIU_ADDR, and FILL_ADDR registers are updated and locked when errors occur.
WB_DIS	<00>W	When set, the WB_DIS bit prevents the write buffer from sending write data to the BIU.  It should be set only for diagnostics.


Bus Interface Unit Control Register (BIU_CTL)

AlphaServer 300 Registers

Bus Interface Unit Control Register

Address: IPR Abox, Index=18, Machine Check Frame Offset: + 0x178

The bus interface unit control register is a write-only register!  It is included here so that you will know what it controls.

Click on the Description button to display the bit fields.


BIU_CTL Bit Descriptions
BIU_CTL Register Bit Descriptions

BAD_DP	<36>W	When the BAD_DP bit is set, the 21064 will invert the value placed on bits <0>, <7>, <14>, and <21> of the check_h<27:0> field during off-chip writes.  This produces bad parity in parity mode and bad check bit codes when in ECC mode.
BC_PA_DIS	<35:32>W	You may use this 4-bit field to prevent the CPU chip from using the external cache to service reads and writes based on the quadrant of physical address space that they reference.  The table below shows the correspondence between this field and physical address space: BIU_CTL bits Physical Address 32 PA<33:32>=0 33 PA<33:32>=1 34 PA<33:32>=2 35 PA<33:32>=3
BAD_TCP	<31>W	When the BAD_TCP bit is set, bad parity is written into the tag control RAM whenever the CPU does a fast external RAM write.
BC_SIZE	<30:28>W	This field indicates the size of the external cache: BC_SIZE SIZE 000 128 KB 001 256 KB 010 512 KB 011 1 MB 100 2 MB 101 4 MB 110 8 MB
BC_WE_CTL <15:1>	<27:13>W	The external cache write-enable control is used to control the timing of the write-enable and chip-enable pins during writes into the data and tag control RAMs.
BC_WR_SPD	<11:08>W	The external cache write speed field indicates to the BIU the write cycle time of the external cache RAM chips.  The value is measured in CPU cycles.
BC_RD_SPD	<07:04>W	The external cache read speed field indicates to the BIU the read access time of the external cache RAM chips.  The value is measured in CPU cycles.
BC_FHIT	<03>W	When the external cache force hit bit is set and the BC_ENA bit is also set, all pin bus READ_BLOCK and WRITE_BLOCK transactions are forced to hit in the external cache.  Tag and tag control are ignored.
OE	<02>W	When this bit is set, the 21064 does not assert its chop-enable pins during RAM write cycles. This enables these pins to be connected to the output-enable pins of the cache RAMs.
ECC	<01>W	When the ECC bit is set, the 21064 generates and expects ECC on the check_h pins.  When the ECC bit is clear,  the 21064 generates and expects parity on four of the check_h pins.
BC_ENA	<00>W	When the external cache enable bit is cleared, the external cache is disabled.  Read/write references will then cause a request on the cReq_h immediately.


General Control Register

AlphaServer 300 Registers

General Control Register

Address: 1 8000 0000, Machine Check Frame Offset: + 0x1A0

The general control register contains status information that affects the major operational modes of the cache and memory control chip.

Click on the Description button to display the bit fields.


General Control Register Bit Descriptions

bc_BadAP	<13>RW	Bcache force bad address parity.  When set, the tag address parity will be loaded as bad.  This bit is independent of the FrcTag bit.
bc_FrcP	<12>RW	Bcache force parity.  When set, the parity bit will be set on the next cache fill.
bc_FrcV	<11>RW	Bcache force valid.  When set, the valid bit will be set on the next cache fill.
bc_FrcD	<10>RW	Bcache force dirty.  When set, the dirty bit will be set on the next cache fill.
bc_FrcTag	<09>RW	Bcache force tag.  When set, the Bcache will be probed for victims and the line will be invalidated using the values in bc_FrcD, bc_FrcV, and bc_FrcP.
bc_IgnTag	<08>RW	Bcache ignore tag.  When set, Bcache probes will act as if the valid bit was invalid.  All tag results will be ignored and any victims will be lost.
bc_LongWr	<07>RW	Bcache long writes.  When set, two sysBus cycles are required to write to the cache data RAMs.
bc_NoAlloc	<06>RW	Bcache no allocate mode.  When set, CPU writes to cacheable memory space will not be allocated to the cache.
bc_En	<05>RW	Bcache enable.  When clear, the Bcache is disabled and the cache state machine will not probe the cache.
wideMem	<04>RW	Memory size.  Reads the status of the wideMem input pin.  Returns 1 if the memory is 128-bits wide, or a 0 if 64-bits wide.
sysArb	<02:01>RW	DMA arbitration mode.  Determines arbitration scheme for sysBus transactions. Value Meaning 0X CPU priority 10 DMA priority 11 DMA strong priority


Tag Enable Register

AlphaServer 300 Registers

Tag Enable Register

Address: 1 8000 0060, Machine Check Frame Offset: + 0x1B0

The tag enable register is a read/write register that indicates which bits of the cache tag are to be compared with sysAdr<33:5>.  If a bit is 1, the corresponding bits in sysAdr<33:5> and tagAdr<31:17> are compared.  If a bit is 0, there is no comparison of those bits and the tagAdr bit is assumed to be tied low on the module.  Bits <15:1> in the register represent tagAdr<31:17>.


Error Low Address Register

AlphaServer 300 Registers

Error Low Address Register

Address: 1 8000 0080, Machine Check Frame Offset: + 0x1B8

The error low address register locks the low order bits of the sysBus address that caused the error that set the bc_TAPErr, bc_TCPErr. or nxMErr bit in the EDSR.  If a victim read caused the error, then the victim address is not latched; rather the address of the transaction is latched.  Bits <15:0> represent sysAdr<20:5>.  This register is read-only and only valid when an error is indicated.


Error High Address Register

AlphaServer 300 Registers

Error High Address Register

Address: 1 8000 00A0, Machine Check Frame Offset: + 0x1C0

The error high address register locks the high order bits of the sysBus address that caused the error that set the bc_TAPErr, bc_TCPErr. or nxMErr bit in the EDSR.  If a victim read caused the error, then the victim address is not latched; rather the address of the transaction is latched.  Bits <12:0> represent sysAdr<33:21>.  This register is read-only and only valid when an error is indicated.


LDx_L Low Address Register

AlphaServer 300 Registers

LDx_L Low Address Register

Address: 1 8000 00C0, Machine Check Frame Offset: + 0x1C8

The LDx_L low address register stores the low order bits of the last locked address.  Bits <15:0> represent sysAdr<20:5>.  This register is read-only.


LDx_L High Address Register

AlphaServer 300 Registers

LDx_L High Address Register

Address: 1 8000 00E0, Machine Check Frame Offset: + 0x1D0

The LDx_L low address register stores the low order bits of the last locked address.  Bits <12:0> represent sysAdr<33:21>.  This register is read-only.


Base Address Registers

AlphaServer 300 Registers

Base Address Registers

Bank 0 Address: 1 8000 0800, Machine Check Frame Offset: + 0x1D8

Bank 1 Address: 1 8000 0820, Machine Check Frame Offset: + 0x1E0

Bank 2 Address: 1 8000 0840, Machine Check Frame Offset: + 0x1E8

Each memory bankset has a corresponding base register.  The bits in this register are compared with the incoming sysAdr to determine the bankset being addressed.  The contents of this register are validated by setting the valid bit in the configuration register of that bankset.  The AlphaServer 300 uses bank registers 0 and 1 for main memory.


Configuration Registers

AlphaServer 300 Registers

Configuration Registers

Bank 0 Address: 1 8000 0A00, Machine Check Frame Offset: + 0x1F0

Bank 1 Address: 1 8000 0A20, Machine Check Frame Offset: + 0x1F8

Bank 2 Address: 1 8000 0A40, Machine Check Frame Offset: + 0x200

Each memory bankset has a corresponding configuration register.  This register contains mode bits and bits for memory address generation, as well as bankset decoding.  The AlphaServer 300 uses configuration registers 0 and 1 for main memory.


Configuration Registers Bit Descriptions
General Control Register Bit Descriptions

s0_ColSel<2:0>	<8:6>RW	Column address selection.  Indicates the number of valid column bits expected at the DRAMs.  Used along with memory width information to generate row or column addresses. s0_ColSel<2:0> Row,Column Bits 000 12, 12 001 12, 10 or 11, 11 010 Reserved 011 10, 10 1XX Reserved
s0_SubEna	<5>RW	Enable subbanks.  When set, subbanks are enabled and determined according to the table in the s0_Size description.
s0_Size<3:0>	<4:1>RW	Bankset size in MB.  Indicates the size of the bankset in order to determine which bits are used to compare the bankset base address with the physical address (PA) and to generate the subset.  Corresponds to the total size of the bankset, including subbanks, if present. s0_size<3:0> Compared Subset Set Size 0000 Reserved 0001 PA<33:29> PA<28> 512 MB 0010 PA<33:28> PA<27> 256 MB 0011 PA<33:27> PA<26> 128 MB 0100 PA<33:26> PA<25> 64 MB 0101 PA<33:25> PA<24> 32 MB 0110 PA<33:24> PA<23> 16 MB 0111 PA<33:23> PA<22> 8 MB 1XXX Reserved
s0_Valid	<0>RW	Bankset valid.  If set, all timing and configuration parameters for the bankset are valid, and access to the bankset is allowed.  If cleared, access to the bankset is not allowed.


Translated Base Registers 1 and 2

AlphaServer 300 Registers

Translated Base Registers 1 and 2

1. Address: 1 A000 00C0, Machine Check Frame Offset: + 0x220

2. Address: 1 A000 00E0, Machine Check Frame Offset: + 0x228

The t_Base field of the translated base registers (1 and 2) specifies the base CPU address for either the:

translated PCI address for the PCI target window (if scatter/gather is disabled), or

scatter/gather map table for the PCI target window (if scatter/gather is enabled).

This register is read/write.


PCI Base Registers 1 and 2

AlphaServer 300 Registers

PCI Base Registers 1 and 2

1. Address: 1 A000 0100, Machine Check Frame Offset: + 0x230

2. Address: 1 A000 0120, Machine Check Frame Offset: + 0x238

The two PCI base registers are used in the mapping of PCI addresses to physical memory addresses (one base register for each of the two allowed regions).


PCI Base Register Bit Descriptions

pci_Base <31:20>	<31:20>RW	The pci_Base field specifies the base address of the PCI target window.
wEnb	<19>RW	Window enable.  When the wEnb bit is cleared this PCI target window is disabled and will not respond to PCI-initiated transfers.  When set, this PCI target window is enabled and will respond to PCI-initiated transfers that hit in the address range of the target window.
sGEn	<18>RW	Scatter/gather enable.  When the sGEn bit is cleared, the PCI target window uses direct mapping to translate a PCI address to a CPU address.  When set, the PCI target window uses scatter/gather mapping to translate a PCI address to a CPU address.
Reserved	<17:0>MBZ


PCI Mask Registers 1 and 2

AlphaServer 300 Registers

PCI Mask Registers 1 and 2

1. Address: 1 A000 0140, Machine Check Frame Offset: + 0x240

2. Address: 1 A000 0160, Machine Check Frame Offset: + 0x248

The PCI mask registers are used with the PCI base registers to allow two regions in PCI memory space to be mapped to system memory.  The pciMask <31:20> field specifies the size of the PCI target window.  It is also used in the translation of the PCI address to the CPU address.

This register is read/write.


Host Address Extension Register 0

AlphaServer 300 Registers

Host Address Extension Register 0

Address: 1 A000 0180, Machine Check Frame Offset: none

The HAXR0 register is hardcoded to 0.  A read from this register returns a 0; a write does nothing.


Host Address Extension Register 1

AlphaServer 300 Registers

Host Address Extension Register 1

Address: 1 A000 01A0, Machine Check Frame Offset: + 0x250

The host address extension register 1 (HARX1) is used to generate AD<31:27> on CPU-initiated transactions that address PCI memory space.

The eAddr<4:0> field is used as the upper five PCI address bits (AD<31:27>).  The field is read/write.


Host Address Extension Register 2

AlphaServer 300 Registers

Host Address Extension Register 2

Address: 1 A000 01C0, Machine Check Frame Offset: + 0x258

The host address extension register 2 (HARX2) is used to generate AD<31:24> on CPU-initiated transactions that address PCI I/O space.  It is also used to generate AD<1:0> during PCI configuration reads and writes.

The eAddr<7:0> field is used as the upper five PCI address bits (AD<31:27>).  The field is read/write.

The conf_Addr<1:0> field is used as the lower PCI address bits (AD<1:0>) during CPU-initiated transactions to PCI configuration space.


PCI Master Latency Timer Register

AlphaServer 300 Registers

PCI Master Latency Timer Register

Address: 1 A000 01E0, Machine Check Frame Offset: + 0x260

The pMLC<7:0> field of the PCI master latency register (PMLT) is loaded into the master latency timer register at the start of a PCI master transaction initiated by the PCI bus bridge chip.


TLB Tag Registers 0-7

AlphaServer 300 Registers

TLB Tag Registers 0-7

0. Address: 1 A000 0200, Machine Check Frame Offset: + 0x268

1. Address: 1 A000 0220, Machine Check Frame Offset: + 0x270

2. Address: 1 A000 0240, Machine Check Frame Offset: + 0x278

3. Address: 1 A000 0260, Machine Check Frame Offset: + 0x280

4. Address: 1 A000 0280, Machine Check Frame Offset: + 0x288

5. Address: 1 A000 02A0, Machine Check Frame Offset: + 0x290

6. Address: 1 A000 02C0, Machine Check Frame Offset: + 0x298

7. Address: 1 A000 02E0, Machine Check Frame Offset: + 0x2A0

These registers are read only.  The pci_Page<31:13> field specifies the PCI page address (TAG) corresponding to the translated CPU page address in the associated TLB data register.

The entry valid (eVal) bit can be read through bit <12>.  Normally, the invalid bit contains the value read during a page table entry read.


TLB Data Registers 0-7

AlphaServer 300 Registers

TLB Data Registers 0-7

0. Address: 1 A000 0300, Machine Check Frame Offset: + 0x2A8

1. Address: 1 A000 0320, Machine Check Frame Offset: + 0x2B0

2. Address: 1 A000 0340, Machine Check Frame Offset: + 0x2B8

3. Address: 1 A000 0360, Machine Check Frame Offset: + 0x2C0

4. Address: 1 A000 0380, Machine Check Frame Offset: + 0x2C8

5. Address: 1 A000 03A0, Machine Check Frame Offset: + 0x2D0

6. Address: 1 A000 03C0, Machine Check Frame Offset: + 0x2D8

7. Address: 1 A000 03E0, Machine Check Frame Offset: + 0x2E0

These registers are read only.  The cpu_Page<32:13> field allows bits <32:13> of the CPU address to be read.


Translation Buffer Invalidate All

AlphaServer 300 Registers

Translation Buffer Invalidate All

Address: 1 A000 0400, Machine Check Frame Offset: none

The TBIA register is a write-only register.  A write to this register causes all the valid entries in the scatter/gather map TLB to be invalidated.