Copyright: Copyright © 1996 Digital Equipment Corp


title


Credits
Digital AlphaStation 255 Service Guide Team

We welcome your comments.

Please let us know:

  Who you are?

  How do you use the AlphaStation 255 Service Guide?

  Is there additional information that can be added to the guide
     to help you do your job?

  How can we improve the guide?

Send your comments to:

Terry Donald (donald@eng.pko.dec.com)

Carmen Wheatcroft (wheatcroft@eng.pko.dec.com)


Press an Action Button

There is nothing of interest here. Click on START to go to the Main menu, or click on EXIT to exit this file.


AlphaStation 255 Service Guide Table of Contents


AlphaStation 255 Series Service Guide Draft Notices
Digital AlphaStation 255 Service Guide - Draft Notes

This draft version of the Service Guide is based on the following:

Please send your comments to donald@eng.pko.dec.com or WREATH::DONALD.


Copyright and Trademarks

The information used in this document is subject to change without notice and should not be construed as a commitment from Digital Equipment Corporation.  Digital Equipment Corporation assumes no responsibility for any errors that appear in this document.

Possession, use, duplication, or dissemination of the software described in this documentation is authorized only pursuant to a valid written license from Digital or the third-party owner of the software copyright.

Copyright © Digital Equipment Corporation 1996.  All rights reserved.

The following are trademarks of Digital Equipment Corporation: AlphaGeneration, AlphaStation, DECchip, DEC, DECstation, DECsystem, DECWORLD, OpenVMS, VAX, VAXstation, Digital, and the DIGITAL logo.

UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd.

Windows NT is a registered trademark of Microsoft Corporation.


AlphaGeneration
Welcome to the fast world of AlphaGeneration systems.  Performance has arrived on your desktop.  Fasten your seatbelt and hang on for the ride of your life!


Copying and Printing Popup Displays

Normally information contained in popup displays can not be copied or printed.  The Digital AlphaStation 255 Service Guide makes provisions to allow you to copy and print popups.

Copyable and printable popups have a hotspotted title line.  Simply click on the title and the popup will become a main window topic.  You may now copy or print the text using the File and Edit menus on the menu bar.  When done, click on the Back button to return to the parent topic of the popup.


Who is the Audience?
Audience

The primary audience of the AlphaStation 255 Service Guide is Digital's Multivendor Customer Services organization.  Secondary audiences include customers who maintain their own systems, and value added resellers (VARs).


Disoriented?
Getting Disoriented?

Do you find yourself losing track of where you are in the service information?  A couple of buttons will help keep you on track.  The "BACK" button will take you backwards a topic at a time along the path you have already traveled.  For example, if you click on the topic title of a popup, the popup becomes the main topic to facilitate printing and copying the information.  To return to the previous topic, click on the BACK button.

The other button that will help cure disorientation is the "CONTENTS" button.  Just click on this button and you will be brought back to the main menu screen.


For More Information

	Digital AlphaStation 255 User Information	EK-VLLXA-UI
	Digital AlphaStation 255 Family Technical Information	EK-VLLXA-TI
	DECchip 21064-AA Microprocessor Hardware Reference Manual	EC-N0079-72
	PCI Local Bus Specification, Revision 2.0	PCI Special Interest Group, order number 281446-001
	AlphaStation 255 Service Guide (This document)	AK-QUBKA-CA  To order call: DTN 264-4446 or from outside, (603) 884-4446


AlphaStation 200 Series Overview
Overview Menu

Features
The Digital AlphaStation 255 system has the following features:

  DECchip 21064A.
  1 MB Bcache.
  Up to 1 GB of system memory (When
       256-MB SIMMs are available).
  Local bus architecture - 32-bit, 33MHZ PCI
      (also includes ISA bus).
  Easy upgradability: four expansion slots,
      four drive bays.
  Ethernet - 10BaseT on motherboard and optional 10Base2 adapter.
  Choice of operating system: Windows NT
      Workstation, Digital UNIX, or OpenVMS.
  Energy efficient hardware.
  3-year warranty.

Specifications:

  Mechanical
  Electrical
  Environmental


Mechanical Specifications
Digital AlphaStation 255 Family Overview
Mechanical Specifications

Height:	99.75 mm (3.9 inches)
Width:	425.0 mm (16.7 inches)
Depth:	400.0 mm (15.75 inches)
Weight:	11-14 kg (25-30 lbs)


Electrical Specifications
Digital AlphaStation 255 Family Overview
Electrical Specifications (for the 210 W power supply)

DC Outputs	Max Load	Max Power	Ripple  (Peak to Peak)
+3.3 V	20.0 Amp	66 W	50  mV
+5.0 V	20.0 Amp	100 W	50  mV
-5.0 V	0.3 Amp	1.5 W	120  mV
+12.0 V	8 Amp	96 W	120  mV
-12.0 V	0.5 Amp	6 W	120  mV

Note: The maximum power from any combination of +3.3 V and +5.0 V together must not exceed 115 W.


Environmental Specifications
Digital AlphaStation 255 Family Overview
Environmental Specifications

Operating temperature range	10 [image] C to 40 [image] C
Maximum rate of change	11 [image] C per hour
Relative humidity	20% to 80% with diskette or tape
Altitude	2400 meters (8000 feet) @36 [image] C
Acoustic - power	5.0 B LWAd (Idle), 5.1 B LWAd (operating)
Acoustic - pressure	40 dBA LpAm (idle), 43 dBA LpAm (operating)


Front View of the System


Digital AlphaStation 255 Family Overview
Front View of the System

1.	3.5-inch floppy drive.
2.	Floppy drive diskette eject button.
3.	CD drive.
4.	CD-ROM eject button.
5.	Reset button.
6.	Power on indicator.
7.	Disk activity indicator for drives attached to the embedded SCSI controller.


Rear View of the System


Digital AlphaStation 255 Family Overview
Rear View of the System

1.	Power on/off switch.
2.	Enclosure lock.
3.	ThinWire connector (10Base2) (optional).
4.	Enhanced bi-directional parallel port.
5.	Attachment point for a Kensington lock.
6.	PCI expansion slot.
7.	PCI expansion slot. (In this example a PCI graphics adapter is shown.)
8.	PCI/ISA combination slot.
9.	ISA expansion slot (for half-size ISA options only).
10.	Headphone jack.
11.	Microphone jack.
12.	Line in (audio into sound card from an amplifier).
13.	Network LEDs: Green indicates the system is linked to the network.  Yellow indicates network activity.
14.	Twisted pair connector (10BaseT).
15.	COM2 Serial line unit connector
16.	COM1 Serial line unit connector
17.	External SCSI port. (This connector must have a terminator if no external devices are connected.)
18.	Mouse connector.
19.	Keyboard connector.
20.	AC input.
21.	AC voltage selection switch (115 or 230).


Block Diagram


Block Diagram (Hot spotted)


Block Diagram - SROM
SROM

The Serial ROM (SROM) and the SROM bus are necessary for initial program load and diagnosis of the DECchip 21064A.  The SROM is 8 KB and contains code to perform power-up initialization and configuration of the CPU and I/O system.  In the AlphaStation 255, the SROM code is located in the flashROM.  A special interface transfers the SROM code from the flashROM to the CPU.


Block Diagram DECchip 21064
DECchip 21064

The DECchip 21064A is the system's CPU.  The chip includes integer and floating point units, and the primary caches.  The DECchip is a CMOS super-scalar, super-pipelined, dual instruction issue processor with the following features:

	233 MHz internal clock rate (model 4/233).
	3.3V supply voltage.
	Dual-instruction issue.
	Pipelined floating point unit.
	Instruction cache - 16-KB on-chip physical direct-mapped.  An Icache block (or line) contains 32-bytes of instruction stream data.
	Data cache - 16-KB on-chip write-through, direct-mapped, read allocated, physical tagged.  Each Dcache block contains 32-bytes of data.
	Write buffer with four 32-byte entries.
	Demand-paged memory management unit with:   12 entry I-stream translation buffer.   32 entry D-stream translation buffer.
	Parity for the onboard Icache and Dcache memories and the data bus.


Block Diagram Cache
Cache

The secondary cache  has the following features:

	1 MB, single-set, direct-mapped, write back, allocate on read and write.
	132 bits wide (128 data bits plus 4 parity bits).
	Cache line size = 32 bytes.
	16K Tag Store containing: 11-bit tag address, 3-bit control and 2-bit parity.


Block Diagram FlashROM
FlashROM

The flashROM is used to store SROM code, DROM code, NVRAM data, and console firmware (either AlphaBIOS or SRM).  The 512-KB flashROM is sector-erasable and re-writeable.  This capability allows a customer to update the firmware or change from SRM to AlphaBIOS or vice versa.

The diagnostic ROM (DROM) code contains power-on self test code (POST).  The DROM code is executed after being successfully loaded by the SROM code.  Following successful completion of POST, the DROM code loads and starts the console firmware (either the AlphaBIOS or SRM).  Alternatively, if there was a flashROM problem, the DROM code attempts to boot a floppy diskette.

The NVRAM portion of the flashROM is used to store setup information for the console firmware (AlphaBIOS and SRM).


Memory SIMMs

The main memory system has the following features:

	Eight industry-standard 72-pin SIMM sockets arranged in two banks, 0 and 1.  A bank consists of four SIMMs.  All SIMMs in a bank must be identical.
	Total size ranges from 16 MB to 1 GB. (When 128 MB SIMMs are available.)
	60 or 70 ns access time SIMMs.
	Each bank (four SIMMs) is 144 bits wide (Four 36-bit SIMMs with 128 data bits, 4 parity bits, and 12 unused bits).  You may encounter 33-bit SIMMs (The DRAMs for the unused bits are removed).


PCI to SCSI Adapter

The PCI-based SCSI controller is an NCR 53C810A.  It supports 8-bit single-ended fast SCSI-2 peripherals.  It supports devices at speeds from 5 MB/second (asynchronous) to 10 MB/second (synchronous).  The system supports internal SCSI peripherals as well as those external to the system unit.  Up to seven peripherals may be on the SCSI bus.

The default device ID of the SCSI controller is 7.


Realtime Clock (TOY)

The realtime clock (Dallas 1287 compatible) is included in the Super I/O chip.  The clock contains time and date information and 114 bytes of battery-supported RAM.  The RAM is cleared by firmware when DIP switch 1 and 2 are set to on (Reset RTC).

The clock is the source of a periodic interrupt for the CPU (CPUIRQ4).  This interrupt bypasses the ISA bridge interrupt controller.


ISA Bus

The ISA bus originates at the ISA bridge.  In addition to the two ISA slots on the riser card, the ISA bus connects to the audio subsystem and the Super I/O chip (adapter for the floppy disk, two serial lines, parallel port, time-of-year clock (TOY), and keyboard/mouse controllers).

ISA bus data width: 16 bits


Super I/O Chip

The Super I/O chip (National 87303) connects the ISA bus to the following:

  Floppy disk controller (FDC).

  Two serial lines (UARTs).

  Enhanced bi-directional parallel port.

  Keyboard and mouse ports.

  Realtime clock and battery supported RAM.


Memory Bus

The memory bus connects the data path portion of the core logic chip set to main memory and the ROM interface.

Width to/from memory:  128 bits plus 4 parity bits (one for each longword).

Width to/from ROM interface: 32 bits ( [31:8] for addressing and [7:0] for data ).


PCI Bus

The Peripheral Component Interconnect (PCI) is a 32-bit-wide multiplexed address/data bus with a clock speed of 33.33 MHz (allowing a peak transfer rate of up to 132 MB per second).

The PCI bus provides the system with its primary I/O interconnect.  The PCI bus originates in the PCI bridge portion of the core logic chipset.  Three PCI expansion slots, a SCSI-2 controller, the Ethernet LAN controller, and the ISA bridge are on the PCI bus.

PCI bus width: 32 bits (AD[31:0]).

An even parity bit (PAR) is calculated on 36 bits ( AD[31:0] and C/BE[3:0] ).


ISA Bridge

The ISA bridge manages traffic flow between the PCI bus and the ISA bus.  The bridge is an Intel 82378 System I/O (SIO) chip.


ISA Slots
ISA Expansion Slots

There are two ISA expansion slots on the riser card.  The uppermost ISA slot shares its position with the lowermost PCI slot, so the option in this position can be either PCI- or ISA-based.  The lower ISA slot is for half-size ISA options only.


ISA/PCI Combination Slot

The uppermost ISA slot shares its position with the lowermost PCI slot.  This combination slot can be use by either a PCI-based card or an ISA-based card.


PCI Bus Expansion Slots

There are two PCI-only expansion slots located on the riser card.  The slots accommodate full-sized 32-bit PCI options requiring +5V and/or +3.3V DC.


ROM Interface

The ROM interface handles the traffic between the main memory data bus and components on the flashbus (flashROM, configuration switch inputs, and power management functions).  The flashbus components are accessed by setting up an index register and then accessing a data register to either read or write data.

The ROM interface uses memory data bus [31:8] for address and control information and [7:0] for data.


Memory Control

The memory control is part of the core logic.  The major features of this area are:

	Control for filling Bcache and extracting victims on CPU-initiated transactions.
	Control for probing the Bcache on DMA transactions (and invalidating on DMA write hits).
	Provides sysBus arbitration.
	Stores addresses for the four cache-line deep memory write buffer.
	Controls the loading of the I/O write buffer and the DMA read buffer.


Decode
Data Path

The data path is part of the core logic.  The major data path functions are provided by:

	The error logic support longword parity.  Error checking is done on DMA transactions.  On CPU-initiated transactions, the CPU performs this function.
	The memory write buffer contains four entries.  Each entry is a cache line (32 bytes).  Data stored in this buffer has been through all coherency checks and is written to memory in the order in which it was received.
	The memory read buffer is a one-cache line temporary holding buffer used to hold data read from memory until it can be sent to the CPU or the DMA read buffer.
	The merge buffer is a one-cache line temporary holding buffer used to hold CPU data on memory writes.
	The I/O write buffer has two entries of one cache line each.  They act as buffers for CPU write data directed toward the PCI bridge or PCI bus.
	The DMA read buffer stores date that is being read from memory by a device on the PCI bus.  The buffer is two cache lines deep.
	The DMA write buffer stores four cache lines of PCI memory write data.  After cache coherency checks are performed, the buffer is unloaded.


Memory Address
Memory Address Bus

The memory-control portion of the core logic supplies the memory address over this bus to the main memory SIMMs.  Along with 12 address bits, RAS/CAS signals are sent to the SIMMs.


epiBus

The PCI bridge logic communicates with the data path logic using the epiBus.

epiBus width: 32 bits.


System Data Bus

The system data bus connects to the CPU, Bcache, memory control, and data paths.

System data bus width: 128 bits plus 4 parity bits (one for each longword).


System Address Bus

The system address bus connects the CPU, Bcache, memory control, and the PCI bridge.  The bus is 29 bits wide.


FlashBus

The flashbus ties the ROM interface logic to the flashROM and other components such as configuration switch inputs and power management functions.

Flashbus data width: 8 bits.


PCI
PCI Bridge

This logic functions as a bridge between the PCI and the CPU, Bcache, and memory.  The PCI bridge logic has the following features:

	Scatter/gather mapping from the 32-bit PCI address to the 34-bit physical address.  Address translations are speeded up by an eight-entry translation lookaside buffer (TLB).
	Sparse and dense space addressing is supported.
	Stores address information for the DMA write buffer and I/O write buffer.


Sound Card
Audio Subsystem

The AlphaStation 255 audio subsystem provides 16-bit stereo-quality audio.  It is compatible with the Microsoft Windows Sound System.  The subsystem is embedded on the motherboard and accessed through the ISA bus.

Connectors are provided at the rear of the system for line in, stereo headphones, and a microphone.  The audio subsystem drives the internal speaker and supports audio from the CD-ROM drive (if present).


Ethernet LAN Controller

The Ethernet LAN controller is a DECchip 21040 embedded on the motherboard.

A Twisted Pair (RJ45) connector is located on the rear of the system.  An optional media adapter unit (MAU) is available if a ThinWire connection is needed.


Media Adapter Unit (MAU)

The optional MAU furnishes a BNC connector for 10Base2 (ThinWire) Ethernet.


Scatter/Gather
Scatter/Gather Address Translation

Incoming 32-bit PCI memory addresses have to be mapped to the 34-bit physical memory space.  The mapping can be either direct (physical mapping with an extension register) or scatter/gather mapped (contiguous virtual pages can be mapped to pages scattered throughout physical memory).

When scatter/gather mapping is enabled, the translated address is generated by performing a scatter/gather map table lookup.  The translated base register specifies the starting base address of the scatter/gather map table.  Bits of the incoming PCI address are used as an offset from the base address of the table to form the address of a page table entry in the map.  The page table entry contains the physical address of the page.  PCI address bits [12:5] are appended to the page address to form the physical memory address.

The scatter/gather map table is stored in memory.  The PCI bridge incorporates an 8-entry translation lookaside buffer (TLB) to improve scatter/gather performance.


PCI Sparse Memory Space Definition
PCI Sparse Memory Space (2 0000 0000 - 2 FFFF FFFF)

Sparse memory space is a region in which the lower bits of the CPU address, [7:3], indicate the transfer size.  This space provides byte, word, or tribyte granularity, which the PCI bus requires.  CPU address bits [31:8] are sent out on the PCI bus as PCI AD[26:3].  If CPU address [31:29] is zero, host address extension register 0 (HAXR0) supplies PCI AD[31:27].  If CPU address [31:29] is non-zero, HAXR1 supplies PCI AD[31:27].


PCI Dense Memory Space Definition
PCI Dense Memory Space (3 0000 0000 - 3 FFFF FFFF)

Dense memory space is a region in which the minimum access granularity is a longword.  There is a one-to-one mapping between the CPU address and the PCI address.  In other words, a longword address from the CPU maps to a longword on the PCI bus.

Dense space is typically used for data buffers on the PCI.


What is AlphaBIOS?

AlphaBIOS brings a new, more PC BIOS-like interface to the older ARC firmware.  ARC stands for Advanced RISC Computing.  Its history dates back to an attempt to define an architecture for an industry standard computing platform based on a non Alpha architecture family of RISC CPUs.

To you, AlphaBIOS means the firmware system that supports the Microsoft Windows NT Workstation operating system.  AlphaBIOS does not support the Digital UNIX or OpenVMS operating systems (they use the SRM console).

The AlphaBIOS firmware is a simple to use menu-driven system.  AlphaBIOS code resides in a portion of the system flashROMs.  The design goal was to hide the complexities of older console designs from the console user.  For example, you do not need to remember actual environment variable names, just make a selection from a clearly worded list of choices.


What is SRM?

The very intuitive term SRM stands for System Reference Manual.  Anyone working for or with Digital knows that are many system reference manuals (VAX, Alpha, ...) There is probably an interesting history as to how this console earned the SRM moniker.  It might have something to do with the effort to make it the console to end all consoles.  This console can be so complex that some people refer to it as another operating system.

To you, SRM means the console system that supports the Digital UNIX or OpenVMS operating systems.  SRM does not support the Microsoft Windows NT Workstation operating system (It uses the AlphaBIOS firmware).

The SRM console is a full-blown command line interface system.  In the SRM world, syntax is king (or queen).  The SRM console code resides in a portion of the system flashROMs.  It is evident when typing help, that this is a substantial console.  That means the SRM is more suited as a troubleshooting tool than other consoles.  During troubleshooting, you might find the need to switch to the SRM console to locate an otherwise unobtainable piece of information.


Configuring the PC

Configuration Menu


Basic Workstation Configurations
Basic Configuration Information


Configuring the Digital AlphaStation 255 Systems
Basic Configuration Information

Digital AlphaStation 255 systems include:

	DECchip 21064A CPU.
	Two PCI slots, one PCI/ISA combination slot, and one ISA slot for half-size options.
	Eight SIMM sockets and parity-protection.
	Integrated PCI-based controllers for SCSI-2 and Ethernet.
	Factory-installed operating system (Digital UNIX or OpenVMS),  Microsoft Windows NT Workstation is not factory installed.
	600 MB CD-ROM (RRD45-AB).
	Embedded 16-bit audio with headset and microphone.
	Two serial ports and one bi-directional enhanced parallel port.
	PS/2 style keyboard and mouse ports.
	Keyboard and three-button mouse.
For specific package information, click on one of the operating systems listed below:

Windows NT Workstation	Digital UNIX	OpenVMS


Windows NT Packages

Windows NT AlphaStation 255 Base Package

Windows NT AlphaStation 255 systems are currently available as system building blocks (not as Advantage Configurations).  The Windows NT building block includes a 1.44-MB floppy drive.

Order Number	Memory (32 MB Required)	Hard Disk (1 Required)	Graphics (1 Required)
PB47-CA	32-MB  MSP01-BA 64-MB  MSP01-BB 128-MB MSP01-BC 256-MB MSP01-BD	1.0 GB  PBXRZ-ED 2.1 GB  PBXRZ-HB 4.3 GB  PBXRZ-NA	ZLX2-E1  PBXGB-AA ZLX2-E3  PBXGB-CA


Digital UNIX Packages
Digital UNIX Based Digital AlphaStation 255 Packages

Order Number	Memory	Hard Disk	Graphics	Floppy Disk
PB470-AA	32 MB	1 GB  RZ26F-E	ZLX2-E1  PBXGB-AA	None
PB470-BA	64 MB	2 GB  RZ28D-E	ZLXp-L1  PBXGC-AA	None
PB470-CA	32 MB	1 GB  RZ26F-E	#9 Trio64  PB2GA-JA	None
PB470-DA	32 MB	1 GB  RZ26F-E	ZLX2-E1  PBXGB-AA	1.44 MB
The PB470-DA also includes the AVP20-AA Multimedia Kit.

The Digital UNIX AlphaStation 255 System Building Block part number is PB47A-AA.


OpenVMS Package

OpenVMS Based Digital AlphaStation 255 Package

Order Number	Memory	Hard Disk	Graphics	Floppy Disk
PB471-AA	32 MB	1 GB  RZ26F-E	ZLX2-E1  PBXGB-AA	None
A PCI option in PCI slot 0, the lowermost PCI slot, is not supported on OpenVMS AlphaStation 255 systems.

The OpenVMS AlphaStation 255 System Building Block part number is PB47A-BA.


Internal Mass Storage Bays


Configuring the Digital AlphaStation 255
Internal Mass Storage Bays

The Digital AlphaStation 255 enclosure has four internal mass storage bays.

1.  The upper outside bay holds one 5 1/4-inch half-height, front-accessible or non-accessible storage device.  This is typically used for a CD-ROM drive.

2.  The lower outside bay area can hold two 1-inch high 3.5-inch drives (if there is no drive in the lower inside bay) or one 1.6-inch high drive.

3.  The upper inside bay is dedicated for a 3.5-inch 1.44 MB floppy drive.  The floppy disk, if present, is controlled by the floppy disk controller (FDC).

4.  The lower inside bay supports a 1-inch high 3.5-inch hard drive if there is one or no hard drives installed in the lower outside bay.  If lower outside bay contains two drives, this bay must be left unused.


Expansion Card Configuration

Configuring the Digital AlphaStation 255

Expansion Card Configurations

The Digital AlphaStation 255 supports both PCI and ISA options.  There are two PCI slots, one combination PCI/ISA slot and one ISA slot for half-size options.  An expansion option in the combination slot may either be an ISA option or a PCI option - but never both at the same time.

The following configuration rule applies to the slots:

If the system has:	Then the system may have up to:
Three PCI-slot options	One ISA-slot option
Two or less PCI-slot options	Two ISA-slot options
  Click here to return to the Configuration Menu.


Memory Configuration


Configuring the Digital AlphaStation 255
Memory Configuration

The Digital AlphaStation 255 memory may range from 16 to 1 GB (when 128-MB SIMMs are available).  The 70 ns DRAM memory plugs into the motherboard as two groups of four SIMMs (eight sockets).

An important guideline to keep in mind when adding memory is: a populated bank of memory must contain four SIMMs of the same capacity and bit size. (AlphaStation 255 systems may have 36- or 33-bit SIMMs.  Make sure each SIMM of a bank is identical.)  There are no restrictions on the physical ordering among the banks when using different sized bank pairs.  For example, the four SIMMs in bank 0 may be larger or smaller than the SIMMs in bank 1.  The initialization code will set the base address of the largest bank to the lowest address.


SIMM Width (33-bit or 36-bit)
SIMM Width (33-bits or 36-bit)

Your system may have SIMMs that are either 33-bits or 36-bits wide.  The AlphaStation 255 system use longword parity.  Therefore, three bits of a 36-bit SIMM are unused.  The 33-bit SIMM does not include the DRAMs for the three unused bits.

A pair of SIMMs in a bank must be the same capacity.  A bank may contain a 33-bit and a 36-bit SIMM as long as they are the same capacity.


Console Configuration


Configuring the Digital AlphaStation 255
Console Configuration

The Digital AlphaStation 255 flashROMs contain one of two possible console systems:

1.	AlphaBIOS, which supports Windows NT.

2.	SRM, which supports Digital UNIX and OpenVMS.

The SRM console may use either the graphics controller or the COM1 serial port as the console device.  The value of the console environment variable (serial or graphics) determines the device.  When console is set to serial, a terminal can be connected to the COM1 port and used as the console device.  The main keyboard and graphics display will still be active, although the POST countdown will not be displayed.

To switch from AlphaBIOS to SRM or vice versa, you must load the appropriate firmware into the flashROM from a CD-ROM or floppy diskette.  For example, to switch firmware from AlphaBIOS to SRM, insert a floppy or CD-ROM containing the SRM firmware.  From the AlphaBIOS setup screen, select Upgrade AlphaBIOS.


PCI Device Configuration


Configuring the Digital AlphaStation 255
PCI Device Configuration

The PCI bus must be initialized each time the system is powered on.  Configuration cycles (accesses to CPU addresses 1 e000.0000 through 1 fff.ff80) are used for this purpose.  The initialization device select (IDSEL) input is used to select a PCI device during configuration read and write transactions.  The AD bits associated with the PCI devices in the Digital AlphaStation 255 are shown below:

Device	IDSEL Bit Assignment	PCI Base Address	CPU  Base Address
SCSI	AD[17]	0002.0000	1 e006.0000
ISA Bridge	AD[18]	0004.0000	1 e007.0000
PCI Bus Slot #0	AD[22]	0040.0000	1 e00b.0000
PCI Bus Slot #1	AD[23]	0080.0000	1 e00c.0000
PCI Bus Slot #2	AD[24]	0100.0000	1 e00d.0000
Ethernet	AD[25]	0200.0000	1 e00e.0000

CPU base address <20:16> represents the encoded value of the IDSEL bit to be asserted (IDSEL bits range from PCI AD<31:11>).  For example, in a CPU base address of 1.e006.0000, the encoded IDSEL value is 06.  Starting at PCI AD<11> and counting up 7 bits (0-6), points to PCI AD<17>, which is hardwired as an IDSEL line to the SCSI controller.

The PCI specification defines three physical address spaces.  Besides the usual memory and I/O space there is configuration address space.  Configuration address space allows the devices to be initialized and configured by software/firmware.  PCI devices have 256 bytes of configuration register information.  Of the 256 bytes, 64 bytes are the predefined header region.  The remaining 192 bytes are device specific.

The console firmware performs the following PCI-configuration tasks:

Task		Action
Determine what PCI devices are present.		Try to read the ID registers.
When a device is located, determine its address space requirements.		All 1's are written to its base address register. Device returns the address bits it uses set to 1's, all others are 0's.
Initialize the base registers		Set up all base address registers in order from largest to smallest.
Determine interrupt assignments		The SRM console uses the configuration database to first identify ISA bus IRQ assignments.  It then assigns open IRQs to the PCI devices. The AlphaBIOS firmware assigns IRQs to the PCI devices as follows: IRQ10 to Ethernet IRQ10 to PCI slot 0 IRQ15 to PCI slot 1 IRQ9 to PCI slot 2 IRQ11 to the embedded SCSI


PCI Expansion Slots

The three PCI expansion slots are each unique.  PCI slot 0 is hardwired to IDSEL bit <22>.  This bit is used during the configuration cycle.  PCI slot 1 is hardwired to IDSEL bit <23> and PCI slot 2 is hardwired to IDSEL bit <24>.  Another PCI device, the Ethernet LAN controller, is mounted on the motherboard.  It is hardwired to IDSEL bit <25>.

PCI Slot 0 and the embedded Ethernet controller share the same interrupt line.  Before installing an option in PCI Slot 0, verify that your operating system supports shared interrupts.  The Digital UNIX and Windows NT systems support shared interrupts.


ISA Expansion Slots

The two ISA slots are electrically identical to each other.  The uppermost ISA slot is capable of holding a full-height ISA option.  (This is a combination slot.  If a PCI option is present, the slot is not available for ISA use.)  The lower ISA slot is restricted to a half-size ISA option.


PCI Configuration Space Header
PCI Predefined Header Region


SCSI Bus Configurations


Configuring the Digital AlphaStation 255
SCSI Bus Configurations

The SCSI controller (NCR 53C810) is a PCI option mounted on the motherboard.  The controller supports a total of seven internal and external fast SCSI-2 devices (up to three internal and the rest external).  Termination is required at both the internal and the external ends of the SCSI bus.

The internal SCSI bus cable connects to the motherboard at (1).  The daisy chained cable has connectors (2) available for a devices in the lower inside bay and lower outside bay including a connector (3) for the CD-ROM drive.  The last bus connector (4) must be connected to a terminator plug (12-36929-03) at all times.

For more information:
  SCSI bus length restrictions.
  Guidelines when adding internal SCSI devices.
  Internal termination.
  External termination.


SCSI Bus Length

The total SCSI bus length, including internal cables and etch on the motherboard as well as the external cables between storage enclosures and the cables inside the storage enclosures, must not exceed three meters (9.8 feet) for fast SCSI operation or four meters (13.1 feet) for slow SCSI (5 Mbyte/second) operation.  The AlphaStation 255 system's internal SCSI length is about 1.1 meters (3.6 feet), leaving 1.9 meters (6.2 feet) available for external fast SCSI use (2.9 meters (9.5 feet) for slow SCSI).


SCSI Bus Internal Termination

The drives attached to the internal SCSI bus must have their termination disabled.  The end connector of the SCSI cable must be terminated with the SCSI terminator plug (12-36929-03).  If you add devices on the internal SCSI bus at the daisy-chain connectors, make sure that the device's termination is disabled.  Refer to the appropriate drive manual.


SCSI Bus External Termination

  When no external SCSI peripherals are present, the external portion of the SCSI bus must be terminated at the SCSI connector on the rear bulkhead (see number 1 in the figure).  A SCSI terminator (12-41667-01) ships with each system  When an external SCSI cable is present, termination must be provided by the last external SCSI device.  If you add external SCSI peripherals (see number 2 in the figure), make sure the last peripheral on the external SCSI bus is properly terminated.


Adding Internal SCSI Devices Guidelines
Guidelines When Adding Internal SCSI Devices

	The end connector of the internal SCSI cable is for the terminator plug (12-36929-03).
	Internal SCSI devices using a daisy-chained connector must not have their terminator enabled.
	The external portion of the SCSI bus must be terminated.  If no external devices are present, use the provided terminator (12-41667-01).  If external device are present, the last drive must provide termination.


ISA Bus Configurations


Configuring the Digital AlphaStation 255
ISA Bus Configurations

The Digital AlphaStation 255 has built-in ISA devices as well as slots for up to two additional ISA options.  The built-in devices are the audio subsystem and the Super I/O chip (National PC87303), which provides controllers for the floppy disk bus, two serial lines, keyboard and mouse, real time clock, and the bi-directional enhanced parallel port.

Before adding ISA options to an OpenVMS or Digital UNIX system, use the ICONFIG utility to add the new options into the configuration database.  If an option is added to the system without the database being updated, and the operating system is booted, the system could hang.  The SRM firmware uses the configuration database to determine PCI IRQ assignments.  If the SRM firmware does not know about an ISA option, a PCI option might inadvertently be assigned the same IRQ as the ISA option, possibly resulting in a hung operating system.

The OpenVMS operating system also uses a VMS configuration file (ISA_CONFIG.DAT).  Check the OpenVMS operating system documentation for information about maintaining the contents of this file.

Note: The Windows NT AlphaBIOS firmware preassigns IRQ9, 10, 11, and 15 to PCI devices.  If one of the PCI devices associated with these IRQs is not installed, the IRQ remains unavailable for other uses.

Use the following procedure when adding ISA options to Digital UNIX and OpenVMS systems:

Action	Result or Next Step
1.  Perform operating system configuration tasks, if any.  Refer to your operating system installation guide and release notes.	The operating system is prepared for the ISA option.  Click here to see ISA addresses.
2.  Shut down the system.	The system is at the console prompt (>>>).
3.  >>>iconfig	Adds the new ISA option to the SRM console configuration table using the appropriate command options.  (See the ICONFIG command for details)
4.  >>>init	Typing init incorporates the changes into the configuration database.
5.  Configure the ISA option.	Using the ISA option's documentation set up the option to match the configuration database.
6.  Turn off the system and install the ISA option.	The option is mounted in the system.
7.  Turn on the system and boot.	The operating system boots and sees the new ISA option.


Interrupts


Configuring the Digital AlphaStation 255
Interrupts

Take care to avoid setting up interrupt conflicts.  Click on the blocks below for more information about the interrupt system.


CPU Interrupts

Name	irq_h	Source	Comments
ERR_IRQ	0	Core logic	CPU bus and parity errors
Not used	1
INT	2	PCI/ISA bridge	8259 compatible types (ISA and PCI device interrupts)
NMI/SERR	3	PCI/ISA bridge	Non-maskable interrupts (IOCHK and SERR)
IRQ8	4	RTC section of the SIO chip	Realtime clock
HALTREQ	5	Front panel switch	Controlled by switch 4


IRQ Assignments

The timer, keyboard, and mouse are hardwired to IRQs 0, 1, and 12 respectively.  The parallel port (LPT1) is assigned to IRQ7, although it is possible to use IRQ5.

IRQ8, normally the interval timer interrupt, is not connected to the IRQ controller in the AlphaStation 255.  Instead, the timer interrupt signal is routed directly to the CPU.

IRQ13, normally used to signal a coprocessor error or signal the end of a DMA scatter/gather operation, is not connected in the AlphaStation 255.


PCI IRQ Assignments

Single function PCI devices have PIRQ numbers based on the device's location.  In the AlphaStation 255 the PIRQs are wired as follows: embedded Ethernet to PIRQ0, PCI slot 0 to PIRQ0, PCI slot 1 to PIRQ1, PCI slot 2 to PIRQ2, and the embedded SCSI controller to PIRQ3.  Caution: PCI slot 0 shares the interrupt signal with the Ethernet controller.  Not all operating system support shared interrupts.

Firmware sets bits in the route control registers to assign a PIRQ to an IRQ level.  The available IRQ levels are 5, 9, 10, 14, and 15.  The SRM console assigns the IRQs to PCI devices based on what IRQs are already allocated to ISA devices.  The ISA IRQ allocation data is contained in the configuration database, which is maintained with the ICONFIG command.  For example, since the parallel port is assigned to IRQ7, the SRM console will not assign a PCI device to that IRQ.  You must update the configuration database before physically adding an ISA option.  This ensures that a PCI device will not receive an ISA device's IRQ, which could cause the system to hang.  Because the ISA IRQ values stored in the database are used to determine the PCI IRQ assignments, it is important to leave enough IRQs available for the PCI options on the system.

Windows NT has hardcoded the PIRQ to IRQ assignments.  Keep these in mind when adding ISA options to a Windows NT system.  The assignments are:

PIRQ0 (Ethernet)	to   IRQ10
PIRQ0 (PCI slot 0)	to   IRQ10
PIRQ1 (PCI slot 1)	to   IRQ15
PIRQ2 (PCI slot 2)	to   IRQ9
PIRQ3 (SCSI)	to   IRQ11


Interrupt Sharing

When an interrupt on a shared line is asserted, it is not possible to determine which device asserted the interrupt, except by polling all the devices attached to the line.

Interrupt sharing is allowed if supported by the operating system.  For example, only non interrupting devices can be installed in PCI slot 0 when the system is running the OpenVMS operating system.  An interrupt from PCI slot 0 is shared with the embedded Ethernet controller and the OpenVMS system would cannot distinguish between the two.


ISA IRQ Assignments

To prevent conflicts, exercise care when assigning interrupts.  When assigning IRQs to ISA devices on a Digital UNIX or OpenVMS system, remember to update the console configuration database with the ICONFIG command before adding the option.  Make sure enough IRQs remain available for the PCI options on the system.

The possible IRQ levels for options are 3-7, 9-12, 14, and 15.  Of these IRQs: 3, 4, 6, 7, 11, and 12 are already assigned.  This leaves IRQ 5, 9, 10, 14, and 15 available.

If the system has three of these IRQs assigned to ISA options (for example, the audio subsystem and two ISA options in the riser card), the two remaining IRQs would be available for PCI options (the Ethernet controller and one of the PCI slots on the riser card).

The audio subsystem is capable of using IRQ7, 9, 10, or 11.  Of these, IRQ7 (parallel port), and IRQ11 (SCSI controller), are already assigned.  (Note: The operating system may use polled I/O to access the parallel port, therefore freeing IRQ7.  This is the case with Digital UNIX and Windows NT systems.)

By disabling an existing ISA device with ICONFIG ( Enabled = N), another IRQ could be made available.  This strategy is used when adding the FaxModem (PCXDF-AA) ISA option with the ADD_FAX command.  The COM2 port is disabled and its IRQ3 is reassigned to the FaxModem option.

If you are working on a Windows NT system, the ARC console preassigns IRQ 9, 10, 11, and 15 to PCI devices, if they are present.


IRQ Controller

The interrupt controller is the functional equivalent of two 82C59 controllers and is located in the PCI to ISA bridge chip.  IRQ2 on the master controller is used to cascade the controllers together.  This means that IRQ8-IRQ15 have a higher priority than IRQ3-IRQ7.


DMA Channel Assignments


Configuring the Digital AlphaStation 255
DMA Channel Assignments

The ISA interface uses eight DMA channels.  DMA channel 4 is used to cascade the two four-channel controllers together and therefore is unavailable.

Any DMA channel may be programmed for 8-bit or 16-bit transfers.

Avoid conflicts.  For example, remember that if the audio subsystem is using channel 0 and 1, those channels are no longer available to the ISA option slots or the parallel port.

Channel	Available To:
0	Audio subsystem, ISA option slots, or the parallel port (ECP).
1	Audio subsystem, ISA option slots, or the parallel port (ECP).
2	Floppy Disk Controller.
3	Audio subsystem or ISA option slots.
4	Unavailable (Channels 0-3 are cascaded to this channel).
5	ISA option slots.
6	ISA option slots.
7	ISA option slots.


Address Space Map


Configuring the Digital AlphaStation 255
Address Space Map

Cacheable
0 0000.0000 -	0 ffff.ffff	Main memory (cacheable)
Non-cacheable
1 0000.0000 -	1 7fff.ffff	Non-cacheable memory
1 8000 0000 -	1 9fff.ffff	Memory controller registers
1 a000.0000 -	1 afff.ffff	PCI bridge registers
1 b000.0000 -	1 bfff.ffff	PCI interrupt/special cycle
1 c000.0000	1 dfff.ffff	PCI sparse I/O space (16 MB)  The lower 256 KB of this space is used for addressing PCI and ISA devices.  Click here to see ISA addresses.
1 e000.0000	1 ffff.ffff	PCI configuration space
PCI sparse memory space
2 0000.0000 -	2 ffff.ffe0	128 MB of PCI space (lower address bits carry byte masks and length information).  Used when byte, word, tribyte, longword, or quadword access granularity is required.
PCI dense memory space
3 0000.0000 -	3 ffff.ffe0	4 GB of PCI space.  Used for devices with access granularity greater than a longword.  Typically used for data buffers.


I/O View of Address Space


Configuring the Digital AlphaStation 255
I/O View of Address Space


Halt Request

A halt request may be asserted when you press the front-panel Halt/Reset button.  Dipswitch 4 determines whether the button generates a halt request or a reset.


Motherboard
Motherboard Configuration


Configuring the Digital AlphaStation 255
Motherboard Configuration

1.	DECchip 21064A CPU
2.	Interrupt PAL
3.	Factory diagnostic port (SROM port)
4.	Diagnostic LED
5.	DIP switch pack
6.	Battery
7.	Audio connectors (headphone, microphone and Line-In)
8.	Twisted-pair Ethernet and network LEDs
9.	COM1 and COM2 (adjacent to Ethernet) ports
10.	SCSI (lower) and parallel ports
11.	Mouse and keyboard ports
12.	MAU cable connector
13.	Power (+/- 12 VDC, +/- 5 VDC)
14.	Power (+3.3 VDC)
15.	Speaker connector
16.	CD-ROM audio connector
17.	Internal SCSI connector
18.	Floppy connector
19.	Front panel connector
20.	Fan power connector
21.	Riser card connector
22.	Ethernet identification (EID) ROM


ISA Device Addresses

All addresses are shown in hexadecimal.

Device	ISA Address	PCI Address	CPU Address
Keyboard	060	0000 0060	1 C000 0C00
Mouse	064	0000 0064	1 C000 0C80
TOY clock	070 071	0000 0070 0000 0071	1 C000 0E00 1 C000 0E20
Serial port 1	03F8 - 03FF	0000 03F8 -  0000 03FF	1 C000 7F00 - 1 C000 7FE0
Serial port 2	02F8 - 02FF	0000 02F8 -  0000 02FF	1 C000 5F00 -  1 C000 5FE0
Parallel port	0378 - 037F	0000 0378 -  0000 037F	1 C000 6F00 -  1 C000 6FE0
Floppy disk controller	03F2 - 03F7	0000 03F2 -  0000 03F7	1 C000 7E40 -  1 C000 7EE0
Audio subsystem	530 - 533	0000 0530 -  0000 0533	1 C000 A600 -  1 C000 A660


ZLXp-E Graphics Adapter Configuration
ZLXp-E Graphics Option


Configuring the Digital AlphaStation 255
ZLXp-E Graphics Option

The ZLXp-E1/E2/E3 PCI-based graphics options are commonly found on AlphaStation 255 system.  The option types are:

Option	Planes	Max Colors	VRAM
ZLXp-E1	8	256	2MB
ZLXp-E2	24	16M	8MB
ZLXp-E3	24Z	16M	16MB

The ZLXp-E1/E2/E3 options have four switches which are used to select the frequency and resolution of the video signal when the adapter is used with OpenVMS and Digital UNIX systems.  Windows NT ignores the switch settings.  The AlphaBIOS firmware initially sets the adapter to VGA.  As Windows NT is booted, the adapter is set to the last values chosen from the Control Panel Display applet.

  Click here for a view of the ZLXp-E switches.

The possible frequency, resolution, and refresh rates for each switch setting are shown below:

Switch Setting	Pixel  Frequency (MHz)	Monitor Resolution (Pixels)	Refresh Rate (Hz)	Monitor Models
0	130	1280x1024	72	VRC16-HA/H4, PCXAV-EA/EC/ED/HA/H4, VRC21-HA/H4
1	119	1280x1024	66	VRC16-CA/C4/HA/H4, PCXAV-EA/EC/ED/HA/H4, VRC21-HA/H4, VR319-C, VR320-C, VRT19-D/H, VRT16-D/H
2	108	1280x1024	60	VRC16-CA/HA
3	104	1152x900	72	VRC16-CA/HA
4	93	1152x900	66	PCXAV-HA/H4, VRC21-HA/H4, VRC16-CA/HA, VRM17-AA/HA
5	75	1024x768	70	VRC16-HA/H4, PCXAV-EA/EC/ED, PCXBV-PC/PD
6	74	1024x768	72	VRC16-CA/C4/HA/H4, PCXBV-PC/PD, PCXAV-EA/EC/ED/HA/H4, VRC21-HA/H4, VR297-DA/D3/D4, VR299-DA/D3/D4
7	69	1024x864	60	PCXAV-EC/ED/HA/H4, VRC21-HA/H4, PCXBV-PC/PD, VRC16
8	65	1024x768	60	VRC16-CA/C4/HA/H4, PCXAV-EA, PCXBV-PC/PD
9	50	800x600	72	VRC16-CA/C4/HA/H4, PCXAV-EA/EC/ED/HA/H4, PCXBV-PC/PD, VRC21-HA/H4
10	40	800x600	60	VRC16-CA/C4/HA/H4, PCXAV-EA/HA/H4, PCXBV-PC/PD, VRC21-HA/H4
11	32	640x480	72	VRC16-CA/C4/HA/H4, PCXAV-EA/HA/H4, PCXBV-PC/PD, VRC21-HA/H4
12	25	640x480	60	VRC16-CA/C4/HA/H4, PCXAV-EA/EC/ED/HA/H4, PCXBV-PC/PD, VRC21-HA/H4
13	135	1280x1024	75	PCXAV-EC/ED
14	110	1280x1024	60	PCXAV-EC/ED/HA/H4, VRC21-HA/H4
15	Reserved


ZLXp-E Frequency Switches


Troubleshooting

Troubleshooting Menu


Troubleshooting Strategy


Digital AlphaStation 255
Troubleshooting Strategy

A successful troubleshooting strategy requires a plan of attack.  Gathering information is the first action to perform.  Use the site log to review the system's service history.  Ask the user or customer contact the following questions:

	What first alerted the user to the problem?
	Were there any recent changes or upgrades to the operating system, firmware, or application software?
	What symptoms did the user notice?  Ask about any unusual sounds or smells.
	Did the user make any initial troubleshooting efforts?  What were the results?
	Is the operating system functioning? If the answer is no, use power on self test (POST) and other loadable diagnostics. If the answer is yes, use it to gather information from log files such as the error log , operator log, and crash dump files.  Run operating system-based diagnostics, such as DEC VET for the DIGITAL UNIX system or UETP for the OpenVMS system.


Troubleshooting Process
A Troubleshooting Strategy


Power System Troubleshooting


Digital AlphaStation 255
Power System Troubleshooting

Symptom	Check

Control panel power indicator is OFF.	Power switch on rear of system is on (1 side pushed in).
	Power at wall receptacle.
	AC cord.
	Voltage selection switch.
Control panel power indicator is ON for a few seconds and then goes OFF.	The power supply fan may have failed.  Replace the power supply.
Control panel power indicator is ON and display monitor is blank.	Monitor power indicator is ON. Raster present if brightness is turned up.
	Fuses and circuit breakers.
	Video controller cable properly connected.
	SROM error-code indicators.
	Power present at system board.  Click here for pinouts.


Power Supply Pinouts


Power Supply Pinouts

Power 	Pin	Wire 	Voltage
Supply 	Number	Color
Connector

P1 (Disk Drive)	1 2 3 4	Red Black Black Orange	+5V GND GND +12V
P2, P3, P4 and P5 (Disk Drives)	1 2 3 4	Orange Black Black Red	+12V GND GND +5V
P8 (motherboard)	1 2 3 4 5 6	White Red Orange Yellow Black Black	POK_H +5V +12V -12V (key) GND GND
P9 (motherboard)	1 2 3 4 5 6	Black Black Red Red Red	GND (key) GND nc +5V +5V +5V
P10 (motherboard)	1 2 3 4 5 6	Black Black Black Green Green Green	GND GND GND +3.3V +3.3V(key) +3.3V
P11 (motherboard)	1 2 3 4 5 6	Green Green Green Black Black Black	+3.3V +3.3V +3.3V GND GND GND(key)


Cooling Problems
Thermal Problems


Digital AlphaStation 255
Thermal Problems

The Digital AlphaStation 255 system operates in an ambient temperature range of 10 to 40C.  The system unit is cooled by two speed-controlled fans.  One fan is in the power supply, and one is in front of the CPU.

The fan near the CPU controls its own speed based on the temperature.  It is powered by +12 VDC.

Intermittent problems could result from overheating.  Check that the air flow path is clear.  Make sure there are not any materials blocking the input grill.  Also, check to see that the cables inside the system are properly dressed and not impeding the airflow.


Initialization and POST Errors


Digital AlphaStation 255
Initialization and POST Errors

The symptoms of an initialization or power-on self test (POST) problem are heard as a beep codes or displayed on the monitor (if enough of the logic is functioning correctly).

When power is turned on, SROM code initializes the CPU, core logic, and memory.  After successful initialization, the SROM code loads the DROM POST code.  The DROM POST code primarily performs data-path verification along with some functional testing.  Typically, POST reports errors that would prevent the SRM or AlphaBIOS firmware from coming up.

For more information, click on a button below:

  SROM initialization steps

  DROM tests

  Firmware initialization steps

  Beep codes


SROM Initialization Tests
SROM Initialization


Digital AlphaStation 255
Initialization

SROM Initialization Steps

Initialize CPU (BIU_CTL and ABOX registers initialized).

Initialize bank 8 logic.  Executing memory sizing code.

Memory sizing completed.  Configuring memory.

Memory configuration successful.
Bcache initialization started.
Initializing all memory to zeroes.

Bcache initialization successful.
Bcache references OFF and Dcache OFF.
Initialize the low 8MB of memory to zero.
Executing memory test 1 of 4.

Memory test 1 of 4 complete.
Executing memory test 2 of 4.
Bcache references ON and Dcache OFF.

Memory test 2 of 4 complete.
Executing memory test 3 of 4.
Bcache references OFF and Dcache ON.

Memory test 3 of 4 complete.
Executing memory test 4 of 4.
Bcache references ON and Dcache ON.

Memory test 4 of 4 complete.

Initialize the core logic registers.

Reserved for future.

Load the DROM code into memory.

Successful load and checksum of DROM

Initialize registers required by console firmware and the PAL_BASE and EXEC_ADDR registers.

Check switches 1 and 2: If both are OFF (normal), then HW_REI to PAL.  If switch 1 is OFF and 2 is ON (SROM prompt), go to the SROM mini-console.


DROM POST Tests


Digital AlphaStation 255
DROM POST Tests

POST Sequence

DROM code entered.

PCI Bridge core logic errors cleared.

Memory test.

FlashROM ID test.

NVRAM test.

SCSI controller (53C810) test.

System I/O (82378) test.

TOY (RTC) test.

Keyboard controller test.

Super I/O (87303) test.

Interrupts test.

Call floppy loader if necessary.

Jump to floppy code.

Call flashROM loader.

Jump to flashROM code (AlphaBIOS or SRM).

Run the DROM console.

Floppy loader failed

FlashROM loader failed


Console Initialization Steps
Console Initialization (ARC and SRM)


Digital AlphaServer 400 Series
Console Initialization

Initialization Steps

AlphaBIOS

Initialize the video and keyboard.  If either is not functioning or is missing, AlphaBIOS directs output to the COM1 port.

Display a windowed, graphical-style user interface.

Test memory.

Initialize SCSI controllers and disks.

Display the boot screen.

SRM Console

Console starting (FF).

Initialize idle PCB (FE).

Initialize semaphores (FD).

Initialize heap (dynamic memory) (FC, FB, and FA).

Initialize driver structures (F9).

Initialize idle process PID (F8).

Initialize file system (F7).

Initialize timer data structures (F6).

Lower the IPL (F5).

Enter the idle loop (F4).

Memory configuration (EF).

Initialize IRQ vector table and configure PCI bus (DF).

DDB startup parts 1, 2, and 3, and locate HWRPB (EE, ED, and EC)

Test memory greater then 8 MB (EB).

DDB startup part 4 (EA).

Set keyboard type according to language variable (E9).

Initialize environment variables (E8).

Initialize SCSI (E7).

DDB startup part 5 (E6).

Show version and console idle (normal final state) (E5).


Beep Codes


Digital AlphaStation 255
Beep Codes

Beep Code     Meaning

1-1-4	The SROM code could not be read from the DROM or flashROM header, or there was a checksum failure.
1-2-4	The SROM code detected a memory test failure.
1-2-1	POST detected a realtime clock failure, or the realtime clock interrupt did not occur.
1-3-3	The SROM code could not find 2 MB of good memory, or no memory is present.
3-2-4	POST detected a keyboard/mouse controller failure.
3-2-1	POST was unable to read the header of the flashROM, or the flashROM checksum failed.  Therefore POST attempted to boot from the floppy diskette.  The attempt failed because there was no boot block on the floppy diskette.
3-2-3	The DROM code was directed to load the floppy diskette, but there was no boot block on the diskette..
3-3-1	POST detected a hard failure during testing.


What is a Beep Code?

Beep codes are heard from the system's speaker as three groups of beeps.  For example, if the SROM code could not find any good memory, you would hear a 1-3-3 beep code (one beep, a pause, a burst of three beeps, a pause, and another burst of three beeps).


SROM Mini-Console
SROM and DROM Mini-Consoles

The SROM and DROM mini-consoles are provided for use by manufacturing.  The SROM Serial Port Adapter Module (54-21827-01) is connected to factory diagnostic connector on the motherboard.  A terminal can then be connected to the port adapter.  Both consoles feature a set of basic commands.


DROM Load or Checksum Failure

If the code from the DROM fails to load properly or the SROM detects a DROM checksum error, the SROM will attempt to load the AlphaBIOS or SRM firmware (whichever is loaded in the flashROM).  If the firmware also failed to load properly, the SROM code jumps to the mini-console.


DROM Unable to Load Flash Code
Flash Code Fails to Load

If the SROM code is unable to load the DROM code and is also unable to load the flash code (console firmware), or there is a checksum error after loading the flash code, the SROM will jump to its mini-console.

The DROM code has a built-in failsafe mechanism that will attempt to load from a floppy if flashROM problems are detected.  The floppy should have an Alpha boot block and contain the Update utility.


DROM Floppy Load Failed
Floppy Load Failure

If the flashROMs are corrupted, the DROM code will use its failsafe mechanism and attempt to load a floppy.  The floppy should have an Alpha boot block and contain the Update utility.  If the floppy boot block is not present, the DROM code loops at this point.


Console Troubleshooting


Digital AlphaStation 255
Console Troubleshooting

The Digital AlphaStation 255 flashROMs contain one of two possible console firmware systems:

1.	AlphaBIOS, which supports the Windows NT system

2.	SRM, which supports the DIGITAL UNIX and OpenVMS systems.

The SRM firmware does not contain diagnostics.  (Manufacturing has a superset of the SRM firmware which contains loadable diagnostics to support their environment.)

The flashROM (console firmware) is typically loaded by DROM code's flash loader.  If the flashROM is corrupted, or the checksum verification failed, the DROM flash loader will fail.  If a power failure occurs while the firmware was being updated, it could corrupt the contents of the flashROMs.

When the system is powered on, the DROM code, sensing the flashROM corruption, will attempt to load from the floppy drive.  The DROM code will continuously try to load the floppy,

Other problems and solutions follow:

Unable to switch from AlphaBIOS to SRM or vice versa.	Verify that switch 3 is in the OFF position.  Use the Alpha Systems Firmware Update CD-ROM to switch between consoles
SRM POST countdown display fails to appear.	Hit the return key a few times.  If the >>> prompt appears on the monitor, the console variable is set to serial.  Type set console graphics, then type init.  The countdown should now be displayed.  The console variable is stored in the flashROM.  If the flashROM gets cleared, the console variable will be set to serial (This happens when switches 1 and 2 are set to ON and the power is cycled.
SRM POST countdown displays, then system hangs. Sometimes pressing the reset button results in the >>> prompt.	Try booting the system and setting the clock.
Unable to get to the console prompt (>>>)	The system is set to autoboot, try the following: 1.  Type control C's during POST testing,  2.  Type control P before the windowing system is up, or 3.  Disconnect the disk. Once you are at the prompt, type: set auto_action halt to prevent autobooting.  If after doing the above steps the prompts still fails to appear, maybe some environmental variables are corrupt.  Power off the system, set switches 1 and 2 to the OFF position, power on the system and wait until the console prompt appears.  Then, power off the system, set switches 1 and 2 to the ON position, and power on the system.
Monitor is unreadable because it's out of sync.	Check to see if the monitor requires the sync signal on the green signal.  On a Digital UNIX or OpenVMS system with a ZLXp controller, set tga_sync_green to 1 (1 for the first ZLXp,  2 for the second, or 3 for both).  To set the variable, temporarily put on a five-wire monitor or hook a terminal to the COM1 port and use the serial console.
AlphaBIOS does not start.	Check that the keyboard is plugged in and the video controller and monitor are properly connected and working.  If the keyboard or video is missing or not functioning, AlphaBIOS sends information to the COM1 port.


Boot Troubleshooting


Digital AlphaStation 255
Boot Troubleshooting

Possible Cause	Action

Will not boot from an IDE hard disk drive.	Configuration not supported.
Operating system software is not installed on the hard disk drive.	Install the appropriate operating system.
System cannot find the boot device.	Check the system configuration for correct device parameters. Digital UNIX and OpenVMS: Use the SRM show config and show device commands.  Use the displayed information to identify target devices for the boot command, and verify that the system sees all of the installed devices.  If you are attempting to use bootp, first set the following variables as shown: >>>set ewa0_inet_init BOOTP >>>set ewa0_protocols BOOTP Windows NT: Use the AlphaBIOS firmware to display the available boot devices from the Display System Configuration screen.  Verify that the target boot device is listed.
Environment variables incorrectly set (this could happen if the battery or the entire motherboard was replaced, thereby losing the previous configuration information).   Configuration information is stored in the flashROM and RTC memory on the motherboard.  If the motherboard is replaced, the information in the flashROM and real time clock is lost.  If the battery is replaced, the information in RTC memory is lost.  Keeping records of the configuration (IRQs, DMAs, I/O addresses, and so forth) will facilitate getting the system back into use.	Check and set the environment variables, if necessary. DIGITAL UNIX and OpenVMS: Use the SRM console show and set commands to check and set the values assigned to boot-related variables such as auto_action, bootdef_dev, and boot_osflag. Windows NT: From the AlphaBIOS Setup, check the CMOS setup screen and the OS Selection Setup (under the Utilities selection).
Hard disk drive is not correctly formatted or the requested partition does not exist.	Format the hard disk drive or correctly partition the hard disk drive using appropriate tools (for example, Hard Disk Setup under AlphaBIOS).
There is no software on the requested partition.	If the command is pointing to the correct partition, install the software.  Otherwise, change the variables to point to the correct partition.
Target boot device is not listed in the show device, show config (SRM), or the Display System Configuration (AlphaBIOS) due to a SCSI bus problem.	Check the cables.  Are the cables oriented properly and not cocked? Are there bent pins? Check all the SCSI devices for incorrect or conflicting IDs.  Refer to the device's documentation. SCSI termination: The SCSI bus must be terminated at the end of the internal cable AND at the last external SCSI peripheral.  The internal SCSI bus must be terminated by a terminator plug (12-36929-03). If no external SCSI cable or devices are plugged into the rear SCSI connector, the external portion must be terminated with the provided plug (12-41667-01).


Troubleshooting Errors and Machine Checks
Machine Checks


Digital AlphaStation 255
Machine Checks

When an error exception occurs, the CPU does the following:

1.	Drains the pipeline.
2.	Loads the program counter (PC) into the EXC_ADDR register.
3.	Dispatches to a PALcode exception routine located at PAL_BASE plus an offset.  The offset for machine checks is 0x0020.
4.	The PALcode then sets to work gathering information and building a machine check stackframe.
NOTE: Digital UNIX and OpenVMS systems build detailed machine check stackframes that can be used to isolate specific failing FRUs.  Windows NT systems (PALcode and HAL) treat machine checks in a more superficial manner and you may find yourself forced to resort to pop-and-swap troubleshooting when trying to fix these systems.

  Click here for an approach to analyzing a machine checks.


Error Checking Map


Error Checking Map (Hot spotted)


DECchip 21064A Error Detection

Error detection in the DECchip 21064A is concentrated in the Bus Interface Unit (BIU).  The AlphaStation 255 CPU uses parity mode (one parity bit per longword).  Click on an error for more information.

Tag Address Parity Error

Tag Control Parity Error

System External Transaction Terminated with CACK_SERR

System Transaction Terminated with CACK_HERR

I-stream Parity Error (Parity mode only)

D-stream Parity Error (Parity mode only)

Icache Parity Error and Dcache Parity Error


Tag Address Parity Error

When the CPU performs a tag probe operation, the tag address [33:17] and its parity bit are checked for even parity.  If the parity is wrong, the tag probe is forced to miss, an external transaction is initiated, and if machine checks are enabled, the 21064A traps to PALcode.

BC_TAG: holds the result of the external cache probe

BIU_STAT: BC_TPERR bit is set

BIU_ADDR: holds the address.

The tag address [33:17] and its parity are never written by the CPU, they are written by the memory control logic during a Bcache miss transaction.  If you see this error, check the CPU module and cable dressing (cables blocking airflow might cause component overheating).

  Return to the CPU error detection window


Tag Control Parity Error

The Tag Control RAM is written by the memory control logic during cache refills and DMA writes that hit in the Bcache, and the CPU during CPU writes that hit in the Bcache.  Therefore, depending on the type of transaction, both the 21064A and the memory control logic are capable of computing the even parity.  When the CPU performs a tag probe operation, the tag control bits (Valid, Shared, and Dirty) and the associated parity bit are read and checked for even parity.  If the parity is wrong, the tag probe results in a miss, an external transaction is initiated, and if machine checks are enabled, the 21064A traps to PALcode.

BC_TAG: holds the result of the external cache probe

BIU_STAT: BC_TCPERR bit is set

BIU_ADDR: holds the address.

If you see this error, check the CPU module and cable dressing (cables blocking airflow might cause component overheating).

  Return to the CPU error detection window


System External Transaction Terminated with CACK_SERR

When the 21064A requests an external cycle, its external interface will keep the cycle until it is acknowledged by the external logic.  The CACK_SERR (soft error) indicates that a failure occurred during the cycle, but the failure was corrected.  The memory control logic in the AlphaStation 255 does not use the soft error acknowledge, therefore you should not see this error.

BIU_STAT: BIU_SERR bit is set, BIU_CMD holds CREQ (the cycle type)

BIU_ADDR: holds the address.

  Return to the CPU error detection window


System External Transaction Terminated with CACK_HERR

When the 21064A requests an external cycle, its external interface will keep the cycle until it is acknowledged by the external logic (memory control).  The CACK_HERR indicates that a catastrophic failure occurred during the cycle.  A machine check will be initiated if enabled.

BIU_STAT: BIU_HERR bit is set, BIU_CMD holds CREQ (the cycle type)

BIU_ADDR: holds the address.

On CPU initiated read transactions addressed to the PCI bridge or the PCI bus, this error indicates a PCI-related error occurred. (No error interrupt will be issued since the CPU received the error status directly.)  CPU write transactions to the PCI are always acknowledged as okay (write and run feature).  If there is a write problem, it will be reported later through an interrupt.

  Return to the CPU error detection window


I-stream Parity Error

The 128-bit data bus to and from the CPU is protected by four even parity bits (one for each longword).  When the 21064A receives external I-stream data with bad parity, the 21064A puts the data into the Icache unchanged and validates the block.  A machine check will be initiated if enabled.

BIU_STAT: FILL_DPERR bit is set, FILL_IRD bit is set

FILL_ADDR [33:5] and BIU_STAT [FILL_QW] give the bad quadword's address

FILL_SYNDROME identifies failing longword(s)

BIU_ADDR, BIU_STAT [6:0] are locked - contents are unpredictable

BC_TAG holds external cache tag probe results, if external cache was enabled

  Return to the CPU error detection window


D-stream Parity Error

The 128-bit data bus to and from the CPU is protected by four even parity bits (one for each longword).  When the 21064A receives external D-stream data with bad parity, the 21064A puts the data into the Dcache unchanged and validates the block.  A machine check will be initiated if enabled.

BIU_STAT: FILL_DPERR bit is set, FILL_IRD bit is clear

FILL_ADDR [33:5] and BIU_STAT [FILL_QW] give the bad quadword's address

FILL_ADDR [4:2] contain PA bits [4:2] of the location which the failing load
instruction attempted to read

FILL_SYNDROME identifies failing longword(s)

BIU_ADDR, BIU_STAT [6:0] are locked - contents are unpredictable

BC_TAG holds external cache tag probe results, if external cache was enabled

  Return to the CPU error detection window


Icache and Dcache Parity Errors

The 21064A supports cache parity for data and tag on both the on-chip Icache and Dcache.  Icache and Dcache errors are non-recoverable.

An Icache parity error will cause C_STAT [IC_ERR] to be set and a machine check will be initiated if enabled.

A Dcache parity error will cause C_STAT [DC_ERR] to be set and a machine check will be initiated if enabled.

  Return to the CPU error detection window


Serial ROM (SROM)

The SROM and the SROM interface to the 21064A do not have error checking capability.  On the AlphaStation 255 the SROM code physically resides in the flashROM


Memory Control Logic Error Detection

The memory control logic provides control for: filling the Bcache, extracting victims on CPU initiated transactions, probing the Bcache on DMAs, and invalidating the Bcache when a DMA write hit occurs.  The memory control logic is capable of detecting the following errors:

Bcache Tag Address Parity Error (bc_TAPErr)

Bcache Tag Control Parity Error (bc_TCPErr)

Nonexistent Memory Error (nxMErr)

When one of the above errors is detected, the memory control logic signals the CPU with Hard Error or the PCI bridge (for DMA operations, in which case the CPU is notified through an interrupt).  Error information is captured by:

Loading the current sysAdr<33:5> into the Error Address Register.

Setting the appropriate bits in the Error and Diagnostic Status Register (EDSR)

If another error occurs when the above registers are locked, the LostErr bit in the EDSR will be set and the error information of the lost error will not be captured.


Bcache Error Detection

The Bcache does not detect errors, but it does furnish information though parity bits to error detection networks in the CPU, memory control, and memory data path.  Parity bits include:

Longword even parity on the data (from memory).

Tag address even parity (written by the memory control logic)

Tag control even parity (written by memory control or CPU)

Keep your cache cool.  Dress the cables properly to let the air flow without blockage.


ROM Error Detection

The ROM section of the system uses checksums to protect the data.  Initially the SROM code, then the DROM code will verify ROM data through checksums.


Memory Data Path Error Detection

The CPU performs its own data checking for CPU initiated transactions.

The memory data path performs error detection for DMA initiated transactions.  When the Bcache or memory is read because of a DMA transaction (DMA read or DMA write masked), the data is checked for parity errors.  If there is a parity error, the data path notifies the PCI bridge.  If the PCI bridge was actually going to transfer the bad word onto the PCI, the CPU will be interrupted and the PCI transaction terminated.

If there is bad parity on data being written to memory during a DMA write, the data path will write the bad data to memory.  If the data is used later, an error will be detected and handled. (This is called write and run.)


Memory Error Detection

The memory SIMMs do not detect errors, but they do furnish information though parity bits to error detection networks in the CPU and memory data path.  The memory SIMMs store longword even parity on the data.  During CPU initiated transactions, parity is typically generated by the CPU (in the case of a write Bcache victim to memory, the parity is from the Bcache).  For DMA write transactions, parity is generated in the PCI world.

If there is bad parity on data being written to memory during a DMA write, the data path will write the bad data to memory.  If the data is used later, an error will be detected and handled. (Basically this means don't worry about the error unless the system is actually going to use the data.)


PCI Bridge Detected Errors

When the PCI Bridge detects errors, the PCI Error Address register (PEAR) logs addresses sent or received on the PCI, and the sysBus Error Address register (SEAR) logs addresses sent or received on the sysBus.  Pick an error and click on it for information about the error and the actions taken as a result of the error.

CPU-Initiated Transaction Errors:

No device error	Target abort errors
Address parity errors	Read data parity errors
Write data parity errors	Retry timeout
DMA-Transaction Errors (DMA transaction errors are flagged by interrupting the CPU):

Address parity error	Read data parity error
Write data parity errors	Memory errors
Uncorrectable data error	Scatter/gather invalid errors
Write uncorrectable errors	Scatter/gather read uncorr. errors
Scatter/gather errors


No Device Error

On an I/O transaction initiated by the PCI bridge, if DEVSEL# is not asserted within 5 cycles, the PCI bridge assumes that no PCI device is going to respond to this transaction.  The following actions are taken:

  The nDev bit in the DCSR is set and the pciCmd field is set appropriately.

  PEAR contains the address sent out at the beginning of the transaction and is locked.

  On writes, intHw0 is asserted to interrupt the CPU.

  On reads, the PCI bridge sends 101=HARD_ERROR on the ioCMD<2:0> lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Target Abort Error

On an I/O transaction initiated by the PCI bridge, if the target device terminates the PCI transaction using target-abort protocol, then:

  DCSR tAbt bit is set and pciCmd set appropriately.

  PEAR is locked.

  On writes,  intHw0 is asserted to interrupt the CPU.

  On reads, the PCI bridge sends 101=HARD_ERROR on the ioCMD<2:0> lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Address Parity Error
Address Parity Errors

On I/O transactions, there is no way for the PCI bridge to determine that an address parity error occurred because the PCI bridge has no way to monitor the PCI Bus SERR signal.  (PERR is not used to convey address parity error information.)  Therefore the PCI bridge can take no action, however, the ISA bridge will assert SERR and send the CPU a non-maskable interrupt (NMI) if there is an address parity error.

  Return to the PCI bridge error detection window


Read Data Parity Error
Read Data Parity Errors

On I/O read transactions initiated by the PCI bridge chip, if the parity of the incoming data (PCI AD lines), the byte enables driven by the PCI bridge, and the parity bit (PAR) is not even, a read data parity error has occurred.  Actions taken are:

  Transaction continues normally.

  PCI bridge asserts PERR# on the PCI.

  iOPE bit set in the DCSR and ioCmd set appropriately.

  PEAR is locked. (If an error occurs on both longwords of a QW transactions, then lost is set.)

  HARD_ERROR returned to CPU.

  Return to the PCI bridge error detection window


Write Data Parity Error

On an I/O write transaction initiated by the PCI bridge, if PERR is asserted by the slave device for any longword of data, a write data parity error has occurred.  The following actions are taken:

  Transaction continues normally.

  iOPE bit set in the DCSR and ioCmd set appropriately.

  PEAR is locked. (If an error occurs on more than 1 longword of a single-write burst, then lost is set.)

  intHw0 is asserted to interrupt the CPU.

  Return to the PCI bridge error detection window


Retry Timeout

On an I/O transaction initiated by the PCI bridge, if the retry timeout overflows (this happens when the PCI bridge has been retried 2 to the 24th times by the target), then:

  The PCI bridge does not retry the transaction.

  ioRT bit in DCSR is set and pci_Cmd is set appropriately.

  PEAR is locked.

  intHw0 is asserted to interrupt the CPU.

  On reads, HARD_ERROR is sent to CPU on ioCmd lines to end the sysBus transaction.

  Return to the PCI bridge error detection window


Address Parity error (DMA)

On any DMA (PCI-initiated) transaction address phase, if the parity of the incoming address (PCI AD), command (C/BE),and parity (PAR) is not even, an address parity error occurred.

The PCI bridge will not respond to the transaction. ( This could be a bad command or address.) (PERR is not asserted because it is intended for data-parity errors on the PCI.)

  Return to the PCI bridge error detection window


Read Data Parity Error (DMA)

On a DMA read transaction (data phase), if there is a parity error it might be detected by the PCI master device.  Even if the device asserts PERR and the PCI bridge takes no action, it is the master's responsibility to handle the error.

  Return to the PCI bridge error detection window


Write Data Parity Error (DMA)
Write Date Parity Error (DMA)

On any DMA write transaction (data phase), if the parity of the incoming data (PCI AD), byte enables (C/BE), and the parity bit (PAR) is not even, a data parity error occurred.  The following actions occur:

  PCI bridge asserts PERR for one cycle on the PCI two cycles after the data was on the bus.

  dDPE bit in DCSR is set.

  PEAR is locked.

  intHw0 is asserted.

  The write will continue normally on the PCI.

  That particular cache line entry will not be written to memory.

  Return to the PCI bridge error detection window


Memory Error (DMA)

On a DMA transaction, if the memory controller logic detects an error (nxm, tag address parity, or tag control parity), it will log the address and specific error bit and terminate the sysBus transaction by signaling a DMA cycle error on ioAck<1:0>.

  mErr bit is set.

  SEAR is locked (contains the address that caused the memory error).

  intHw0 is asserted.

  On reads, the PCI bridge terminates the PCI transaction using the target-abort protocol.

  On writes, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Read Uncorrectable Data Error (DMA)

On a DMA read transaction, if there is a parity error in memory (or cache), the data path chips will inform the PCI bridge chip over the epiData bus.

If and when this longword is sent to the PCI bridge, along with the data on the epiData bus, epiBEnErr<0> will contain information whether this longword had an uncorrectable error or not. If the longword was going to be transferred on the PCI:

  intHw0 is asserted.

  uMRD bit in the DCSR is set.

  SEAR is locked

  If the bad data is requested by the PCI, the PCI bridge terminates the PCI transaction using the target-abort mechanism.

  Return to the PCI bridge error detection window


Scatter/Gather Entry Invalid Error

On scatter/gather mapped DMA transactions, the scatter/gather entry being accessed might be invalid.  The actual write to or read from memory will not occur.  The following actions are taken:

  iPTL bit set in DCSR

  PEAR is locked.

  intHw0 is asserted

  On reads, the transaction will terminate on the PCI with target-abort protocol.

  On writes, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Write Uncorrectable Data Error (DMA)
Write Uncorrectable Data Error

If a DMA write is not a full hexaword, the memory controller logic performs a read-modify-write.  If an error is detected on the read from memory before the write is done, the PCI bridge does not perform any action.  The data path core logic will proceed with the merge, but write incorrect parity back into memory.  When this location is read from later, an error will be detected.

  Return to the PCI bridge error detection window


Scatter/Gather Read Uncorrectable Error (DMA)
Scatter/Gather Read Uncorrectable Error

Just as in DMA read data transactions, if an uncorrectable data error (parity error) occurs when accessing a scatter/gather map entry in memory or Bcache, the PCI bridge is notified of the error when the longword is sent to it from the data path.  The following actions are taken:

  The uMRD bit is set in the DCSR

  The address is logged in the SEAR

  intHw0 is asserted.

  If the scatter/gather read was for a DMA read, the PCI bridge will terminate the PCI transaction with target-abort protocol.

  If the scatter/gather read was for a DMA write, the PCI bridge dismisses the write buffer entry (single cache line).  Note that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


Scatter/Gather Memory Error (DMA)

On a DMA transaction, if the memory controller detects an error (nxm, tagape, or tagcpe) during a scatter/gather read transaction, it will terminate the sysBus transaction.  The memory controller will log the address and specific error bit, and terminate the sysBus by signaling a DMA cycle error on ioCAck<1:0>. Actions are:

  mErr bit in DCSR set.

  SEAR is locked.

  intHw0 asserted.

  If the scatter/gather read was for a DMA read, the PCI bridge terminates the PCI using target-abort.

  If the scatter/gather read was for a DMA write, the PCI bridge dismisses the write buffer entry (single cache line).  Notice that if a single PCI write burst crossed a cache line boundary and therefore filled two write buffer entries (two cache lines), each entry is handled separately on the sysBus.

  Return to the PCI bridge error detection window


PCI Bus Error Detection

Not all PCI devices are required to detect and report parity errors, but all are required to generate parity on all of their transactions. Some do this more successfully then others.  See Disabling PCI Parity.

During the address phase, the PAR bit provides even parity for AD [31:0} and C/BE[3:0] regardless of whether or not all the lines carry meaningful information.

Master devices drive PAR for the address and data phases on write transactions. Target devices drive PAR during the data phase of read transactions.

The PCI contains PERR and SERR to signal errors.  PERR reports data parity errors for all transactions except special cycle commands.  PERR can only be driven by one device at a time.  Targets signal data parity errors back to the master using PERR.

SERR reports address parity errors and data parity errors on special cycles.  It is a wire-OR'd signal that can be driven by multiple devices at any one time.  SERR will be sent to the CPU as an NMI.


ISA Bus Error Detection

The ISA bus uses I/O Channel Check (IOCHK) to signal that some ISA device detected a parity error on the ISA bus.  The assertion of IOCHK will cause an NMI to be sent to the CPU.


SCSI Controller Error Detection

The SCSI controller is an NCR 53C810 chip.  On the PCI side, if the SCSI controller detects an address parity error, it asserts SERR which results in a non-maskable interrupt (NMI).

On the SCSI bus side, if the controller detects a parity error while receiving or sending SCSI data, and the appropriate interrupt enable bits in the controller are set, an interrupt will be asserted.


Ethernet LAN Controller Error Detection

The Ethernet LAN Controller (DECchip 21040) is mounted on the motherboard.  When a data parity error on the PCI bus is detected, the controller asserts PERR.  When the controller detects a PCI address parity error, SERR is asserted.

Errors on the attachment unit interface (AUI) side are typically handled by interrupting the CPU (for example, a link fail occurred in the twisted pair lines).

The rear of the motherboard contains two LEDs (visible from the rear of the system).  One is asserted for at least 300 milliseconds when LinkPass is detected.  The other asserts for at least 300 milliseconds when any activity is detected on the network.


Analyze a Machine Check
Analyzing Machine Checks


Digital AlphaStation 255
Analyzing Machine Checks

Here is an approach to analyzing a memory-related machine check.

1.  Locate the machine check stackframe.  The frame may appear in different ways depending on the error reporting tool used (for example, uerf, DECevent, ERF, or a console dump) and the format selected.   The first longword of the frame contains the frame's byte count, 2E8, although not all operating systems display it.  On OpenVMS systems, look for 000002E8 to locate the beginning of the frame.

2.  Identify the machine check ID/mchk_code.  The ID is offset by 0x10 bytes from start of the stackframe.  For example, an ID of 0x84 would indicate a hardware error.

3.  Check the BIU_STAT register as shown below:

For this example, assume that BIU_STAT contains 00000C40.

BIU_STAT<13:12>=0	Quadword within the requested hexaword that caused the error.
BIU_STAT<11>=1	Error occurred during an Icache fill (If during a Dcache fill, <11>=0).
BIU_STAT<10>=1	There was a data parity error during a fill operation.
BIU_STAT<6:4>=4	A read block operation was being performed.
4.  Since the error occurred during a fill operation(<10>=1), you need to determine if the Icache fill data was coming from the Bcache or the SIMMs.  Examine the BC_TAG register bit <0>.

For this example, assume that BC_TAG contains 00401A14.

BC_TAG<0>=0	Bcache had a miss. A miss indicates the data was coming from main memory (SIMMs)
Now we know that quadword 0 contains a parity error from the memory SIMMs.

5.  Check the FILL_SYNDROME register.

Assume that FILL_SYNDROME contains 00000080.

FILL_SYNDROME<00>=1	Indicates the low longword was corrupted.
FILL_SYNDROME<07>=1	Indicates the high longword was corrupted.

There is a little more work to do before the actual failing SIMM is identified.  The bank sizes and the address being read must be determined.

Click here to see the SIMM isolation process.

If BIU_STAT<10> was clear (zero - the error did not occur during a fill operation), check the following bits in the BIU_STAT register:

BIU_STAT<7>=1	A hard error occurred while a bit in BIU_STAT<3:0> was already set.
BIU_STAT<3>=1	Bcache tag control parity error.
BIU_STAT<2>=1	Bcache tag parity error.
BIU_STAT<1>=1	Soft error (correctable).
BIU_STAT<0>=1	Hard error (uncorrectable).
For the above errors, look at BIU_STAT<6:4> to determine the cycle type.

6.  If you did not see any indications of errors in the above steps, check the EDSR register and the DCSR register.


Failing SIMM Isolation


Digital AlphaStation 255
Failing SIMM Isolation

If a parity error occurred during a primary cache fill operation, FILL_DPERR should be set (BIU_STAT<10>=1), and Bcache hit is clear (BC_TAG<0>=0).  To isolate the suspect SIMM, you must gather the following information:

1.	If FILL_IRD =1 (BIU_STAT<11>), then record FILL_ADDR<33:05>	Physical address of the 32-byte cache block that the CPU was attempting to read when the error occurred (<4:2> are unpredictable).
	If FILL_IRD =0 (BIU_STAT<11>), then record FILL_ADDR<33:02>.	Physical address generated by the load instruction that triggered the cache fill.
2.	Record FILL_QW (BIU_STAT<13:12>).  This represents physical address <4:3>.	When FILL_DPERR is set, this field indicates the quadword within the hexaword fill block that caused the error.  Use with FILL_ADDR<33:05> to get the complete address of the failing quadword.  In this example, FILL_QW=0.
3.	Determine the system's memory configuration.  Using the SRM console, issue a SHOW MEMORY command.  For AlphaBIOS, go to AlphaBIOS Setup and select Display System Configuration.  Select Memory Configuration.	The SHOW MEMORY command will display the memory configuration.  For example, >>>show memory 64 Meg of System Memory Bank 0 = 32 MB starting at 0x2000000 Bank 1 = 32 MB starting at 0x0 Flash ROM0 Mfr - AMD
4.	Compare the failing address with the memory configuration to identify the failing bank. Now that we know which bank is failing, the next step is to identify which SIMM in the bank is bad.	Using the information from step 3, if the failing address was 0x2B7BF8, that address would be located in bank 1, quadword 0.  Click here to see the AlphaStation 255 logical bank layout.
5.	Use the FILL_SYNDROME register to identify which SIMM in a bank is failing.
	FILL_SYNDROME<0>=1	The parity error is in the low longword (<31:00>) of the failing quadword.
	FILL_SYNDROME<7>=1	The parity error is in the high longword (<63:32>) of the failing quadword.
6.	Assuming that FILL_SYNDROME<7>=1, then the high longword SIMM in quadword 0, Bank 1 is suspect.	You have now isolated the failing SIMM.  Reseat or replace the SIMM in connector J11.


Memory Bank Layout


Disabling PCI Parity Checking


Digital AlphaStation 255
Disabling PCI Parity Checking

Digital Equipment systems are engineered to protect the customer's data.  Parity protection is one method to help accomplish this.  In the PC market, parity protection is relatively rare.  Even in the new world of PCI options, parity is not consistently being implemented.  In fact, there are cases in which PCI devices have a parity-generating scheme in which the parity is incorrect.  The device functions properly as long as parity is not checked.

You might find yourself working on a system with one of these parity-challenged PCI devices.  Your customer might not appreciate the finer points of data security when the bad parity causes system problems.  In appreciation of this, the SRM and AlphaBIOS firmware have an option that allows you to turn off PCI parity checking.  This is not a step to take lightly, however.

In the AlphaBIOS firmware, the PCI parity-checking option is located in the Advanced CMOS Setup screen.  You can reach it by taking the following path:

1.	From the Boot screen, press F2 to enter AlphaBIOS setup.
2.	From the AlphaBIOS Setup, select CMOS Setup....
3.	At the CMOS Setup screen, press F6.
4.	Choose the appropriate setting.

In the SRM console, you can control the PCI parity checking with the set command. For example: >>>set pci_parity off.  See the list of environment variables for more details.


Non-Maskable Interrupts (NMI)

The non-maskable interrupt (NMI) originates on the ISA bridge chip (NCR 82378).  NMI will be asserted for the following conditions:

	SERR#: An address parity error has been detected on the PCI bus by the ISA bridge chip.  The ISA bridge chip takes no action other than reporting the error to the CPU.
	IOCHK#: A parity error has been detected on an expansion module plugged into the ISA bus.


Troubleshooting Tools


Digital AlphaStation 255
Troubleshooting Tools

There are many tools available to assist you with troubleshooting.  Some tools help test and exercise the system, while others gather and format information.

The DEC Verifier and Exerciser Tool (DEC VET) falls into the first category.  DEC VET is an on-line tool for verifying system installations and acceptance.  It is also used to maintain and troubleshoot systems, and perform load and stress tests on single devices, systems, and networks.  There are versions of DEC VET for each operating system.  For more information see the following guides:

DEC Verifier and Exerciser Tool User's Guide for DIGITAL UNIX

DEC Verifier and Exerciser Tool User's Guide for OpenVMS

DEC Verifier and Exerciser Tool User's Guide for Windows NT

Each operating system has a specific mechanism for capturing and logging error information.  To access an operating system error log, click on one of the following buttons:

Windows NT

DIGITAL UNIX

OpenVMS


Accessing the Windows NT Error Log

Windows NT maintains an event log file. The event logging service starts automatically when Windows NT is started. The Event Viewer is used to view and manage the event logs.

Start the Event Viewer by clicking on its icon. The icon is located in the Administrative Tools group in Program Manager. Windows NT uses three logs:

System log	Tracks events logged by Windows NT system components: for example, the failure of a driver to properly load.
Application log	Tracks events logged by applications.
Security log	Tracks changes to the security system and identifies possible security breaches.

Use the Log menu of the Event Viewer to select the log you need to view.

For more information, see the Event Viewer chapter in the Microsoft Windows NT System Guide or use online help.


Accessing the DIGITAL UNIX Error Log

The event report formatter for DIGITAL UNIX is uerf (In the future, DECevent, a new tool, will replace uerf). The syntax of the command is:

 /usr/sbin/uerf [ options ... ]

The uerf command uses the uerf.bin, uerf.hlp, and uerf.err data files.  The uerf.bin file is the event information database. The uerf.hlp file is the help file. The uerf.err file is the event message file.  The uerf command expects to find the data files in the /usr/sbin directory.

By default, the uerf command outputs the contents of the event log file specified by the *.* entry in the /etc/binlog.conf configuration file.  To report on any other event log file or if there is no *.* entry, you must use the uerf command with the -f option.

  Click here to see a few command examples.

Note: For further information, see the uerf Man pages. (Type "man uerf" at the prompt.)


Digital UNIX Error Log Command Examples

DIGITAL UNIX Error Log EXAMPLE Commands

The following example produces a report containing all event events, excluding logged operating-system events and operator and maintenance-class events:

uerf -O -x -c oper,maint

The following example produces an event report from the /usr/adm/binary.errlog.old file:

uerf -f /usr/adm/binary.errlog.old

The following examples produce event reports for the specified record codes:

uerf -r 100,102

uerf -r 100-109

The following example produces a report of all the events that occurred between 10:47 a.m. on April 13, 1986 and 5:30 p.m. on April 20, 1986:

uerf -t s:13-apr-1986,10:47:00 e:20-apr-1986,17:30:00

The following example produces an event report of the events that occurred on the current day and year, starting at 1:20 p.m. and ending at the current time:

uerf -t s:13:20

The following example produces a report of all logged events and displays it in reverse chronological order, starting with the current date and time:

uerf -R


Accessing the OpenVMS Error Log

Access the OpenVMS Errorlog Report Formatter (ERF) with the ANALYZE/ERROR_LOG command (In the future, DECevent, a new tool, will replace ERF). The syntax is:

ANALYZE/ERROR_LOG [filespec[,...]]

For more information, see the VMS Error Log Utility Reference Manual.

EXAMPLES

The following example will use all the defaults:

$ ANALYZE/ERROR_LOG

The next example will limit the entry range generated from the file ERRLOG.SYS to entries from 1 to 18:

$ ANALYZE/ERROR_LOG/ENTRY=(START:1,END:18) ERRLOG.SYS

This example shows how to exclude a given class of event information (disk information, in this case):

$ ANALYZE/ERROR_LOG/EXCLUDE=(DISK)

The following example will furnish a report containing only disk-related information:

$ ANALYZE/ERROR_LOG/INCLUDE=(DISK)


FRU Replacement

AlphaStation 255 FRU Replacement Menu

Removing the Top and Side Covers

Memory SIMMs

Storage Options

ISA and PCI Options

Riser Card

Media Access Unit (MAU)

Battery

Motherboard

Speaker

Power Supply

System Unit Fan

CAUTION: Remove the AC power cord and follow ESD procedures when working on the AlphaStation 255 System.


Removing the Top Cover

Digital AlphaStation 255 FRU Replacement

Opening the Enclosure

To open the Digital AlphaStation 255 enclosure, follow these steps:
1. Turn off the system.
2. Turn off any external peripheral devices.
3. Use the key to unlock the cover (1).
4. Loosen the thumbscrew fastener (2).
5. Slide the top cover (3) back and upwards to remove it.
6. Release the side cover latch (4).
7. Slide the side cover (5) back and outward to remove it.


Memory SIMM Removal and Replacement

Digital AlphaStation 255 FRU Replacement

Memory SIMM Removal and Replacement

You may have to remove other SIMMs to gain access to the bad one.  To remove a SIMM:
1. Release the two clips (1).
2. Tilt the SIMM toward the power supply and lift the SIMM out of its socket.

To replace a SIMM:
1. Make sure the notch (3) is aligned with the protrusion in the bottom of the socket.
2. Insert the SIMM into its socket at an angle (4).
3. Tilt the SIMM upward (2) away from the power supply until both clips (1) engage the SIMM.

HINT:  Access to the SIMMs is sometimes improved by removing the floppy drive bracket.

  Click here for memory configuration guidelines.

  Click here for 33-bit SIMM information.


Storage Options Replacement

Digital AlphaStation 255 FRU Replacement

Storage Options Replacement

Click on the bay area containing the device that you need to replace.


Inside Storage Bay Option Replacement
Inside Storage Bay


Inside Storage Bay

The inside storage bay may contain two 3.5-inch, 1-inch high devices.  The upper position is front-accessible, the lower position is not.  To replace an inner-bay option, follow these steps:

1.	Power off the system and disconnect the AC power cables.
2.	Remove the top cover.
3.	Remove the drive bay bracket assembly by squeezing the two tabs (1), while moving it backwards and lifting it up.  Set the bracket on the power supply.
4.	Remove the cables from the faulty drive.
5.	Remove the upper drive (1) from the bracket by removing the screws (2) and spreading the tabs (3).  The floppy drive includes a shield (4).  The lower drive mounting screws are accessible after the upper drive is removed.
6.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
7.	Insert the replacement drive into the bracket and fasten it with the mounting screws.
8.	Connect the cables.
9.	Place the drive bracket back into the system unit while carefully guiding the locator pins (1) and checking the cables.  Make sure the bracket spring arms (2) snap in place to secure the bracket.
10.	Replace the top cover.
11.	Connect the AC power and turn on the system.


Inside Bay Removal


Removing Drives from the Inside Bracket


Inside Bay Drive Bracket Installation


Outside Storage Bay Option Replacement
 Outside Storage Bay


Outside Storage Bay

The outside storage bay accommodates a CD-ROM drive in the upper section and 3.5-inch devices in the lower, non accessible section (two 1-inch or one 1-inch and one 1.6-inch drives).  Due to thermal restrictions, the system does not support more than two hard disks internally.  If there is a hard disk installed in the inside bay, then only one hard disk can be installed in the outside bay.  To replace drives in the outside bay, follow these steps:

1.	Turn off the system and disconnect the AC power cord.
2.	Unlock and remove the top cover.
3.	Remove the CD-ROM drive bracket (outside bay upper position) by removing the safety pin and pressing the tray release tab (1) and sliding the CD-ROM drive bracket (2) backwards.  You can rest the bracket on the power supply.  If you removed the CD-ROM to access the lower storage section, proceed to Step 8.
4.	If you are replacing the CD-ROM drive, remove the power, SCSI and audio cables, and the four mounting screws.
5.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
6.	Mount the replacement CD-ROM drive in the bracket.
7.	Connect the SCSI, power, and audio cables to the drive.  Proceed to Step 14.
8.	Remove the lower section drive tray by pressing the tray release tab (1) and sliding the tray (2) backwards.
9.	Disconnect the SCSI and power cables and remove the faulty drive from the drive tray bracket  The tray can hold two 1-inch drives (1), or one 1.6-inch drive (2).
10.	Check the configuration jumpers of the replacement drive.  (For address, termination, and so forth, refer to the drive manual.)
11.	Mount the replacement drive in the bracket.
12.	Connect the SCSI and power cables to the drive.
13.	Replace the drive tray bracket into the storage bay.  Guide the bracket into the tabs (1). Slide forward until it clicks in place.
14.	Replace the CD-ROM tray.  Set the tray on rail (2) and slide forward while engaging notch (1) until the tray clicks in place.
15.	Replace the system top cover.
16.	Plug in the power and turn on the system.


Outside Bay Upper Section Device Removal


CD-ROM Drive Replacement


Outer Bay Lower Section Device Removal


Outer Bay Lower Bracket Drive Removal


Outer Bay Lower Bracket Installation


CD-ROM Drive Tray Installation


ISA and PCI Option Removal

Digital AlphaStation 255 FRU Replacement

ISA and PCI Option Removal

To remove the ISA and PCI option boards, follow these steps:

1.	Disconnect any cables connected to the option board you are removing.
2.	Remove the screw at the rear end of the option card.
3.	Gently pull out the option card.
4.	Configure the option by checking and setting switches and jumpers according to the option documentation.  If replacement option is ISA-based and set up differently than the original option on Digital UNIX or OpenVMS systems, use the ISA Configuration utility, ICONFIG, to modify the SRM console configuration database.  For DEC EtherWORKS 3 Turbo Plus Ethernet controllers, use the EWRK3_CONFIG utility if you need to change the default settings on the replacement board.
5.	Plug the replacement card into the appropriate slot.  Make sure the card is fully seated.
6.	Fasten the card in with the mounting screw.
7.	Connect previously removed cables to the replacement card.


Expansion Board R and R


Riser Card (and Ethernet Controller) Replacement

Digital AlphaStation 255 FRU Replacement

Riser Card Replacement

The riser card contains PCI and ISA expansion slots.

To replace the riser card, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover and side panel.
3.	Remove any cables from ISA and PCI options installed in the riser card.
4.	Remove the ISA and PCI options from the riser card.
5.	Remove the two riser card mounting screws.
6.	Gently pull the riser card out of its slot in the motherboard.
7.	Gently insert the new riser card into the motherboard.
8.	Fasten the riser card with the mounting screws.
	Re-insert and hook up the previously removed ISA and PCI options.
9.	Replace the side panel and top cover.
10.	Hook up the AC power cord and power on the system.


Riser Card


Media Access Unit (MAU) Replacement

Digital AlphaStation 255 FRU Replacement

Media Access Unit (MAU) Replacement

The optional MAU takes the attachment unit interface (AUI) signals from the Ethernet LAN controller (DECchip 21040) and makes a ThinWire network connection available on the rear panel.

Note:  The MAU ribbon cable connects to the motherboard at J19, (1) in the figure.  Early systems use a missing pin at J19 for keying.  Later systems have a shroud (with a key slot) on J19 and no missing pin.  The cables with the later systems are labeled to identify the missing pin side of the cable.  This is done for cases where the new cable is used with the early (shroudless) systems.  The red stripe should be at the pin 1 end of the connector.

To replace the MAU, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover.
3.	Remove the ThinWire cable from MAU connector on the rear of the system.
4.	Remove the MAU mounting screw from the rear panel.
5.	Lift the MAU card out of the system and disconnect the ribbon cable from CN1 connector on the MAU.
6.	Connect the ribbon cable to the new MAU card.
7.	Position the MAU and fasten it with the mounting screw.
8.	Re-connect the network (ThinWire).
9.	Replace the top cover.
10.	Connect the AC cord and power on the system.


MAU


Replacing the Battery

Digital AlphaStation 255 FRU Replacement

Replacing the Battery

The battery supplies power to the real time clock.  Replace the battery with a Panasonic BR2032, CR2032, or equivalent.  After replacing the battery, you should verify the configuration and setup data using the AlphaBIOS or SRM console. (Some firmware data resides in the battery backed-up RAM within the real time clock.)

Warning: There is a danger of explosion if battery is incorrectly replaced.  Replace only with the same or equivalent type recommended by the manufacturer,  Discard used batteries according to the manufacturer's instructions.

To replace the battery, follow these steps:

1.	Power off the system and remove the AC power cord.
2.	Remove the top cover.
3.	Gently pry the old battery from the battery holder.  Be very cautious not to bend the battery hold-down spring.  Intermittent contact could result from a bent spring.
4.	Insert the new battery, positive side up, into the holder.
5.	Replace the top cover.
6.	Connect the AC cord and power the system on.
7.	Re-enter the configuration data.


Battery Holder


Motherboard Replacement

Digital AlphaStation 255 FRU Replacement

Motherboard Replacement

NOTE: The motherboard contains the environment variable data, time of year (TOY) logic, and the Ethernet ID ROM.  When the motherboard is replaced, the information it contains is lost and must be reentered in the replacement motherboard.  Keeping records of the configuration (IRQs, DMAs, I/O addresses, and so forth) will facilitate getting the system back into use.

To replace the motherboard, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cords at the rear of the PC.
3.	At the unit's rear, disconnect the cables for the:   Keyboard.   Mouse.   Serial line units (2).   Printer.   External SCSI bus.   PCI or ISA options.
4.	Remove the top cover and side panel.
5.	Remove any PCI and ISA options.
6.	Remove the riser board.
7.	Remove the EID ROM (1) and transfer it to the new motherboard.
8.	Disconnect cables plugged into the main logic board (MLB).
9.	Remove the inside drive bracket assembly (set it on the power supply).
10.	Remove the motherboard-mounting screws.
11.	Gently slide the motherboard out the side of the enclosure.
12.	Before installing the new motherboard, check that the switches are configured properly.
13.	Reassemble by performing the steps in reverse order (10 to 1).


Motherboard


Speaker Replacement

Digital AlphaStation 255 FRU Replacement

Speaker / LED Front Panel Assembly Replacement

To replace the speaker/LED front panel assembly, follow these steps:

1.	Turn off the system and remove the power cord.
2.	Remove the top cover.
3.	Remove the CD-ROM drive tray and the hard drive tray from the outside storage area.  Rest them on the power supply.
4.	Disconnect the speaker cable from J7 on the motherboard.
5.	Disconnect the front panel cable from J2 on the motherboard.
6.	Push down on the two tabs on the top of the speaker/LED front panel assembly, while pulling the assembly out.
7.	Install the replacement speaker/LED front panel assembly by aligning the two guide tabs, then snapping the assembly in place.
8.	Connect the front panel cable to J2 on the motherboard.
9.	Connect the speaker cable to J7 on the motherboard.
10.	Mount the hard drive tray, then the CD-ROM drive tray into the outer storage area.
11.	Replace the top cover.
12.	Connect the power cord and power on the system.


Speaker


Power Supply Replacement

Digital AlphaStation 255 FRU Replacement

Power Supply Replacement

The AlphaStation 255 has a 210W power supply.

To replace the power supply, follow these steps:

1.	Power off the system.
2.	Disconnect the AC power cord at the rear of the system.
3.	Remove the top cover.
4.	Disconnect the power supply cables going to:   Motherboard (4).   Outer storage-bay drives.   Inner storage-bay drives.
5.	Remove the power supply mounting screws (6).
6.	Carefully lift the power supply out of the enclosure while ensuring that the cables do not get hung up.
7.	Install the replacement power supply by repeating the above steps in reverse order.


Power Supply Location


System Fan Replacement

Digital AlphaStation 255 FRU Replacement

System Unit Fan Replacement

To replace the system unit fan, follow these steps:

1.	Turn off the power and remove the AC cord.
2.	Remove the top cover and the side panel.
3.	Remove the fan housing and pipe assembly by pressing in on the two snap clips, while pulling the housing to the rear.
4.	Disconnect the fan power cable from J1 on the motherboard.
5.	Connect the replacement fan's power cable to J1 on the motherboard.
6.	Mount the fan housing back into the enclosure by first inserting the fan housing into the two tabs at the bottom, and then snapping the housing in place.  Keep an eye on the cables while you are doing this.
7.	Replace the side panel and top cover.
8.	Connect the AC cord and power on the system.


System Unit Fan


Part Numbers

Digital AlphaStation 255

Part Numbers

Field Replaceable Units (FRUs)

AlphaStation 255 Kernel	PB47H-AA
Bezel assembly	70-32036-01
CD-ROM, 600 MB	RRD45-AB
CD-ROM drive tray	70-32021-01
Chassis assembly (with fan, without power supply)	70-32022-02
Cover assembly	70-32026-01
Cover assembly, top	70-32035-01
Ethernet ThinWire Media Access Unit (MAU)	30-46726-01
Fan, 92mm (Delta)	DFB0912H
Fan guard	74-50909-01
Fan pipe	74-51163-01
Floppy diskette drive (3.5 in 1.44 MB)	RX23L-AB
Floppy drive tray	74-50610-01
Floppy shield	74-50611-01
Hard drive tray	74-50628-01
Headset, stereophonic with 8 feet of cord	30-43276-01
LED and reset assembly (front panel) (includes cable)	70-32779-01
Lock assembly with master key	12-37977-03
Lock pawl	74-50613-01
Media adapter unit (MAU)	30-46726-01
Memory (one 8 MB x 33 bit, 70ns SIMM)	54-23639-BA
Memory (one 16 MB x 33 bit, 70ns SIMM)	54-23170-EA
Microphone, Voice Commander	30-43275-01
Motherboard, 233 MHz	54-24631-01
Motherboard, 300 MHz	54-24631-02
Mouse, 3-button, PS/2 compatible	30-46117-02
Panel, right	74-50598-01
Panel assembly, left	70-32037-01
Power supply (210 Watts)	30-46120-02
Riser card (2 PCI, 1 PCI/ISA combination, 1 ISA slots)	54-24321-01
SCSI terminator, internal SCSI bus	12-36929-03
SCSI terminator, external SCSI bus	12-41667-01
Speaker assembly	70-32774-01

Digital AlphaStation 255 Cable Part Numbers

CD-Audio - 4 conductor wire harness.	17-04272-01
Floppy - Motherboard to floppy drive, 34-conductor, slit flat ribbon with two FDD connectors	17-04314-01
MAU - 16 conductor cable from motherboard to MAU.	17-04365-01
SCSI (internal) - Motherboard to internal SCSI drives, 50-conductor, slit flat ribbon daisy-chained with three drive connectors	17-04313-01


Connector Pinouts

Digital AlphaStation 255

Connector Pinouts


Keyboard Port Pinouts


Digital AlphaStation 255
Keyboard Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

1	KBData
2	N/C
3	Ground
4	+5 VDC
5	KBClock
6	N/C


Mouse Port Pinouts


Digital AlphaStation 255
Mouse Port Pinouts

Miniature, circular DIN, 6-position, receptacle

Pin	Signal

1	MSData
2	N/C
3	Ground
4	+5 VDC
5	MSClock
6	N/C


External SCSI
External SCSI Port Pinouts


Digital AlphaStation 255
External SCSI Port Pinouts

50-pin high-density Honda-type receptacle

Pin	Signal		Pin	Signal/Meaning
1	Ground		26	DB(0) Data bus line 0
2	Ground		27	DB(1) Data bus line 1
3	Ground		28	DB(2) Data bus line 2
4	Ground		29	DB(3) Data bus line 3
5	Ground		30	DB(4) Data bus line 4
6	Ground		31	DB(5) Data bus line 5
7	Ground		32	DB(6) Data bus line 6
8	Ground		33	DB(7) Data bus line 7
9	Ground		34	DB(P) Data bus parity
10	Ground		35	Ground
11	Ground		36	Ground
12	Reserved		37	Reserved
13	Open		38	TERMPWR Terminator power
14	Reserved		39	Reserved
15	Ground		40	Ground
16	Ground		41	ATN Attention
17	Ground		42	Ground
18	Ground		43	BSY Busy
19	Ground		44	ACK Acknowledge
20	Ground		45	RST Reset
21	Ground		46	MSG Message
22	Ground		47	SEL Select
23	Ground		48	C/D Control/Data
24	Ground		49	REQ Request
25	Ground		50	I/O Input/Output


Communication Ports Pinouts


Digital AlphaStation 255
Communication Ports Pinouts

9-Pin Sub D, plug, DB9 (Both serial line unit connectors have the same pinouts.)

Pin	Signal	Meaning
1 2 3 4 5 6 7 8 9	DCD RX TX DTR Ground DSR RTS CTS RI	Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal Ground Data Set Ready Request to Send Clear to Send Ring Indicator
The serial line units (COM1 and COM2) support full MODEM control.  The baud rates supported by the serial line units are:

50	75	110	134.5
150	300	600	1200
1800	2000	2400	3600
4800	7200	9600	19200
38400	57600	115200

Refer to the operating system documentation to confirm which baud rates from the preceding list are supported by the operating system.

The name each SLU is recognized by is dependent on the operating system.  For example, an OpenVMS AlphaStation with a graphics head console, defines COM1 as OPA1 and COM2 as TTA0.  If there is not a graphics head (console = serial), then COM1 is OPA0 (COM2 remains as TTA0).


Parallel Port Pinouts
Bi-Directional Parallel Port Pinout


Digital AlphaStation 255
Bi-Directional Parallel Port Pinouts

25-position, Sub D, receptacle, DB25

Pin	Signal	Meaning
1		Strobe
2	PD0	Data bit 0
3	PD1	Data bit 1
4	PD2	Data bit 2
5	PD3	Data bit 3
6	PD4	Data bit 4
7	PD5	Data bit 5
8	PD6	Data bit 6
9	PD7	Data bit 7
10		Acknowledge
11	BUSY	Busy
12	PE	Paper End
13	SLCT	Select
14		Auto line feed
15		Error
16		Initialize printer
17		Select in
18-25	Ground	Ground


Ethernet Twisted-Pair Port Pinouts


Digital AlphaStation 255
Ethernet Twisted-Pair Port Pinouts

RJ45

Pin	Signal	Meaning
1	TPTXD	Transmit data
2	TPTXD	Trasmit data
3	TPRXD	Receive data
4	N/A
5	N/A
6	TPRXD	Receive data


Audio Pinouts
Audio Ports


Digital AlphaStation 255
Audio Ports

3.5 mm jacks

Legend	Connector	Meaning
1	Headphones.	Stereo headphones (600 ohm). When headphones are installed, the internal speaker is muted.  The output can drive small 4-ohm or higher speakers.
2	Microphone	Monaural electret microphone  (2.2 kOhm to 2.5V). A dynamic mike can be used but bias current may cause distortion.
3	Line In	Stereo Line In. 1 V peak-to-peak nominal Input impedance is 10 kohm.


Configuration Switches


Digital AlphaStation 255
Configuration Switches

(D) = Default

Switch    Setting            Function                     Description

1, 2	1           2 OFF     OFF(D) ON       OFF OFF      ON ON        ON	Normal Stop at SROM prompt Boot from floppy Reset RTC and NVRAM	Switches 1 and 2 are the config switches.  An adapter is required to communicate with the SROM code.  To reset the RTC/NVRAM: A. Set 1 and 2 ON. B. Power on system and wait for the console to start. C. Power off system. D. Set 1 and 2 OFF. E. Power on system.
3	OFF (D) ON	Writes enabled Writes disabled  (Do not use)	Switch 2 is the flashROM write protect switch.  It should always be off.
4	OFF ON (D)	Halt interrupt request. Reset.	The front-panel push button can be set to cause either a Reset or a Halt Interrupt Request.
5	OFF (D) ON	Enables TC sound Disables TC sound	Switch 5 controls the timer-counter (TC) circuit.  When OFF, TC sound is enabled directly to the speaker.  This allows TC sounds when no sound driver is installed.  The amplitude of these signals cannot be varied by the user.
6,7,8	6       7       8 ON    ON    ON OFF  ON    ON ON    OFF  ON OFF  OFF  ON ON    ON    OFF OFF  ON    OFF ON    OFF  OFF OFF  OFF  OFF	CPU Clock Rate (MHz) 133 166 200 233 266 300 333 366	Switches 6, 7, and 8 are used to set the CPU clock rate.  You can set the system to run on a slower rate.  However, faster rates require an upgrade which replaces the Interrupt PAL.


Beep Codes

Digital AlphaStation 255

Beep Codes

The AlphaStation 255 can signal problems to you before the video monitor is operational through the use of beep codes.  When certain problems are detected a beep code is sent to the speaker.  Since the speaker is driven from the ISA bridge chip, most of the system must be working to generate the beep codes.

  Beep Codes


Registers
Digital AlphaStation 255 - Registers


Machine Check Types


Machine Check Types

    CPU Errors                                                  PALcode    Machine Check Errors

0x80 0x82 0x84 0x86 0x88 0x8A 0x8C 0x8E 0x90 0x92 0x94 0x96	Tag parity error Tag control error Hardware error Correctable ECC Noncorrectable ECC Unknown error CackSoft error Bugcheck OS bugcheck Dcache parity error Icache parity error C3 tag parity error		0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209	I/O read/write retry timeout DMA data parity error I/O data parity error Slave abort PCI transaction IDSEL not asserted Correctable read error Uncorrectable read error Invalid page table lookup (scatter/gather) Memory cycle error
                                           Core Logic Machine Checks (0x220 PALcode entry)

			0x20A 0x20B 0x20C	Bcache tag address parity error Bcache tag control parity error Nonexistent memory error
                                            SIO Errors (IOCHECK in NMI Status Register) IRQ3

			0x20D	SIO I/O check occurred PCI SERR asserted


PAL Temp Registers

Digital AlphaStation 255 Registers

PAL Temp Registers

Machine Check Frame Offset: + 0x018 through 0x108

There are 31 PAL temp registers of 64-bits each.  The registers are used by the PALcode.


Exception Mask Register

Digital AlphaStation 255 Registers

Exception Mask Register

Machine Check Frame Offset: + 0x128


Instruction Cache CSR (ICCSR)

Digital AlphaStation 255 Registers

Instruction Cache Control and Status Register

Address: IPR Ibox-Index=2, Machine Check Frame Offset: + 0x128

This register contains various CPU I-box hardware enable bits.

Click on the Description button to display the bit fields.


ICCSR Bit Descriptions
ICCSR Register Bit Descriptions

ASN <5:0>	<33:28>R <52:47>W	Address space number.
FPE	<23>R <42>W	If set, floating point is enabled.
MAP	<22>R <41>W	If set, allows super-page I-stream memory mapping of VPC<33:13> directly to physical PC<33:13>.
HWE	<21>R <40>W	If set, allows the five PALRES instructions to be issued in kernel mode.
DI	<20>R <39>W	If set, dual issue is enabled.
BHE	<19>R <38>W	Used with BPE for branch-prediction selection. BPE BHE Prediction 0 X Not taken 1 0 Sign of displacement 1 1 Branch history table
JSE	<18>R <37>W	If set, allows pushing return addresses on the JSR stack.
BPE	<17>R <36>W	Used with BHE for branch prediction selection.  See BHE, bit <19>R for more details.
Pipe	<16>R <35>W	If set, pipeline operation is normal (The pipe will not drain for HW_MTPR, HW_REI, conditional branches, and instructions with R31 as the destination.)
PC MUX1 <2:0>	<15:13>R <34:32>W	Performance counter 1 input selection. Possible selections are: PC MUX1<2:0> Input 000 Dcache misses 001 Icache misses 010 Dual issues 011 Branch mispredicts 100 FP instructions 101 Integer operate 110 Store instructions 111 External events (PERF_CNT_H<1>)
PC MUX0 <3:0>	<12:09>R <11:08>W	Performance counter 0 input selection.  Possible selections are: PC MUX0<3:0> Input 000X Total issues divided by 2 001X Pipeline dry 010X Load instructions 011X Pipeline frozen 100X Branch instructions 1010 PAL mode 1011 Total cycles 110X Total nonissues divided by 2 111X External events (PERF_CNT_H<0>)
PC1	<02>R <00>W	If set, enables a performance counter 1 interrupt request after 256 events are counted.  If clear, the request occurs after 4096 events are counted.
PC0	<01>R <03>W	If set, enables a performance counter 0 interrupt request after 4096 events are counted.  If clear, the request occurs after 65536 events are counted.


Exception Address Register (EXC_ADD)

Digital AlphaStation 255 Registers

Exception Address Register

Address: IPR Ibox, Index=4, Machine Check Frame Offset: + 0x110

The exception address register is used to restart the machine after exceptions or interrupts.

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EXC_ADD Bit Descriptions
EXC_ADD Register Bit Descriptions

PC	<63:2>RW	Address of the instruction that has not completed execution.  This address will be used to return from the exception or interrupt.
PAL	<0>	This bit indicates PAL mode to the hardware.  When clear, the HW_REI instruction executes a jump to native (non-PAL) mode, enabling address translation.


Exception Summary Register (EXC_SUM)

Digital AlphaStation 255 Registers

Exception Summary Register

Address: IPR Ibox, Index=10, Machine Check Frame Offset: + 0x118

This register contains various types of arithmetic traps that have occurred since the last time the register was written to (cleared).  Any write to the EXC_SUM register clears bits <08:02>.

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EXC_SUM Bit Descriptions
EXC_SUM Register Bit Descriptions

MSK	<33>	Write mask IPR window.
IOV	<08>	If set, this bit indicates an F-box convert to integer overflow or integer arithmetic overflow.
INE	<07>	If set, this bit indicates a floating inexact error.
UNF	<06>	If set, this bit indicates a floating point underflow.
FOV	<05>	If set, this bit indicates a floating point overflow.
DZE	<04>	If set, this bit indicates a divide by zero.
INV	<03>	If set, this bit indicates an invalid operation.
SWC	<02>	If set, this bit indicates that software completion is possible.


Hardware Interrupt Enable Register (HIER)

Digital AlphaStation 255 Registers

Hardware Interrupt Enable Register

Address: IPR Ibox, Index=16, Machine Check Frame Offset: + 0x138

The hardware interrupt enable register enables interrupts from the corresponding bits of the hardware interrupt request register (HIRR).

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HIER Bit Descriptions
HIER Register Bit Descriptions

UAE	<32>R
SAE	<31>R
EAE	<30>R
KAE	<29>R
SIRR<15:01>	<28:14>R	Corresponds to software interrupt requests 15 to 1.
SLE	<13>R <32>W	When set, this bit enables interrupts from the serial line.
HIER<02:00>	<12:10>R <11:09>W
PC0	<09>R <08>W	When set, this bit enables interrupts from performance counter 0.
PC1	<08>R <15>W	When set, this bit enables interrupts from performance counter 1.
HIER<05:03>	<07:05>R <14:12>W
CRE	<04>R <02>W	When set, this bit enables interrupts due to correctable read errors.


Memory Management CSR (MM_CSR)

Digital AlphaStation 255 Registers

Memory Management Control and Status Register

Address: IPR Abox, Index=4, Machine Check Frame Offset: + 0x148

The memory management control and status register is used latch and save information about data stream faults.

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MM_CSR Bit Descriptions
MM_CSR Register Bit Descriptions

OPCODE	<14:09>R	This field contains the opcode of the faulting instruction.
RA	<08:04>R	The Ra field of the faulting instruction.
FOW	<03>R	This bit is set if the reference was a write and the PTE's FOW bit was set.
FOR	<02>R	This bit is set if the reference was a read and the PTE's FOR bit was set.
ACV	<01>R	This bit is set if the reference caused an access violation.
WR	<00>R	This bit is set if a write reference caused the error.


Hardware Interrupt Request Register (HIRR)

Digital AlphaStation 255 Registers

Hardware Interrupt Request Register

Address: IPR Ibox, Index=12, Machine Check Frame Offset: + 0x140

The hardware interrupt request register is a read-only register that provides a record of all currently outstanding interrupt requests and summary bits at the time of a read.

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HIRR Bit Descriptions
HIRR Register Bit Descriptions

USEK ASTRR	<32:29>R
SIRR<15:01>	<28:14>R	Corresponds to software interrupt requests 15 to 1.
SLR	<13>R	Serial line interrupt request.
HIRR<02:00>	<12:10>R	Corresponds to pins IRQ(H)<2:0>
PC0	<09>R	Performance counter 0 interrupt request.
PC1	<08>R	Performance counter 1 interrupt request.
HIRR<05:03>	<07:05>R	Corresponds to pins IRQ(H)<5:3>
CRR	<04>R	Correctable read error interrupt request.
ATR	<03>R	This bit is set if any AST request and corresponding enable is set.  This bit also requires that the processor mode is equal to or higher than the request mode, and that SIER<02> be set.
SWR	<02>R	Set if any software interrupt request and corresponding enable bit is set.
HWR	<01>R	Set if any hardware interrupt request and corresponding enable bit is set.


Data Cache Status Register (DC_STAT)

Digital AlphaStation 255 Registers

Data Cache Status Register

Address: IPR Abox, Index=12, Machine Check Frame Offset: + 0x150

The data cache status register is a read-only register.  When an external parity error is recognized during a primary cache fill operation, the DC_STAT register is locked until the DC_ADDR register is read.

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DC_STAT Bit Descriptions
DC_STAT Register Bit Descriptions

SEO	<14>R	Second error occurred.  Set when an error that normally locks the DC_STAT register occurs while the DC_STAT register is already locked.
STORE	<13>R	This bit indicates the error was caused by a store operation.
LOCK	<12>R	This bit is set to indicate that the error was caused by an LDLL, LDQL, STLC, or STQC instruction.
VAX_FP	<11>R	When INT is clear, this bit is set to indicate that a VAX floating point format load or store caused the error.
LW	<10>R	When set, this bit indicates that the data length of the load or store was a longword.
INT	<09>R	When set, this bit indicates an integer load or store.
RA	<08:04>R	The RA field of the error-causing instruction.
DC_HIT	<03>R	Data cache hit.  The last load or store instruction processed by the A-box hit, if set, or missed if clear the data cache.


DC_ADDR Register

Digital AlphaStation 255 Registers

DC_ADDR Register

Machine Check Frame Offset: + 0x158

The DC_ADDR register is a pseudo-register used for unlocking the DC_STAT register.  When the DC_ADDR register is read, the DC_STAT register is unlocked.


Bus Interface Unit Status Register (BIU_STAT)

Digital AlphaStation 255 Registers

Bus Interface Unit Status Register

Address: IPR Abox, Index=10, Machine Check Frame Offset: + 0x168

The bus interface unit status register is a read-only register.  When the BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR bit is set, the BIU_STAT<6:0> register bits are locked until the BIU_ADDR register is read.

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BIU_STAT Bit Descriptions
BIU_STAT Register Bit Descriptions

FILL_SEO	<14>R	Set when either a primary cache fill operation resulted in an uncorrectable EDC error or a parity error while the FILL_EDC bit was set, or the FILL_DPERR bit was already set.
FILL_QW	<13:12>R	When FILL_DPERR is set, this field identifies the quadword in the hexaword fill block that caused the error.
FILL_IRD	<11>R	If the I-cache was being filled when either the FILL_EDC or FILL_DPERR bit set, this bit is set.  It is clear when the error occurred during a D-cache fill operation.
FILL_DPERR	<10>R	Set if the primary cache fill data from outside the DECchip 21064 contained a parity error.
FILL_EDC	<08>R	Set if the primary cache fill data received from outside the DECchip 21064 contained an EDC error.
BIU_SEO	<07>R	Set when either an external cycle was terminated by the CACK(H) pins indicating HARD_ERROR, or an external cache tag probe encountered bad parity in the tag address RAM or tag control RAM while BIU_HERR, BIU_SERR, BIU_TPERR, or BIU_TCPERR was set.
BIU_CMD	<06:04>R	The cycle type on the cReq_h pins is latched in this field when a BIU_HERR, BIU_SERR, BIU_TPERR, or BIU_TCPERR error occurs.  Cycle types are: 0 0 0 IDLE 0 0 1 BARRIER 0 1 0 FETCH 0 1 1 FETCH_M 1 0 0 READ_BLOCK 1 0 1 WRITE_BLOCK 1 1 0 LDL_L/LDQ_L 1 1 1 STL_C/STQ_C
BIU_TCPERR	<03>R	Backup cache tag control parity error.
BIU_TPERR	<02>R	Backup cache tag parity error.
BIU_SERR	<01>R	Soft error.
BIU_HERR	<00>R	Hard error.


Bus Interface Unit Address Register (BIU_ADDR)

Digital AlphaStation 255 Registers

Bus Interface Unit Address Register

Address: IPR Abox, Index=9, Machine Check Frame Offset: + 0x170

The bus interface unit address register is a read-only register.  It contains the physical address associated with errors reported by BIU_STAT<7:0>.  The BIU_ADDR register's contents are valid when BIU_HERR, BIU_SERR, BC_TPERR, or BC_TCPERR bit are set.  A read of the BIU_ADDR register will unlock both BIU_ADDR and BIU_STAT<7:0>.

If the BIU_CMD field of the BIU_STAT register indicates that the transaction that received the error was READ_BLOCK or load_locked, then BIU_ADDR<4:2> are unpredictable.  If the BIU_CMD contained any other command, then BIU_ADDR<4:2> will contain zeros.


Fill Syndrome Register

Digital AlphaStation 255 Registers

Fill Syndrome Register

Address: IPR Abox, Index=19, Machine Check Frame Offset: + 0x180

The fill syndrome is a 14-bit read-only register.  If the DECchip 2106 is in ECC mode and an ECC error is recognized during a primary cache fill operation, the syndrome bits associated with the bad quadword are locked in this register.  The FILL_SYNDROME register is unlocked when the FILL_ADDR register is read.

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FILL_SYNDROME Bit Descriptions
FILL_SYNDROME Register Bit Descriptions

HI	<13:07>R	Syndrome bits associated with the upper longword of the quadword.  If the DECchip 21064 is in parity mode, <07> indicates which longword in the quadword has bad parity (<13:08> are RAZ in parity mode).
LO	<06:00>R	Syndrome bits associated with the lower longword of the quadword.  If the DECchip 21064 is in parity mode, <00> indicates which longword in the quadword has bad parity (<06:01> are RAZ in parity mode).


Fill Address Register

Digital AlphaStation 255 Registers

Fill Address Register

Address: IPR Abox, Index=13, Machine Check Frame Offset: + 0x188

The fill address register is a read-only register that contains the physical address associated with errors reported by BIU_STAT<14:08>.  Its contents are meaningful only when FILL_ECC or FILL_DPERR is set.  Reading the FILL_ADDR register unlocks FILL_ADDR, BIU_STATS<14:08>, and FILL_SYNDROME.

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FILL_ADDR Bit Descriptions
FILL_ADDR Register Bit Descriptions

ADDRESS	<33:05>R	Address of the 32-byte cache block that the CPU was attempting to read when the error occurred.
ADDRESS	<04:02>	If the FILL_IRD bit in BIU_STAT is clear, indicating the error occurred during a D-stream cache fill, bits FILL_ADDR<04:02> contain physical address bits <04:02> of the load instruction that triggered the cache fill.  If the FILL_IRD bit is set, then FILL_ADDR<04:02> are unpredictable.


Virtual Address Register

Digital AlphaStation 255 Registers

Virtual Address Register

Machine Check Frame Offset: + 0x190

The Virtual Address (VA) register latches the effective VA associated with D-stream faults or DTB misses.  The VA and the MM_CSR are locked against further updates until the software reads the VA register.


Backup Cache Tag Register (BC_TAG)

Digital AlphaStation 255 Registers

Backup Cache Tag Register

Address: IPR Abox, Index=20, Machine Check Frame Offset: + 0x198

The backup cache tag register is a read-only register.  Unless locked, the BC_TAG register is loaded with the results of every backup cache tag probe.  When a tag or tag control parity error or primary fill data error (parity or ECC) occurs, this register is locked against further updates.  The software reads the LSB by using the HW_MFPR instruction.  Every read shifts the contents one position to the right, so a series of reads is needed.  The register is unlocked by using a HW_MTPR to the BC_TAG.

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BC_TAG Bit Descriptions
BC_TAG Register Bit Descriptions

TAG_P	<22>R	Parity bit for the backup cache tag.  Even parity is used.
TAG<33:17>	<21:05>R	The backup cache tag field.
TAGCTL_V	<04>R	The tag valid bit.
TAGCTL_S	<03>R	The shared bit.  When clear, the entry is private.
TAGCTL_D	<02>R	The dirty bit.
TAGCTL_P	<01>R	Parity bit for the tag control bits.  Even parity is used.
HIT	<00>R	Hit.


Error and Diagnostic Status Register (EDSR)

Digital AlphaStation 255 Registers

Error and Diagnostic Status Register

Address: 1 8000 0040, Machine Check Frame Offset: + 0x1A8

The error and diagnostic status register is a read-only register located in the core logic.  When an error occurs, an error bit will be set and the address will be locked in the Error Low and Error High Address Registers.  Any additional errors occurring after the address is locked will cause lostErr to be set.

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EDSR Bit Descriptions
EDSR Register Bit Descriptions

wrPend	<15>R	When write pending is set, it indicates that valid write data is stored in the write buffer.
ldxlLock	<14>R	When LDx_L Locked is set, it indicates that the next STx_C may succeed.  Writing to any CSR or I/O space location clears this lock bit.
pass2	<13>R	Version of the DECchip 21071-CA.  Low indicates pass1, and high indicates pass2.
cReqCause	<08:06>R	This field indicates the cycle request that caused the error.  Depending on the DmaCause CSR, a copy of either the cpuCReq or the ioCmd lines will be placed in this field.  This field is valid only when bc_TAPErr, bc_TCPErr, or nxMErr error is indicated.
vicCause	<05>R	When the victim write caused error bit is set, it indicates that a NXM error was caused by a victim write transaction.  This is only valid when an error is indicated in bc_TAPErr, bc_TCPErr, or nxMErr.
dmaCause	<04>R	When set, this bit indicates that the bc_TAPErr, bc_TCPErr, or nxMErr was caused by a DMA transaction.
nxMErr	<03>RW	When set, the nonexistent memory error indicates that a read or write occurred to an invalid address that did not map to any memory bank, CSR, or I/O quadrant.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
bc_TCPErr	<02>RW	The Bcache tag control parity error bit indicates that a tag probe encountered bad parity in the tag control RAM.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
bc_TAPErr	<01>RW	The Bcache tag address parity error bit indicates that a tag probe encountered bad parity in the tag address RAM.  This bit can be set only when the error address is unlocked.  The bit is cleared by writing a one to it.
lostErr	<00>RW	The multiple-errors bit indicates that an additional error occurred when the error address was already locked.  The bit is cleared by writing a one to it.


Diagnostic Control and Status Register (DCSR)

Digital AlphaStation 255 Registers

Diagnostic Control and Status Register

Address: 1 A000 0000, Machine Check Frame Offset: + 0x208

The diagnostic control and status register provides control of operational and diagnostic modes.  It also reports status and error conditions relating to the PCI interface section of the core logic.

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DCSR Bit Descriptions
DCSR Register Bit Descriptions

pass2	<31>R	Version of the DECchip 21071-DA.  Low indicates pass1 and high indicates pass2.
pCmd	<21:18>R	The pCmd field indicates the PCI cycle type when a PCI-initiated error is logged in the DCSR.  This field is only valid when an iPTL, nDev, tAbt, or iOPE error is set. Value Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate
dByp	<17:16>RW	The disable read bypass field is used to control the ordering of PCI-initiated memory reads with respect to PCI-initiated memory writes.  The modes are: Value Mode 00 Full Bypass 01 Reserved 10 Partial Bypass 11 No Bypass
mErr	<15>RW	Memory error is set when the DECchip 21071-DA receives an error code in the ioCAck<1:0> field in response to a memory access.  The address, sysAdr<33:5>, of this transaction is locked in the SEAR <31:3>.  If another error occurs while the address register is locked, the lost bit will be set.
iPTL	<14>RW	The invalid page table lookup bit is set when the longword scatter/gather map entry being accessed is invalid.  The address, AD<31:0>, is locked in the PEAR.
uMRD	<13>RW	The unrecoverable memory read data bit is set when an uncorrectable error is encountered on data read from the DMA read buffer in the 21071-BA chip during a DMA read or a scatter/gather read transaction.
cMRD	<12>RW	The correctable memory read data bit is set when a correctable error is encountered on data read from the DMA read buffer in the 21071-BA chip during a DMA read or a scatter/gather read transaction.  Setting the dCEI bit will disable setting the cMRD bit.
nDev	<11>R	The no device bit is set when DEVSEL# is not asserted in response to an I/O read or write transaction initiated on the PCI by the 21071-DA chip.  The AD<31:0> for this transaction is logged in the PEAR.
tAbt	<10>RW	The target abort bit is set when a PCI slave device ends an I/O read or write transaction using the PCI target abort protocol.  AD<31:0> is put in the PEAR.
iOPE	<09>RW	The I/O parity error is set when a parity error occurs in the data phase of an I/O read or write transaction.  AD<31:0> is put in the PEAR.
dDPE	<08>RW	The DMA parity error is set when a parity error occurs in the data phase of a DMA transaction.  AD<31:0> is put in the PEAR.
lost	<06>RW	The lost bit is set when the address register corresponding to an error is already locked due to a previous error.
ioRT	<05>RW	The retry timeout error is set when a timeout occurs on CPU-initiated write or read transactions over the PCI.  AD<31:0> is put in the PEAR.
dPEC	<04>RW	When set, the dPEC bit disables PCI address and data parity error checking by the 21071-DA chip.  When clear, parity checking will be performed.
dCEI	<03>RW	When the disable correctable error interrupt bit is set, correctable errors on DMA read data are not logged in the cMRD bit and the address is not logged in the SEAR.
pEnb	<02>RW	When pre-fetch enable is set, the sysBus master machine will enable pre-fetching on DMA reads.
tEnb	<00>RW	When the translation buffer (TLB) enable bit is set, the entire TLB is enabled.  When tEnb is clear, the TLB is turned off and subsequent scatter/gather reads will not result in allocation of TLB entries.


PCI Error Address Register (PEAR)

Digital AlphaStation 255 Registers

PCI Error Address Register

Address: 1 A000 0020, Machine Check Frame Offset: + 0x210

The PCI error address register is used to log the address of various errors relating to PCI bus transactions.

Click on the Description button to display the bit fields.


PEAR Bit Descriptions
PEAR Register Bit Descriptions

pci_Err	<31:00>R	The address sent out on the PCI bus (AD<31:0>) as the result of an I/O transaction is stored here.  This field logs the address of errors indicated by the nDev, tAbt, iOPE, dDPE, iPTL, and iORT bits in the DCSR. The register is valid only when one of these six error bits is set.  The type of error and the transaction determine how much of the pci_Err<31:0> field is valid. Condition Valid Field nDev and iPTL pci_Err<31:0> ioRT, tAbt, and iOPE during  dense memory writes pci_Err<31:5> ioRT, tAbt, and iOPE during  other transactions pci_Err<31:3> dDPE pci_Err<31:3>


sysBus Error Address Register (SEAR)

Digital AlphaStation 255 Registers

sysBus Error Address Register

Address: 1 A000 0040, Machine Check Frame Offset: + 0x218

The sysBus error address register is used to log the address of various errors relating to sysBus transactions.

Click on the Description button to display the bit fields.


SEAR Bit Descriptions
SEAR Register Bit Descriptions

sys_Err <33:5>	<31:00>R	This field logs the address sent out on the sysBus.  Addresses are logged as the result of the mErr, uMRD, or cMRD bits in the DCSR being set.


PAL Base Address Register (PAL_BASE)

Digital AlphaStation 255 Registers

PAL Base Address Register

Address: IPR Ibox, Index=11, Machine Check Frame Offset: + 0x130

The PAL base address register is a read/write register containing the base address for the PALcode.


Abox Control Register

Digital AlphaStation 255 Registers

Abox Control Register

Address: IPR Abox, Index=14, Machine Check Frame Offset: + 0x160

The Abox control register is a write-only register!  It is included here so that you will know what it controls.

Click on the Description button to display the bit fields.


ABOX_CTL Bit Descriptions
ABOX_CTL Register Bit Descriptions

DC_FHIT	<11>W	When set, this bit forces all D-stream references to hit in the Dcache.  This bit takes precedence over DC_ENA.
DC_ENA	<10>W	When set, the DC_ENA bit enables the Dcache.  When cleared, the Dcache is disabled and flushed.
EMD_EN	<06>W	When set, the EMD_EN bit inverts physical address bit <2> for all D-stream references.  This provides limited support for big endian formats.
SPE_2	<05>W	When set, the SPE_2 bit enables one-to-one super-page mapping of D-stream virtual addresses(VA) with VA<33:13> directly to physical addresses PA<33:13>, if VA bits VA<42:41>=2.  VA bits <40:34> are ignored in this translation.  Access is allowed only in kernel mode.
SPE_1	<04>W	When set, the SPE_1 bit enables one-to-one super-page mapping of D-stream VA with VA<42:30>=1FFE to physical addresses with PA<33:30>=0.  Access is allowed only in kernel mode.
IC_SBUF_EN	<03>W	When set, the IC_SBUF_EN bit enables operation of a single-entry Icache stream buffer.
CRD_EN	<02>W	When set, the CRD_EN bit enables the Abox to generate an interrupt request whenever a pin bus transaction is terminated with a cAck_h code of SOFT_ERROR.
MCHK_EN	<01>W	When the MCHK_EN bit is set, the Abox generates a machine check when errors that are not correctable by the hardware are encountered.  When cleared, uncorrectable errors do not cause a machine check.  However, the BIU_STAT, DC_STAT, BIU_ADDR, and FILL_ADDR registers are updated and locked when errors occur.
WB_DIS	<00>W	When set, the WB_DIS bit prevents the write buffer from sending write data to the BIU.  It should be set only for diagnostics.


Bus Interface Unit Control Register (BIU_CTL)

Digital AlphaStation 255 Registers

Bus Interface Unit Control Register

Address: IPR Abox, Index=18, Machine Check Frame Offset: + 0x178

The bus interface unit control register is a write-only register!  It is included here so that you will know what it controls.

Click on the Description button to display the bit fields.


BIU_CTL Bit Descriptions
BIU_CTL Register Bit Descriptions

BAD_DP	<36>W	When the BAD_DP bit is set, the 21064 will invert the value placed on bits <0>, <7>, <14>, and <21> of the check_h<27:0> field during off-chip writes.  This produces bad parity in parity mode and bad check bit codes when in ECC mode.
BC_PA_DIS	<35:32>W	You may use this 4-bit field to prevent the CPU chip from using the external cache to service reads and writes based on the quadrant of physical address space that they reference.  The table below shows the correspondence between this field and physical address space: BIU_CTL bits Physical Address 32 PA<33:32>=0 33 PA<33:32>=1 34 PA<33:32>=2 35 PA<33:32>=3
BAD_TCP	<31>W	When the BAD_TCP bit is set, bad parity is written into the tag control RAM whenever the CPU does a fast external RAM write.
BC_SIZE	<30:28>W	This field indicates the size of the external cache: BC_SIZE SIZE 000 128 KB 001 256 KB 010 512 KB 011 1 MB 100 2 MB 101 4 MB 110 8 MB
BC_WE_CTL <15:1>	<27:13>W	The external cache write enable control is used to control the timing of the write enable and chip enable pins during writes into the data and tag control RAMs.
BC_WR_SPD	<11:08>W	The external cache write speed field indicates to the BIU the write cycle time of the external cache RAM chips.  The value is measured in CPU cycles.
BC_RD_SPD	<07:04>W	The external cache read speed field indicates to the BIU the read access time of the external cache RAM chips.  The value is measured in CPU cycles.
BC_FHIT	<03>W	When the external cache force hit bit is set and the BC_ENA bit is also set, all pin bus READ_BLOCK and WRITE_BLOCK transactions are forced to hit in the external cache.  Tag and tag control are ignored.
OE	<02>W	When this bit is set, the 21064 does not assert its chop-enable pins during RAM write cycles. This enables these pins to be connected to the output-enable pins of the cache RAMs.
ECC	<01>W	When the ECC bit is set, the 21064 generates and expects ECC on the check_h pins.  When the ECC bit is clear,  the 21064 generates and expects parity on four of the check_h pins.
BC_ENA	<00>W	When the external cache enable bit is cleared, the external cache is disabled.  Read/write references will then cause a request on the cReq_h immediately.


General Control Register

Digital AlphaStation 255 Registers

General Control Register

Address: 1 8000 0000, Machine Check Frame Offset: + 0x1A0

The general control register contains status information that affects the major operational modes of the cache and memory control chip.

Click on the Description button to display the bit fields.


General Control Register Bit Descriptions

bc_BadAP	<13>RW	Bcache force bad address parity.  When set, the tag address parity will be loaded as bad.  This bit is independent of the FrcTag bit.
bc_FrcP	<12>RW	Bcache force parity.  When set, the parity bit will be set on the next cache fill.
bc_FrcV	<11>RW	Bcache force valid.  When set, the valid bit will be set on the next cache fill.
bc_FrcD	<10>RW	Bcache force dirty.  When set, the dirty bit will be set on the next cache fill.
bc_FrcTag	<09>RW	Bcache force tag.  When set, the Bcache will be probed for victims and the line will be invalidated using the values in bc_FrcD, bc_FrcV, and bc_FrcP.
bc_IgnTag	<08>RW	Bcache ignore tag.  When set, Bcache probes will act as if the valid bit was invalid.  All tag results will be ignored and any victims will be lost.
bc_LongWr	<07>RW	Bcache long writes.  When set, two sysBus cycles are required to write to the cache data RAMs.
bc_NoAlloc	<06>RW	Bcache no allocate mode.  When set, CPU writes to cacheable memory space will not be allocated to the cache.
bc_En	<05>RW	Bcache enable.  When clear, the Bcache is disabled and the cache state machine will not probe the cache.
wideMem	<04>RW	Memory size.  Reads the status of the wideMem input pin.  Returns 1 if the memory is 128-bits wide, or a 0 if 64-bits wide.
sysArb	<02:01>RW	DMA arbitration mode.  Determines arbitration scheme for sysBus transactions. Value Meaning 0X CPU priority 10 DMA priority 11 DMA strong priority


Tag Enable Register

Digital AlphaStation 255 Registers

Tag Enable Register

Address: 1 8000 0060, Machine Check Frame Offset: + 0x1B0

The tag enable register is a read/write register that indicates which bits of the cache tag are to be compared with sysAdr<33:5>.  If a bit is 1, the corresponding bits in sysAdr<33:5> and tagAdr<31:17> are compared.  If a bit is 0, there is no comparison of those bits and the tagAdr bit is assumed to be tied low on the module.  Bits <15:1> in the register represent tagAdr<31:17>.


Error Low Address Register

Digital AlphaStation 255 Registers

Error Low Address Register

Address: 1 8000 0080, Machine Check Frame Offset: + 0x1B8

The error low address register locks the low order bits of the sysBus address that caused the error that set the bc_TAPErr, bc_TCPErr. or nxMErr bit in the EDSR.  If a victim read caused the error, then the victim address is not latched; rather the address of the transaction is latched.  Bits <15:0> represent sysAdr<20:5>.  This register is read-only and only valid when an error is indicated.


Error High Address Register

Digital AlphaStation 255 Registers

Error High Address Register

Address: 1 8000 00A0, Machine Check Frame Offset: + 0x1C0

The error high address register locks the high order bits of the sysBus address that caused the error that set the bc_TAPErr, bc_TCPErr. or nxMErr bit in the EDSR.  If a victim read caused the error, then the victim address is not latched; rather the address of the transaction is latched.  Bits <12:0> represent sysAdr<33:21>.  This register is read-only and only valid when an error is indicated.


LDx_L Low Address Register

Digital AlphaStation 255 Registers

LDx_L Low Address Register

Address: 1 8000 00C0, Machine Check Frame Offset: + 0x1C8

The LDx_L low address register stores the low order bits of the last locked address.  Bits <15:0> represent sysAdr<20:5>.  This register is read-only.


LDx_L High Address Register

Digital AlphaStation 255 Registers

LDx_L High Address Register

Address: 1 8000 00E0, Machine Check Frame Offset: + 0x1D0

The LDx_L low address register stores the low order bits of the last locked address.  Bits <12:0> represent sysAdr<33:21>.  This register is read-only.


Base Address Registers

Digital AlphaStation 255 Registers

Base Address Registers

Bank 0 Address: 1 8000 0800, Machine Check Frame Offset: + 0x1D8

Bank 1 Address: 1 8000 0820, Machine Check Frame Offset: + 0x1E0

Bank 2 Address: 1 8000 0840, Machine Check Frame Offset: + 0x1E8

Each memory bankset has a corresponding base register.  The bits in this register are compared with the incoming sysAdr to determine the bankset being addressed.  The contents of this register are validated by setting the valid bit in the configuration register of that bankset.  The AlphaStation 255 uses bank registers 0, 1, and 2 for main memory.


Configuration Registers

Digital AlphaStation 255 Registers

Configuration Registers

Bank 0 Address: 1 8000 0A00, Machine Check Frame Offset: + 0x1F0

Bank 1 Address: 1 8000 0A20, Machine Check Frame Offset: + 0x1F8

Bank 2 Address: 1 8000 0A40, Machine Check Frame Offset: + 0x200

Each memory bankset has a corresponding configuration register.  This register contains mode bits and bits for memory address generation, as well as bankset decoding.  The AlphaStation 255 uses configuration registers 0, 1, and 2 for main memory.


Configuration Registers Bit Descriptions
General Control Register Bit Descriptions

s0_ColSel<2:0>	<8:6>RW	Column address selection.  Indicates the number of valid column bits expected at the DRAMs.  Used along with memory width information to generate row or column addresses. s0_ColSel<2:0> Row,Column Bits 000 12, 12 001 12, 10 or 11, 11 010 Reserved 011 10, 10 1XX Reserved
s0_SubEna	<5>RW	Enable subbanks.  When set, subbanks are enabled and determined according to the table in the s0_Size description.
s0_Size<3:0>	<4:1>RW	Bankset size in MB.  Indicates the size of the bankset in order to determine which bits are used to compare the bankset base address with the physical address (PA) and to generate the subset.  Corresponds to the total size of the bankset, including subbanks, if present. s0_size<3:0> Compared Subset Set Size 0000 Reserved 0001 PA<33:29> PA<28> 512 MB 0010 PA<33:28> PA<27> 256 MB 0011 PA<33:27> PA<26> 128 MB 0100 PA<33:26> PA<25> 64 MB 0101 PA<33:25> PA<24> 32 MB 0110 PA<33:24> PA<23> 16 MB 0111 PA<33:23> PA<22> 8 MB 1XXX Reserved
s0_Valid	<0>RW	Bankset valid.  If set, all timing and configuration parameters for the bankset are valid, and access to the bankset is allowed.  If cleared, access to the bankset is not allowed.


Translated Base Registers 1 and 2

Digital AlphaStation 255 Registers

Translated Base Registers 1 and 2

1. Address: 1 A000 00C0, Machine Check Frame Offset: + 0x220

2. Address: 1 A000 00E0, Machine Check Frame Offset: + 0x228

The t_Base field of the translated base registers (1 and 2) specifies the base CPU address for either the:

translated PCI address for the PCI target window (if scatter/gather is disabled), or

scatter/gather map table for the PCI target window (if scatter/gather is enabled).

This register is read/write.


PCI Base Registers 1 and 2

Digital AlphaStation 255 Registers

PCI Base Registers 1 and 2

1. Address: 1 A000 0100, Machine Check Frame Offset: + 0x230

2. Address: 1 A000 0120, Machine Check Frame Offset: + 0x238

The two PCI base registers are used in the mapping of PCI addresses to physical memory addresses (one base register for each of the two allowed regions).


PCI Base Register Bit Descriptions

pci_Base <31:20>	<31:20>RW	The pci_Base field specifies the base address of the PCI target window.
wEnb	<19>RW	Window enable.  When the wEnb bit is cleared this PCI target window is disabled and will not respond to PCI-initiated transfers.  When set, this PCI target window is enabled and will respond to PCI-initiated transfers that hit in the address range of the target window.
sGEn	<18>RW	Scatter/gather enable.  When the sGEn bit is cleared, the PCI target window uses direct mapping to translate a PCI address to a CPU address.  When set, the PCI target window uses scatter/gather mapping to translate a PCI address to a CPU address.
Reserved	<17:0>MBZ


PCI Mask Registers 1 and 2

Digital AlphaStation 255 Registers

PCI Mask Registers 1 and 2

1. Address: 1 A000 0140, Machine Check Frame Offset: + 0x240

2. Address: 1 A000 0160, Machine Check Frame Offset: + 0x248

The PCI mask registers are used with the PCI base registers to allow two regions in PCI memory space to be mapped to system memory.  The pciMask <31:20> field specifies the size of the PCI target window.  It is also used in the translation of the PCI address to the CPU address.

This register is read/write.


Host Address Extension Register 0

Digital AlphaStation 255 Registers

Host Address Extension Register 0

Address: 1 A000 0180, Machine Check Frame Offset: none

The HAXR0 register is hardcoded to 0.  A read from this register returns a 0; a write does nothing.


Host Address Extension Register 1

Digital AlphaStation 255 Registers

Host Address Extension Register 1

Address: 1 A000 01A0, Machine Check Frame Offset: + 0x250

The host address extension register 1 (HARX1) is used to generate AD<31:27> on CPU-initiated transactions that address PCI memory space.

The eAddr<4:0> field is used as the upper five PCI address bits (AD<31:27>).  The field is read/write.


Host Address Extension Register 2

Digital AlphaStation 255 Registers

Host Address Extension Register 2

Address: 1 A000 01C0, Machine Check Frame Offset: + 0x258

The host address extension register 2 (HARX2) is used to generate AD<31:24> on CPU-initiated transactions that address PCI I/O space.  It is also used to generate AD<1:0> during PCI configuration reads and writes.

The eAddr<7:0> field is used as the upper five PCI address bits (AD<31:27>).  The field is read/write.

The conf_Addr<1:0> field is used as the lower PCI address bits (AD<1:0>) during CPU-initiated transactions to PCI configuration space.


PCI Master Latency Timer Register

Digital AlphaStation 255 Registers

PCI Master Latency Timer Register

Address: 1 A000 01E0, Machine Check Frame Offset: + 0x260

The pMLC<7:0> field of the PCI master latency register (PMLT) is loaded into the master latency timer register at the start of a PCI master transaction initiated by the PCI bus bridge chip.


TLB Tag Registers 0-7

Digital AlphaStation 255 Registers

TLB Tag Registers 0-7

0. Address: 1 A000 0200, Machine Check Frame Offset: + 0x268

1. Address: 1 A000 0220, Machine Check Frame Offset: + 0x270

2. Address: 1 A000 0240, Machine Check Frame Offset: + 0x278

3. Address: 1 A000 0260, Machine Check Frame Offset: + 0x280

4. Address: 1 A000 0280, Machine Check Frame Offset: + 0x288

5. Address: 1 A000 02A0, Machine Check Frame Offset: + 0x290

6. Address: 1 A000 02C0, Machine Check Frame Offset: + 0x298

7. Address: 1 A000 02E0, Machine Check Frame Offset: + 0x2A0

These registers are read only.  The pci_Page<31:13> field specifies the PCI page address (TAG) corresponding to the translated CPU page address in the associated TLB data register.

The entry valid (eVal) bit can be read through bit <12>.  Normally, the invalid bit contains the value read during a page table entry read.


TLB Data Registers 0-7

Digital AlphaStation 255 Registers

TLB Data Registers 0-7

0. Address: 1 A000 0300, Machine Check Frame Offset: + 0x2A8

1. Address: 1 A000 0320, Machine Check Frame Offset: + 0x2B0

2. Address: 1 A000 0340, Machine Check Frame Offset: + 0x2B8

3. Address: 1 A000 0360, Machine Check Frame Offset: + 0x2C0

4. Address: 1 A000 0380, Machine Check Frame Offset: + 0x2C8

5. Address: 1 A000 03A0, Machine Check Frame Offset: + 0x2D0

6. Address: 1 A000 03C0, Machine Check Frame Offset: + 0x2D8

7. Address: 1 A000 03E0, Machine Check Frame Offset: + 0x2E0

These registers are read only.  The cpu_Page<32:13> field allows bits <32:13> of the CPU address to be read.


Translation Buffer Invalidate All

Digital AlphaStation 255 Registers

Translation Buffer Invalidate All

Address: 1 A000 0400, Machine Check Frame Offset: none

The TBIA register is a write-only register.  A write to this register causes all the valid entries in the scatter/gather map TLB to be invalidated.


Console Commands

Console Menu

The Digital AlphaStation 255 system can have loaded one of two available console firmware programs.  The AlphaBIOS firmware supports Windows NT and the SRM console firmware supports Digital UNIX and OpenVMS.  The console firmware resides in flashROM on the motherboard.  The firmware can be changed or updated in the field.

AlphaBIOS (Firmware for Windows NT)

SRM (Firmware for Digital UNIX and OpenVMS)

ICONFIG (A forms-based interface to ISACFG)

ISA Configuration Utility (ISACFG)

EWRK3 Configuration Utility (EWRK3_CONFIG)

Updating or Changing the Console Firmware


AlphaBIOS Firmware

Digital AlphaStation 255 Console Commands

AlphaBIOS Firmware

The AlphaBIOS firmware features an easy-to-use menu interface.  It is intuitively designed and straightforward to use.
When the system is powered on and POST successfully completes, AlphaBIOS is loaded from the flashROM and started.

Several initialization tasks are performed.

Click on the operating system list for boot information and the <F2> for AlphaBIOS Setup information.


AlphaBIOS Initialization Tasks

The initialization tasks performed by AlphaBIOS include:

  Initialize the keyboard and video devices.

  Test memory.

  Detect and initialize the SCSI disk controllers.

After the video device is initialized, subsequent steps are displayed on the monitor in an initialization window.  When the SCSI initialization is complete, AlphaBIOS leaves the initialization window and displays the boot screen shown here.


Booting the Operating System

The boot screen lists each Windows NT operating system that has been set up on the system.  Use the OS Selection Setup utility to modify the list.  OS Selection is started by selecting it from the Utilities menu in the AlphaBIOS Setup screen.  When a particular copy of Windows NT is selected, AlphaBIOS starts the two-stage boot process.

During the first stage, AlphaBIOS reads the OS Loader program (OSLOADER.EXE in Windows NT 3.51) from the path described by the selection.  The OS Loader program must be located in a FAT-formatted partition.

In the second stage, the OS Loader program starts.  It uses AlphaBIOS services to load the operating system components.  Once the components are loaded, the OS Loader starts the operating system.


AlphaBIOS Setup Screen

Digital AlphaStation 255 Console Commands

AlphaBIOS Setup Screen

The AlphaBIOS Setup screen is used to perform several system configurations tasks.  Click on the screen below for task descriptions.  Click on ESC to return to the AlphaBIOS boot screen.


Display System Configuration

The Display System Configuration screen provides detailed information about the CPU, memory, attached devices, and option boards.  The information is divided into six configuration categories:

Category	Contents
System board	System type, processor, CPU speed, cache, memory size, floppy drives, keyboard, and AlphaBIOS version.
Memory	Memory size and starting address by bank.
Hard disk	Physical disk ID, controller, controller ID, raw disk size, SCSI ID, and partition maps.
PCI	Device names and types, revision levels, and slots.  Press Enter for PCI device detail.
SCSI	SCSI controller information and a list of SCSI devices.
Integrated peripherals	I/O address and IRQ information about COM1, COM2, and the parallel port.


Upgrading AlphaBIOS

The Upgrade AlphaBIOS selection is used to install newer releases of the AlphaBIOS firmware into the system flashROM.

Prior to selecting this choice, insert the firmware update media into the appropriate device, typically a floppy or CD-ROM drive.

CAUTION: Check the revision level of the currently installed firmware and the firmware on the update media before selecting this command.

NOTE: Use this command to switch from the AlphaBIOS firmware to the SRM firmware.


Hard Disk Setup

The Hard Disk Setup selection is used to create and delete disk partitions, and format the disks.

An Express option is available to set up the first hard disk with the recommended default partition arrangement.

Partition 1 is the drive size minus 6 MB.  This partition typically will be NTFS-formatted during the Windows NT installation.

Partition 2 is 6 MB, FAT-formatted.  This is the system partition.


AlphaBIOS CMOS Setup Screen

Digital AlphaStation 255 Console Commands

CMOS Setup Screen

The CMOS Setup screen is used to perform basic system configurations tasks.  Click on the screen below for task descriptions.  Click on ESC to return to the AlphaBIOS Setup screen.


Install Windows NT

Prior to selecting this choice, insert the Windows NT distribution CD-ROM into the CD drive.  When selected, the AlphaBIOS firmware will start installing the Windows NT system.  Screen displays will appear to guide you through the installation.

If this is the first time Windows NT is being installed on the system, before starting the installation use CMOS Setup to set the system date and time, and Hard Disk Setup to partition and format a disk.


Utilities

The Utilities selection is used to set up the operating system selections and to run maintenance programs, such as RAID configuration utilities.

The OS System Selection contains pointers to the disk and partition containing OSLOADER.EXE associated with a particular operating system installation.  There are also pointers to the operating system directory (OS path).  Provisions to validate operating system selections are included in the program.


About AlphaBIOS

This About AlphaBIOS selection displays version information.


F1 Help

There are two levels of keyboard help available.  Pressing F1 once displays explanations of the keystrokes available for the specific part of AlphaBIOS currently displayed.

Pressing F1 twice displays explanations of the keystrokes available for navigating through the AlphaBIOS interface.


Set System Time
Set System Date and Time

Selecting this choice will allow you to enter the date and time.  Use a 24-hour format for the time.


Set Floppy Drive and Keyboard Configuration

Selecting these choices allow you to enter configuration information about the floppy drive(s) and the keyboard

The keyboard setting makes it possible to use keyboards for different languages.  To ensure correct character mappings, the language of the keyboard, the Windows NT system, and this keyboard language selection should all match.


Context Help Display

This message box displays information pertaining to the currently selected operation.


Setting the Display Color

Pressing F3 repeatedly cycles through the available AlphaBIOS color schemes.


CMOS Setup Defaults

Pressing F7 restores the standard CMOS setup default values.  The advanced CMOS setup values are not affected.


Save CMOS Setup Changes

Pressing F10 saves the changes made in both the standard and advanced modes of CMOS setup.

Pressing Escape restores the settings in effect when CMOS Setup was started.  This option also discards any changes made in advanced CMOS setup.


Advanced CMOS Setup Screen

Digital AlphaStation 255 Console Commands

Advanced CMOS Setup Screen

Advanced CMOS Setup is used to set system-specific parameters and password protection.

Click on ESC to return to the CMOS Setup screen.


Setting up Auto Start
Auto Start

Auto Start determines whether the primary operating system is automatically started after the system is reset or power cycled.  The Auto Start Count setting is the delay in seconds from the time the boot screen is displayed until the system is booted.  To stop the countdown, press a down arrow to stay at the boot screen, or press F2 to enter CMOS Setup.


PCI Parity Checking

The PCI Parity Checking setting controls parity testing at the PCI bridge chip.  Use caution when making this selection.  It allows you to turn PCI parity checking on and off.  The new value becomes effective after an init or power cycle. See Disabling PCI Parity for more information.


Power-up Memory Test

Use this feature to enable or disable the power-up memory test.  When enabled, the memory test writes and reads patterns of data to main memory.


Password Setup

Use this feature to enable and disable two levels of security: setup protection and startup protection.  When setup protection is enabled, a password is required to start AlphaBIOS Setup.  When startup protection is enabled, a password is required before the system initializes.  Startup protection provides more comprehensive protection than setup protection because the system cannot be used at all until the correct password is entered.


SCSI Termination

The SCSI termination feature is not supported on the AlphaStation 255.  The SCSI bus must be properly terminated internally and externally with the appropriate terminator plugs.


SRM Console

Digital AlphaStation 255 Console Commands

SRM Console

SRM Console Conventions

SRM Console Special Characters

Console Commands

The SRM console firmware supports many commands.  Type Help at the >>> prompt for a list of all the commands.  The following console commands include some you are more apt to be using (click on a command for more information):

Boot

Examine

Deposit

Set

Show

Isacfg

ICONFIG (A forms-based interface to ISACFG)

Security Features

EWRK3_CONFIG


SRM Console Conventions

The following table lists SRM console conventions:

Item	Convention
Console prompt	>>>
Continuation line prompt	_>
Maximum command length	255 characters
Multiple contiguous spaces or tabs	Treated as a single space
Command abbreviations	Allowed, if not ambiguous
Command qualifiers or options	Prefix with a space and a dash " -"
Numbers	Hexadecimal, unless otherwise specified.  (Note that registers such as R0-R31 are shown in decimal notation.)


SRM Console Special Characters

The following table lists SRM console special characters:

Character/Key(s)	Function
Return	Terminates command line input.
Backspace	Deletes the character that was previously typed.
Ctrl A	Toggles insert/overstrike mode.   (Overstrike is the default.)
Ctrl B, , or	Recalls previous commands.  (The last 16 commands are stored.)
Ctrl C	Terminates the foreground process.
Ctrl D or	Moves the cursor left one position.
Ctrl E	Moves the cursor to the end of the line.
Ctrl F or	Moves the cursor right one position.
Ctrl H	Moves the cursor to the beginning of the line.
Ctrl O	Suppresses console output.
Ctrl Q	XOFF, Resumes flow of data to the console .
Ctrl S	XON, Stops the flow of data to the console.
Ctrl U	Deletes the entire line.
Ctrl R	Retypes the current command line.
Ctrl P	In console mode, Ctrl P is ignored. In program mode, and if enabled, the software running is halted and the console firmware is started.


SRM Boot Command
Digital AlphaStation 255 Console Commands
Boot Command

boot [-file filename] [-flags longword[,longword]] [-protocols enet_protocol] [-halt] [boot_device]

Description

The boot command performs the following functions:

  Initializes the processor

  Loads a program image from the specified boot device

  Transfers control to the loaded image

Where:

-file filename	Specifies the name of a file to load into the system.  For booting from Ethernet, this name is limited to 15 characters.  Use the set boot_file command to set an environment variable that specifies a default boot file.
-flags longword[,longword]	Specifies additional information for the operating system.  Use the set boot_osflags command to set an environment variable that specifies a default boot flag values.   OpenVMS boot flags.   Digital UNIX boot flags.
-protocols enet_protocol	Specifies an Ethernet protocol(s) that will be used for a network boot.  Values may be mop or bootp.
-halt	Forces the bootstrap operation to halt and invoke the console program after the image is loaded and the page tables and other data structures are set up.
boot_device	Specifies a device path or list of devices that the firmware will attempt to boot.  Use the set bootdef_dev command to set an environment variable that specifies a default boot device.


SRM Boot Command Examples
Boot Command Examples


Boot Command Examples

>>>boot	Boots the system from the default boot device.
>>>boot ewa0	Boots the system from Ethernet port ewa0.
>>>boot -file dec2.sys ewa0	Boots the file named dec2.sys from Ethernet port ewa0.
>>>boot -protocol bootp ewa0	Boots using TCP/IP BOOTP protocol from Ethernet post ewa0.  (Make sure the environment variables ewa0_protocols and ewa0_inet_init are both set to BOOTP before booting.)
>>>boot -flags 0,1	Boots the system from the default boot device using flag settings 0,1.
>>>boot -halt dka0	Loads the image from disk dka0, but remains in console mode.
>>> boot  Trying MOP boot. ... ... ...	Successful boot from a system that is set to secure mode.  In this example the boot command is equivalent to: (boot eza0.0.6.0 -file myfile.sys -flags 0)
>>> set boot_file myfile.sys  Console is secure >>>  >>> boot -file myfile_ev4p2  Console is secure -  parameters are not allowed >>> boot -halt  console is secure -  parameters are not allowed >>> boot ezb0 Console is secure -  parameters are not allowed >>>	Unsuccessful boot examples from a system in secure mode.


SRM Examine Command
Digital AlphaStation 255 Console Commands
Examine Command

examine [-{b,w,l,q,o,h,d}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address

Description

The examine command displays the contents of an address you specify.  The address can be a memory location, register, device, or file.

Where:

-b	Byte of data.
-w	Word of data.
-l	Longword of data.
-q	Quadword of data.
-o	Octaword of data.
-h	Hexaword of data.
-d	Display data as a decoded macro instruction.
-physical	Reference physical address space.
-virtual	Reference virtual address space.
-gpr	Reference general purpose register address space.
-fpr	Reference floating point register address space.
-ipr	Reference internal processor register address space.
-n count	Specifies the number of consecutive locations to examine.
-s step	Specifies the address increment as a hexadecimal value.  This option allows you to override the increment that is normally derived from the data size.
[device:]	Selects the device to access.
address	Specifies the address of the first location to examine within the current device.


SRM Examine Examples
Examine Command Examples


Examine Command Examples

>>>e r0 gpr: 0(R0) 0000000000000002	Examine R0 by symbolic address
>>>e -g 0 gpr: 0(R0) 0000000000000002	Examine R0 by address space
>>>e gpr:0 gpr: 0(R0) 0000000000000002	Examine R0 by device name
>>>examine pc PC psr: 0(PC) 0000000000040A48	Examine the PC
>>>examine -n 5 r7 gpr:38 (R7) 000000000015CC00 gpr:40 (R8) 0000004E20006345 gpr:48 (R9) 0000000000000020 gpr:50(R10) 0000000000000000 gpr:58(R11) 0000000000000020 gpr:60(R12) 0000000000004200	Examine R7 and the next five registers.
>>>examine ipr:11 ipr: 11(KSP)0000000000400000	Examines IPR 11, the kernel stack pointer.


SRM Deposit Command
Digital AlphaStation 255 Console Commands
Deposit Command

deposit [-{b,w,l,q,o,h}] [-{physical,virtual,gpr,fpr,ipr}] [-n count] [-s step] [device:]address data

Description

The deposit command writes data to an address that you specify.  The address can be a memory location, register, device, or file.

Where:

-b	Byte of data.
-w	Word of data.
-l	Longword of data.
-q	Quadword of data.
-o	Octaword of data.
-h	Hexaword of data.
-physical	Reference physical address space.
-virtual	Reference virtual address space.
-gpr	Reference general purpose register address space.
-fpr	Reference floating point register address space.
-ipr	Reference internal processor register address space.
-n count	Specifies the number of consecutive locations to examine.
-s step	Specifies the address increment as a hexadecimal value.  This option allows you to override the increment that is normally derived from the data size.
[device:]	Selects the device to access.  The following devices are supported: pmem: Physical memory vmem: Virtual memory. All access and protection checking will occur.
address	An address that specifies the offset within a device into which data is deposited.  The address may also be any legal symbolic address.  Valid symbolic addresses are: gpr-name - symbol representing General Purpose Register ipr-name - symbol representing Internal Processor Register PC - Program Counter + - The location immediately following the last location referenced by an examine or deposit. - - The location immediately preceding the last location referenced by an examine or deposit. * - The location last referenced by an examine or deposit. @ - The location addressed by the last location referenced by an examine or deposit.
data	The data to be deposited.


SRM Deposit Command Examples
Deposit Command Examples


Deposit Command Examples

>>>d -n 1FF pmem:0 0	Clear the first 4096 bytes of physical memory.
>>>d -l -n 3 vmem:1234 5	Deposit 5 into four longwords starting at virtual memory address 1234.
>>>d -n 8 R0 FFFFFFFF	Loads GPRs R0 through R8 with -1.
>>>d -l -n 10 -s 200 pmem:0 8	Deposit 8 in the first longword of the first 17 pages in physical memory.


SRM Set Command
Digital AlphaStation 255 Console Commands
Set Command

set envar value [-default] [-integer] [-string]

Description

You use the set command to set or modify the value of an environment variable, or setup security features.  Use environment variables to pass configuration information between the console and the operating system.  Click here for security feature information.

Where:

envar	The environment variable to be assigned a new value.    Click here to see a list of environment variables.
value	The value that is assigned to the environment variable.  It can be either a numeric value or an ASCII string.
-default	Restores an environment variable to its default value.
-integer	Creates an environment variable as an integer.
-string	Creates an environment variable as a string.


SRM Set Command Examples
Set Command Examples


Set Command Examples

>>>set auto_action boot	The console will attempt to boot following an error, halt, or power-up.
>>>set bootdef_dev ewa0	The default boot device is set to ewa0.
>>>set boot_osflags 0,1	The default boot flags are set to 0,1.
>>>set ewa0_inet_init bootp >>>set ewa0_protocol bootp	Sets the system up for a network boot, such as from a Digital UNIX RIS server.
>>>set ewa0_mode twisted-pair	Sets the Ethernet controller to use the RJ45 Twisted-Pair connector.
>>>set foobar 5	An environment variable called foobar is created and given a value of 5.
>>>set language 0	After initing, the system will prompt you for the language.
>>>set password >>>set secure	Allows you to set the console password or secure mode.  Click here for security feature information.


SRM Environment Variables
Environment Variables


Digital AlphaStation 255
Environment Variables

auto_action	Sets the console action following an error, halt, or power-up.  The action can be halt, boot, or restart.  Halt is the default.
bootdef_dev	Sets the default device or device list from which the system will attempt to boot.  If the system shipped with its software installed, the variable is pre-set to point to the device containing the software.  Otherwise, the default value is null.
boot_file	Sets the file name to be used when a bootstrap requires a filename.  The default setting is null.
boot_osflags	Sets additional parameters to be passed to system software.  The default setting is 0,0.   OpenVMS boot flags.   Digital UNIX boot flags.
bus_probe_algorithm	This variable is used to determine the method used to size the PCI bus.  The values are old (for OpenVMS) or new (for Digital UNIX).  The default is new.
console	This variable routes the console output to either the graphics controller or the serial line port.
control_disfd	When set to enable, this variable write protects the floppy diskette drive.  When set to disable, writes are enabled.
control_irq11	This variable controls the source of IRQ11.  When set to irq11, the interrupt is from an ISA IRQ11 device.  When set to scsi, the SCSI controller is the source.
control_irq12	This variable controls the source of IRQ12.  When set to irq12, the interrupt is from an ISA IRQ12 device.  When set to mouse, the mouse controller is the source.
control_scsi_term	Unused in the AlphaStation 255.
control_idema	When set to enable, IDE devices are allowed to make requests.  When set to disable, IDE device requests are blocked.  There is no IDE on the AlphaStation 255.
ewa0_inet_init	Used when booting over a TCP/IP network.  The value is normally BOOTP.
ewa0_mode	This variable is set to the appropriate Ethernet media type being used by the system.  The possible values are: Twisted-Pair Full Duplex, Twisted-Pair AUI (Default) BNC Fast (for FAST Ethernet controllers) FastFD (for FAST Ethernet controllers which support full duplex)
ewa0_protocols	The possible values are BOOTP and MOP.  The default is MOP.
kbd_hardware_type	This variable specifies the keyboard type, LK411 or PCXAL.  The default is PCXAL.
language	The language environment variable associates a language to the system.  You can have the system prompt you for the language using the following command:  >>>set language 0 and then >>>init.  Select the desired language.  Type >>>init again, then power cycle the system
os_type	Set to the operating system running on the system.  The possible values are OSF, UNIX, OpenVMS, and VMS.
pci_parity	The pci_parity variable controls PCI parity checking at the PCI bridge chip.  The new value becomes effective after an init or power cycle. The possible values are: On - parity checking is performed Off - parity checking is disabled Sniff - parity checking will be on for SCSI controllers (NCR53C810) at rev 2.  Otherwise, parity checking is off.
pkao_fast	A value of 0 sets the SCSI mode to slow (5 MB/sec); a value of 1 sets the SCSI mode to fast (10 MB/sec).  Digital UNIX operating system users also must edit the configuration file and rebuild the kernel.
tga_sync_green	This variable is used to control the composite video signal for monitors on the ZLXp controller that cannot detect the presence of composite video or v/h signals.  The possible values are: 1 - Composite video for first ZLXp. 2 - Composite video for second ZLXp. 3 - Composite video for first and second ZLXp.


SRM Show Command
Digital AlphaStation 255 Console Commands
Show Command

show [{config, device, hwrpb, memory, pal, version,...}] [envar]

Description

The show command displays the current value of a specified environment variable. The show command also displays information about the system, according to the arguments entered.

Where:

config	Displays the current system configuration.
device [device name]	Displays the devices and controllers in the system.  Specifying a device name returns information on that device only.
envar	Displays the value of the environment variable specified.   Click here to see a list of environment variables.
error	Displays error log information.
fru	Displays FRU information.
hwrpb	Display the Alpha HWRPB.
map	Displays the system virtual memory map.
memory	Displays the memory module configuration.
pal	Displays the version of OpenVMS and Digital UNIX PALcode.
version	Displays the version of the console firmware.


SRM Show Command Examples
Show Command Examples


Show Command Examples

>>>show config	Firmware SRM Console:   V6.0-311 show_arc: ARC Console is not found PALcode:       VMS PALcode X5.48-115,                 OSF PALcode X1.35-84 Serial ROM:    X0.40 Diag ROM:      V1.1 Processor DECchip (tm) 21064A-6    233Mhz 1MB Cache MEMORY   64 Meg of System Memory   Bank 0 = 32 Mbytes(8 MB Per Simm)            Starting at 0x0   Bank 1 = 32 Mbytes(8 MB Per Simm)            Starting at 0x2000000   Flash ROM0 Mfr - AMD PCI Bus   Bus 00 Slot 06: NCR 810 Scsi Controller                pka0.7.0.6.0  SCSI Bus ID 7                dka0.0.0.6.0  RZ26L                dka400.5.0.6.0RRD45   Bus 00 Slot 07: Intel SIO 82378   Bus 00 Slot 12: Digital ZLXp Graphics                   Controller   Bus 00 Slot 14: DECchip 21040 Network                   Controller        ewa0.0.0.14.0      08-00-2B-E2-1C-25 ISA Slot Dev Name Type   Enable BaseAd  IRQ DMA 0       0 MOUSE  Embedded Yes  60     12       1  KBD   Embedded Yes  60      1       2  COM1  Embedded Yes  3f8     4       3  COM2  Embedded Yes  2f8     3       4  LPT1  Embedded Yes  3bc     7       5 FLOPPY Embedded Yes  3f0     6   2 2       0 PCXBJ Singleport Yes 530     9   0
>>>show device	dka0.0.0.6.0    DKA0   RZ25L          0006 dka400.4.0.6.0  DKA400 Toshiba CD-ROM 3213 dva0.0.0.0.1    DVA0 ewa0.0.0.0.1    EWA0   08-00-2B-33-40-8F pka0.7.0.6.0    PKA0   SCSI Bus ID 7
>>>show memory	64 Meg of System Memory Bank 0 = 32 Mbytes(8 MB Per Simm)          Starting at 0x0 Bank 1 = 32 Mbytes(8 MB Per Simm)          Starting at 0x2000000 Flash ROM0 Mfr - AMD
>>>show version	V6.0-311 Nov 29 1995 16:10:02


OpenVMS Boot Flags

The OpenVMS boot flags consist of two portions separated by a comma: root , bootflag.  The value may be stored in the boot_osflags variable or typed in when booting.  The default value is 0,0.  The left half specifies the directory to boot from (0 = [SYS0], 1 = [SYS1] and so forth).  The right half can be used to enable specific functions during booting as shown below:

Value	Bit	Description
1	0	Conversational boot (SYSBOOT>).
2	1	Maps XDELTA to a running system.
4	2	Stops at the initial system breakpoint.
8	3	Performs a diagnostic bootstrap.
10	4	Stops at the bootstrap breakpoints.
20	5	Omits header from secondary boot image.
80	7	Prompts for the name of the secondary bootfile.
100	8	Halts the system before secondary bootstrap.
2000	13	Marks corrected read data error pages as bad.
10000	16	Displays extensive debug messages during booting.
20000	17	Displays selected user messages during booting.


Digital UNIX Boot Flags

The Digital UNIX boot flags can be stored in the boot_osflags variable or typed in along with the boot command.  The possible Digital UNIX boot flags are:

Flag	Description
a	Load operating system from the specified boot device. Boot to multiuser mode.
i	Prompt for the name of a file to load and other options (Boot interactively). Boot to single user mode.
s	Stop in single user mode. Boot /vmunix to single user mode and stop at the # (root) prompt.
D	Full dump, implies "s" as well


ISACFG Utility
Digital AlphaStation 255 Console Commands
ISA Configuration Utility (ISACFG)

isacfg [-slot <slot#>] [-dev <device#>] [-all|-rm|-mk|-mod] [-<field> <value>] . . .

Description

ISA devices cannot be probed for configuration information by the Digital UNIX or OpenVMS operating systems.  Therefore, you must enter ISA option information manually using the ISA configuration (ISACFG) utility.  You should run this utility before installing a new ISA option module on a Digital AlphaStation 255 system running either the Digital UNIX or OpenVMS operating systems.  A new forms-based interface to ISACFG was developed.  See ICONFIG  for more information.

Where:

-all	Shows the entire configuration table.  Overrides all other commands.
-dev <dev#>	Optional, defaults to 0 if not entered.  On a multifunction or multiport adapter, this specifies the device on the adapter.
-dmachan{0-3} <#>	Allows you to specify up to four DMA channels for the device.
-dmamode{0-3} <#>	Allows you to specify the DMA type for -dmachan{0-3}. DMA modes are: 1 = Block 2 = Demand 4 = Single 8 = Cascade
-enadev	Allows you to specify whether an entry is enabled or disabled.  Disabled devices are not used in resource allocation calculations.  The possible values are: 0 - No (disabled) 1 - Yes (enabled)
-etyp <#>	Defines an entry type for this entry.  The # sign can be: 0 - Unused 1 - Single option 2 - Embedded multiport device 3 - Multiport option device
-handle {string}	Binds a name to the driver (up to 15 characters).
-init	Initializes the configuration table to the default settings.
-iobase{0-5} <#>	Specifies up to 6 I/O base registers for a particular device entry (in hexadecimal).
-irq{0-3} <#>	Allows you to assign up to four IRQ channels to the device (in decimal).
-membase{0-2} <#>	Specifies up to 3 R/W ISA memory regions (in hexadecimal).
-memlen{0-2} <#>	Specifies the length corresponding to membase{0-2} (in hexadecimal).
-mk	Adds an entry into the table.
-mod	Modifies an entry in the table.
-rm	Deletes an entry from the table.
-rombase <#>	Specify an address for ISA BIOS ext. ROM (in hexadecimal).
-romlen <#>	Specifies length of ROM (in hexadecimal).
-slot <slot#>	Allows you to enter a unique slot number for each ISA adapter.  You may assign the numbers in any order.  The slot number does not relate to a physical ISA adapter position in the motherboard.  Slot 0 is reserved for the local multiport adapter.
-totdev <#>	Placeholder for you to keep track of # of devices at this slot.  Modify this for your own use.


SRM ISACFG Command Examples
ISACFG Command Examples


ISACFG Command Examples

Add the DE205 option by typing its script name:

>>>add_de205

or the full command:

>>>isacfg -slot 1 -dev 0 -mk -handle DE200-LE \
_>-irq0 5 -iobase0 300 -membase0 d0000 -etyp 1 -enadev 1

Enable the audio subsystem by typing its script name:

>>>add_sound

or the full command:

>>>isacfg -slot 2 -etyp 1 -mk -iobase0 530 -iobase1 388 \
_>-irq0 9  -dmachan0 0 -dmachan1 1 -handle PCXBJ -enadev 1

Disable the audio subsystem with the following command:

>>>isacfg -slot 2 -dev 0 -rm  or
>>>isacfg -slot2 -dev 0 -enadev 0 -mod

Add the FAX/MODEM (PCXDF-AA) option by typing its script name:

>>>add_fax

or the full command (two commands in this case):

>>>isacfg -mod -slot 0 -dev 3 -enadev 0
>>>isacfg -slot 4 -dev 0 -mk -handle COM4 -irq0 3 \
_> -iobase0 2e8 -etyp 1 -enadev 1

Display the full configuration database:

>>>isacfg -all

Modify the IRQ0 entry of an option:

>>>isacfg -mod -slot 1 -dev 0 -irq0 14

Remove an entry:

>>>isacfg -rm -slot 1 -dev 0


ICONFIG
Digital AlphaStation 255 Console Commands
ICONFIG

iconfig

Description

The ICONFIG utility is a subset of the ISACFG utility.  In the initial release of ICONFIG, only one type of each field (or option) can be set (for example, one IRQ or one address).  Future versions will include more functionality.  Use ISACFG if a particular field has more than one entry.

To use the forms-based interface of ICONFIG, start ICONFIG at the SRM prompt by typing

>>>iconfig[Return].


SRM ICONFIG Command Examples
ICONFIG Command Examples


ICONFIG Command Examples

>>>iconfig[Return]
ISA CONFIGURATION UTILITY

Name           I/O  IRQ  DMA  Mem       Length   Enabled

MOUSE          60   12                           Y
KBD            60   1                            Y
COM1           3f8  4                            Y
COM2           2f8  3                            Y
LPT1           3bc  7                            Y
FLOPPY         3f0  6    2                       Y

HELP: Enter up to 15 char device name
KEY HELP: Arrows/TAB to move, RET once to submit entry,
          RET 2nd time to exit

To add an ISA option, first enter the device's name, then move to the next field and enter its I/O address, and so forth.  For example, to add a DE205 Ethernet controller to the database, follow these steps in response to the HELP: prompts at the bottom of the display:

1.	Enter up to 15 char device name	DE200-LE [Tab]

2.	Enter i/o address in hex	300 [Tab]

3.	Enter IRQ channel in decimal	5 [Tab]

4.	Enter dma channel in decimal	[Tab]

5.	Enter memory address in hex	d0000 [Tab]

6.	Enter length of memory in hex	10000 [Tab]

7.	Enter N to disable, Y to enable	Y [Return]

When you press [Return], the entry is submitted and checked for conflicts.  If conflicts exist, a message is displayed.  For example, if you entered an IRQ value of 8 instead of 5, the following message is displayed:

ISACFG MESSAGE: ERROR: IRQ conflict with reserved IRQ values (0,2,8,11 or 13)

If you entered a DMA value of 2 rather than nothing, the following message is displayed:

ISACFG MESSAGE: ERROR: DMA conflict with slot 0 dev 5

You can delete an entire entry by using the [Backspace] key.


EWRK3 Configuration Utility
Digital AlphaStation 255 Console Commands
EWRK3 Configuration Utility (EWRK3_CONFIG)

ewrk3_config [-curaddr <I/O base address>] . . .

Description

The DEC EtherWORKS 3 Turbo Plus Ethernet controller (DE205) uses on board EEROM to store information such as the I/O base address, IRQ, memory base address, and so forth.  For more information on the DE205 option refer to the DEC EtherWORKS 3 Turbo User Information (EK-LEMAC-OM).

Invoking "ewrk3_config" with no parameters searches the entire address space for DE205 modules and displays the addresses of all modules found.

Where:

<none>	Find all DE205 boards and display their I/O Base address
-curaddr	The current hex I/O base address of the module being changed
-ioaddr	The hex I/O base address to change the current module to
-irq	The decimal IRQ value (valid values are 5, 10 or 15)
-fbus	Fast bus enable
-ena16	16 bit bus enable
-memaddr	Base memory address the board should respond to
-bufsize	Buffer size of the memory address (2K, 32K or 64K)
-swflag	Software flag field
-netmgt	Net management field
-default	Set the board back to the default settings
-show	Displays the entire EEROM for the board


EWRK3_CONFIG Command Examples


EWRK3_CONFIG Command Examples

Locate the DE205 boards currently installed:

>>>ewrk3_config

found board addr=300

Change the address of the DE205 board at I/O base address 300h:

>>>ewrk3_config -curaddr 300 -ioaddr 320

Change the IRQ of the DE205 to 10:

>>>ewrk3_config -curaddr 300 -irq 10


Setting the Default Console and Updating the Firmware

Digital AlphaStation 255 Console Commands

Updating or Changing the Console Firmware

The Digital AlphaStation 255 may have either the AlphaBIOS or SRM console firmware loaded into the flashROM.  Use this procedure to change from the SRM to AlphaBIOS or the AlphaBIOS to SRM console firmware.  The procedure can also be used to update the flashROM contents.

The Update utility contains three images: the Update utility itself, the SRM image, and the AlphaBIOS image.  When running the Update utility from the AlphaBIOS or SRM firmware, it will use the existing console port (either the graphic port or the serial line port).  Firmware update are available on the Alpha AXP(TM) Systems Firmware Update CD-ROM.  Firmware can also be loaded from appropriately formatted floppy diskettes.  The SRM firmware uses a floppy with an Alpha boot block.  The AlphaBIOS firmware uses a FAT formatted update floppy.

The following procedure shows the update occurring from the SRM console.  If the system is running AlphaBIOS firmware, do Steps 1 and 2.  Then from the AlphaBIOS Setup screen, select Upgrade AlphaBIOS and go to Step 5.

	Action	Response
1.	Make sure the Flash write enable switch (3) on the motherboard is switched to the OFF position.  This is the default position.	None.
2.	Insert the Firmware Update CD-ROM or a floppy diskette containing the update (must have an Alpha boot block).	None.
3.	Use the show device command to identify the device ID of the CD-drive. >>>show device	dka0.0.0.6.0   DKA0   RZ26L  440C dka400.4.0.6.0 DKA400 RRD45  0064 dva0.0.0.0.1   DVA0 ewa0.0.0.1.1   EWA0   08-00-2B-38-67-6B pka0.7.0.6.0   PKA0   SCSI Bus ID 7
4.	If floppy type >>>boot -fl 0,a0 dva0  or if CD-ROM, type >>>boot -fl 0,a0 dka400	From the SRM console, boot the floppy. The following prompt displays: BOOTFILE:
5.	Enter the directory and filename of the AlphaStation 255 firmware: BOOTFILE: [alpha255]as255_vx_x.exe	Where vx_x is the version of the firmware.  The following is displayed: apu-version 959328854  ** Firmware Update Utility VX.X ** ** System Type: AlphaStation 255 ** Update Verify List Show Dump Verbose Nverbose Debug Ndebug ? Apu->
6.	Start the firmware update by typing: Apu-> update To change from the SRM firmware to the AlphaBIOS firmware, type: Apu-> update arc Or, to switch from AlphaBIOS to SRM, type: Apu-> update srm	The currently loaded console firmware (SRM in this case) will be updated when no parameter is specified after the update command.  If update arc was typed in, the SRM firmware will be replaced by the AlphaBIOS firmware. APU-I *** ROM Contents will be destroyed APU-I Are you ready to Program Device? (y/n)
7.	If you are ready, enter: y	APU-I Programming device APU-I Programming device completed APU-I Programming device APU-I Programming device completed Apu->
8.	Apu-> quit	All done.
9.	Power cycle the system	The system restarts with the newly loaded firmware.
NOTE: Commands such as Dump, List, Show, and Verify must have verbose mode enabled for the output to be displayed.  Type the Verbose command at the Apu-> prompt to enter verbose mode.


SRM Security Features

Digital AlphaStation 255 Console Commands

SRM Security Features

The SRM console firmware contains console security features intended to prevent unauthorized personnel from modifying the system parameters or otherwise tampering with the system from the console. The security features include new commands and new parameters to some existing commands. The following two console modes are supported:

  Secure mode allows you to perform the boot command (with stored parameters) and the login commands.

  User mode allows you to perform all SRM console commands.

Note:  The security features work only if access to the system hardware is denied to unauthorized personnel.  Be sure to keep the top cover of the system locked and make the key available only to authorized personnel.

Security Commands

  Set password

  Set secure

  Login

  Clear password

If the user forgets the password, there is only one recovery mechanism.  The user must:

1.  Power the system off.

2.  Open the system box.

3.  Set the configuration DIP switches to erase NVRAM (Switches 1 and 2 to ON).

4.  Power the system on and wait for the console to start.

5. Power the system off.

6.  Reset the configuration dip switches to the original settings (1 and 2 OFF).

7.  Put the system top and side covers on and make them secure.

8.  Power the system on and console will now be in user mode

In addition to clearing out the secure mode password, all environment variables will be cleared and must be reestablished by the user.  For this reason, if the user should decide to use secure mode, it would be useful for the user to keep a list of any environment variables he set along with the values they were set to.  That way the environment variables can be re-established if the user must clear the NVRAM to reset the console to user mode.

Secure Mode Functions

Secure mode allows you to perform only the boot command (using the stored parameters) and login, continue and start commands.

boot

When the console is in the secure mode, the boot command will not accept command line parameters. The console will boot using the environment variables stored in NVRAM (boot_ file, bootdef_dev, boot_flags).

After a successful boot, the console is secured if there is a valid password. The boot command will accept parameters when the console is not in secure mode.


SRM Set Password Command
Digital AlphaStation 255 Console Commands
Set Password Command

set password

Description

The set password command allows you to set the console password for the first time or to change an existing password. You do not have to set the password if you do not wish to operate in secure mode.

  If the password has not been set, the console prompts  you for the new password and verification.

  If the password has been set previously, the console prompts you for the new password and verification, then prompts you for the old password. The password is not changed if the validation password entered does not match the existing password in the NVRAM.

The password length must be between 15 and 30 alphanumeric characters. Any characters entered after the 30th character are truncated and are not stored.


SRM Set Password Command Examples
Set Password Command Examples


Set Password Command Examples

>>> set password Please enter the password: < password is not echoed > Please enter the password again: < validation is not echoed > >>>	Entering a password for the first time.
>>> set password  Please enter the password: Please enter the password again: Now enter the old password: >>>	Changing an existing password.
>>> set password Please enter the password: < input is not echoed > Password length must be between 15 and 30 characters  >>>	The password entered was too short.
>>> set password Please enter the password: < password is not echoed >  Please enter the password again: < validation is not echoed >  Validation error  >>>	The password failed the validation test.


SRM Set Secure Command
Digital AlphaStation 255 Console Commands
Set Secure Command

set secure

Description

The set secure command allows you to enable the security features without requiring you to restart the console. If the password has been set, the console will be secured and only the start, continue, boot (using the stored parameters), and login commands can be performed. If the password has not been set, you are prompted to set the password. See the set password command for instructions.


SRM Set Secure Command Examples
Set Secure Command Examples


Set Secure Command Examples

>>> set secure Console is secure >>> >>> show boot_file Console is secure	This example shows set secure when a password has already been set.
>>> set secure Secure not set. Please set the password. >>>	This example shows set secure when a password has not been set.


SRM Login Command
Digital AlphaStation 255 Console Commands
Login Command

login

Description

The login command allows you to turn off the security features and gain access to all of the SRM console commands during a particular session.  The system automatically returns to secure mode as soon as you enter the boot command or when you initialize the system.

The login command works as follows: When you enter login, you are prompted for the current system password.  If no password has been set, you are prompted that there is no password in NVRAM.  You do not have to set a password if you do not wish to.

If the password has been set, the following prompt is  displayed:

Please enter the password:

If the password you enter matches the stored password, the console is no longer in the secure mode and all of the console commands can  be performed.


SRM Login Command Examples
Login Command Examples


Login Command Examples

>>> login Secure not set. Please set the password.  >>>	This example shows a valid login when the secure feature is not set.
>>> login  Please enter the password: < password is not echoed > >>>	This example shows a valid login when the secure feature is set.
>>> login Please enter the password: < password is not echoed >  Invalid password >>>	This example shows an invalid login when the secure feature is set.


SRM Clear Password Command
Digital AlphaStation 255 Console Commands
Clear Password Command

clear password

Description

The clear password command clears the environment variable, password, setting it to zero.  This command is used when you want access to all of the SRM console commands, but the system is in secure mode.  In order to use clear password, you must know the current password.

To clear the password without knowing the current password, you must have access to the configuration switches inside the system.


SRM Clear Password Command Examples
Clear Password Command Examples


Clear Password Command Examples

>>> clear password  Please enter the password: < enter password (not echoed) >  Password successfully cleared  >>>	This example shows a successful clear password command.  The command was entered with a valid password.
>>> clear password  Please enter the password: < invalid password entered (not echoed) >  Console is secure  >>>	In this example, the clear password command was entered with an invalid password